?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ixgbevf: Fix checksum error when using stacked vlan
[linux/fpc-iii.git] / sound / soc / fsl / fsl_spdif.c
blobaf0429421fc8b4997874777acf58950908ec317f
1 /*
2 * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
3 *
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
5 *
6 * Based on stmp3xxx_spdif_dai.c
7 * Vladimir Barinov <vbarinov@embeddedalley.com>
8 * Copyright 2008 SigmaTel, Inc
9 * Copyright 2008 Embedded Alley Solutions, Inc
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 */
15
16 #include <linux/bitrev.h>
17 #include <linux/clk.h>
18 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22 #include <linux/regmap.h>
23
24 #include <sound/asoundef.h>
25 #include <sound/dmaengine_pcm.h>
26 #include <sound/soc.h>
27
28 #include "fsl_spdif.h"
29 #include "imx-pcm.h"
30
31 #define FSL_SPDIF_TXFIFO_WML 0x8
32 #define FSL_SPDIF_RXFIFO_WML 0x8
33
34 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
35 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
36 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
37 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
38 INT_LOSS_LOCK | INT_DPLL_LOCKED)
39
40 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
41
42 /* Index list for the values that has if (DPLL Locked) condition */
43 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
44 #define SRPC_NODPLL_START1 0x5
45 #define SRPC_NODPLL_START2 0xc
46
47 #define DEFAULT_RXCLK_SRC 1
48
49 /*
50 * SPDIF control structure
51 * Defines channel status, subcode and Q sub
52 */
53 struct spdif_mixer_control {
54 /* spinlock to access control data */
55 spinlock_t ctl_lock;
56
57 /* IEC958 channel tx status bit */
58 unsigned char ch_status[4];
59
60 /* User bits */
61 unsigned char subcode[2 * SPDIF_UBITS_SIZE];
62
63 /* Q subcode part of user bits */
64 unsigned char qsub[2 * SPDIF_QSUB_SIZE];
65
66 /* Buffer offset for U/Q */
67 u32 upos;
68 u32 qpos;
69
70 /* Ready buffer index of the two buffers */
71 u32 ready_buf;
72 };
73
74 /**
75 * fsl_spdif_priv: Freescale SPDIF private data
76 *
77 * @fsl_spdif_control: SPDIF control data
78 * @cpu_dai_drv: cpu dai driver
79 * @pdev: platform device pointer
80 * @regmap: regmap handler
81 * @dpll_locked: dpll lock flag
82 * @txrate: the best rates for playback
83 * @txclk_df: STC_TXCLK_DF dividers value for playback
84 * @sysclk_df: STC_SYSCLK_DF dividers value for playback
85 * @txclk_src: STC_TXCLK_SRC values for playback
86 * @rxclk_src: SRPC_CLKSRC_SEL values for capture
87 * @txclk: tx clock sources for playback
88 * @rxclk: rx clock sources for capture
89 * @coreclk: core clock for register access via DMA
90 * @sysclk: system clock for rx clock rate measurement
91 * @dma_params_tx: DMA parameters for transmit channel
92 * @dma_params_rx: DMA parameters for receive channel
93 * @name: driver name
94 */
95 struct fsl_spdif_priv {
96 struct spdif_mixer_control fsl_spdif_control;
97 struct snd_soc_dai_driver cpu_dai_drv;
98 struct platform_device *pdev;
99 struct regmap *regmap;
100 bool dpll_locked;
101 u32 txrate[SPDIF_TXRATE_MAX];
102 u8 txclk_df[SPDIF_TXRATE_MAX];
103 u8 sysclk_df[SPDIF_TXRATE_MAX];
104 u8 txclk_src[SPDIF_TXRATE_MAX];
105 u8 rxclk_src;
106 struct clk *txclk[SPDIF_TXRATE_MAX];
107 struct clk *rxclk;
108 struct clk *coreclk;
109 struct clk *sysclk;
110 struct snd_dmaengine_dai_dma_data dma_params_tx;
111 struct snd_dmaengine_dai_dma_data dma_params_rx;
112
113 /* The name space will be allocated dynamically */
114 char name[0];
115 };
116
117
118 /* DPLL locked and lock loss interrupt handler */
119 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
120 {
121 struct regmap *regmap = spdif_priv->regmap;
122 struct platform_device *pdev = spdif_priv->pdev;
123 u32 locked;
124
125 regmap_read(regmap, REG_SPDIF_SRPC, &locked);
126 locked &= SRPC_DPLL_LOCKED;
127
128 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
129 locked ? "locked" : "loss lock");
130
131 spdif_priv->dpll_locked = locked ? true : false;
132 }
133
134 /* Receiver found illegal symbol interrupt handler */
135 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
136 {
137 struct regmap *regmap = spdif_priv->regmap;
138 struct platform_device *pdev = spdif_priv->pdev;
139
140 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
141
142 /* Clear illegal symbol if DPLL unlocked since no audio stream */
143 if (!spdif_priv->dpll_locked)
144 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
145 }
146
147 /* U/Q Channel receive register full */
148 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
149 {
150 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
151 struct regmap *regmap = spdif_priv->regmap;
152 struct platform_device *pdev = spdif_priv->pdev;
153 u32 *pos, size, val, reg;
154
155 switch (name) {
156 case 'U':
157 pos = &ctrl->upos;
158 size = SPDIF_UBITS_SIZE;
159 reg = REG_SPDIF_SRU;
160 break;
161 case 'Q':
162 pos = &ctrl->qpos;
163 size = SPDIF_QSUB_SIZE;
164 reg = REG_SPDIF_SRQ;
165 break;
166 default:
167 dev_err(&pdev->dev, "unsupported channel name\n");
168 return;
169 }
170
171 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
172
173 if (*pos >= size * 2) {
174 *pos = 0;
175 } else if (unlikely((*pos % size) + 3 > size)) {
176 dev_err(&pdev->dev, "User bit receivce buffer overflow\n");
177 return;
178 }
179
180 regmap_read(regmap, reg, &val);
181 ctrl->subcode[*pos++] = val >> 16;
182 ctrl->subcode[*pos++] = val >> 8;
183 ctrl->subcode[*pos++] = val;
184 }
185
186 /* U/Q Channel sync found */
187 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
188 {
189 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
190 struct platform_device *pdev = spdif_priv->pdev;
191
192 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
193
194 /* U/Q buffer reset */
195 if (ctrl->qpos == 0)
196 return;
197
198 /* Set ready to this buffer */
199 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
200 }
201
202 /* U/Q Channel framing error */
203 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
204 {
205 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
206 struct regmap *regmap = spdif_priv->regmap;
207 struct platform_device *pdev = spdif_priv->pdev;
208 u32 val;
209
210 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
211
212 /* Read U/Q data to clear the irq and do buffer reset */
213 regmap_read(regmap, REG_SPDIF_SRU, &val);
214 regmap_read(regmap, REG_SPDIF_SRQ, &val);
215
216 /* Drop this U/Q buffer */
217 ctrl->ready_buf = 0;
218 ctrl->upos = 0;
219 ctrl->qpos = 0;
220 }
221
222 /* Get spdif interrupt status and clear the interrupt */
223 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
224 {
225 struct regmap *regmap = spdif_priv->regmap;
226 u32 val, val2;
227
228 regmap_read(regmap, REG_SPDIF_SIS, &val);
229 regmap_read(regmap, REG_SPDIF_SIE, &val2);
230
231 regmap_write(regmap, REG_SPDIF_SIC, val & val2);
232
233 return val;
234 }
235
236 static irqreturn_t spdif_isr(int irq, void *devid)
237 {
238 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
239 struct platform_device *pdev = spdif_priv->pdev;
240 u32 sis;
241
242 sis = spdif_intr_status_clear(spdif_priv);
243
244 if (sis & INT_DPLL_LOCKED)
245 spdif_irq_dpll_lock(spdif_priv);
246
247 if (sis & INT_TXFIFO_UNOV)
248 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
249
250 if (sis & INT_TXFIFO_RESYNC)
251 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
252
253 if (sis & INT_CNEW)
254 dev_dbg(&pdev->dev, "isr: cstatus new\n");
255
256 if (sis & INT_VAL_NOGOOD)
257 dev_dbg(&pdev->dev, "isr: validity flag no good\n");
258
259 if (sis & INT_SYM_ERR)
260 spdif_irq_sym_error(spdif_priv);
261
262 if (sis & INT_BIT_ERR)
263 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
264
265 if (sis & INT_URX_FUL)
266 spdif_irq_uqrx_full(spdif_priv, 'U');
267
268 if (sis & INT_URX_OV)
269 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
270
271 if (sis & INT_QRX_FUL)
272 spdif_irq_uqrx_full(spdif_priv, 'Q');
273
274 if (sis & INT_QRX_OV)
275 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
276
277 if (sis & INT_UQ_SYNC)
278 spdif_irq_uq_sync(spdif_priv);
279
280 if (sis & INT_UQ_ERR)
281 spdif_irq_uq_err(spdif_priv);
282
283 if (sis & INT_RXFIFO_UNOV)
284 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
285
286 if (sis & INT_RXFIFO_RESYNC)
287 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
288
289 if (sis & INT_LOSS_LOCK)
290 spdif_irq_dpll_lock(spdif_priv);
291
292 /* FIXME: Write Tx FIFO to clear TxEm */
293 if (sis & INT_TX_EM)
294 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
295
296 /* FIXME: Read Rx FIFO to clear RxFIFOFul */
297 if (sis & INT_RXFIFO_FUL)
298 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
299
300 return IRQ_HANDLED;
301 }
302
303 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
304 {
305 struct regmap *regmap = spdif_priv->regmap;
306 u32 val, cycle = 1000;
307
308 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
309
310 /*
311 * RESET bit would be cleared after finishing its reset procedure,
312 * which typically lasts 8 cycles. 1000 cycles will keep it safe.
313 */
314 do {
315 regmap_read(regmap, REG_SPDIF_SCR, &val);
316 } while ((val & SCR_SOFT_RESET) && cycle--);
317
318 if (cycle)
319 return 0;
320 else
321 return -EBUSY;
322 }
323
324 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
325 u8 mask, u8 cstatus)
326 {
327 ctrl->ch_status[3] &= ~mask;
328 ctrl->ch_status[3] |= cstatus & mask;
329 }
330
331 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
332 {
333 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
334 struct regmap *regmap = spdif_priv->regmap;
335 struct platform_device *pdev = spdif_priv->pdev;
336 u32 ch_status;
337
338 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
339 (bitrev8(ctrl->ch_status[1]) << 8) |
340 bitrev8(ctrl->ch_status[2]);
341 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
342
343 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
344
345 ch_status = bitrev8(ctrl->ch_status[3]) << 16;
346 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
347
348 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
349 }
350
351 /* Set SPDIF PhaseConfig register for rx clock */
352 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
353 enum spdif_gainsel gainsel, int dpll_locked)
354 {
355 struct regmap *regmap = spdif_priv->regmap;
356 u8 clksrc = spdif_priv->rxclk_src;
357
358 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
359 return -EINVAL;
360
361 regmap_update_bits(regmap, REG_SPDIF_SRPC,
362 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
363 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
364
365 return 0;
366 }
367
368 static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
369 int sample_rate)
370 {
371 struct snd_soc_pcm_runtime *rtd = substream->private_data;
372 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
373 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
374 struct regmap *regmap = spdif_priv->regmap;
375 struct platform_device *pdev = spdif_priv->pdev;
376 unsigned long csfs = 0;
377 u32 stc, mask, rate;
378 u8 clk, txclk_df, sysclk_df;
379 int ret;
380
381 switch (sample_rate) {
382 case 32000:
383 rate = SPDIF_TXRATE_32000;
384 csfs = IEC958_AES3_CON_FS_32000;
385 break;
386 case 44100:
387 rate = SPDIF_TXRATE_44100;
388 csfs = IEC958_AES3_CON_FS_44100;
389 break;
390 case 48000:
391 rate = SPDIF_TXRATE_48000;
392 csfs = IEC958_AES3_CON_FS_48000;
393 break;
394 case 96000:
395 rate = SPDIF_TXRATE_96000;
396 csfs = IEC958_AES3_CON_FS_96000;
397 break;
398 case 192000:
399 rate = SPDIF_TXRATE_192000;
400 csfs = IEC958_AES3_CON_FS_192000;
401 break;
402 default:
403 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
404 return -EINVAL;
405 }
406
407 clk = spdif_priv->txclk_src[rate];
408 if (clk >= STC_TXCLK_SRC_MAX) {
409 dev_err(&pdev->dev, "tx clock source is out of range\n");
410 return -EINVAL;
411 }
412
413 txclk_df = spdif_priv->txclk_df[rate];
414 if (txclk_df == 0) {
415 dev_err(&pdev->dev, "the txclk_df can't be zero\n");
416 return -EINVAL;
417 }
418
419 sysclk_df = spdif_priv->sysclk_df[rate];
420
421 /* Don't mess up the clocks from other modules */
422 if (clk != STC_TXCLK_SPDIF_ROOT)
423 goto clk_set_bypass;
424
425 /*
426 * The S/PDIF block needs a clock of 64 * fs * txclk_df.
427 * So request 64 * fs * (txclk_df + 1) to get rounded.
428 */
429 ret = clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (txclk_df + 1));
430 if (ret) {
431 dev_err(&pdev->dev, "failed to set tx clock rate\n");
432 return ret;
433 }
434
435 clk_set_bypass:
436 dev_dbg(&pdev->dev, "expected clock rate = %d\n",
437 (64 * sample_rate * txclk_df * sysclk_df));
438 dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
439 clk_get_rate(spdif_priv->txclk[rate]));
440
441 /* set fs field in consumer channel status */
442 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
443
444 /* select clock source and divisor */
445 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
446 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
447 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
448 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
449 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
450
451 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
452 spdif_priv->txrate[rate], sample_rate);
453
454 return 0;
455 }
456
457 static int fsl_spdif_startup(struct snd_pcm_substream *substream,
458 struct snd_soc_dai *cpu_dai)
459 {
460 struct snd_soc_pcm_runtime *rtd = substream->private_data;
461 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
462 struct platform_device *pdev = spdif_priv->pdev;
463 struct regmap *regmap = spdif_priv->regmap;
464 u32 scr, mask, i;
465 int ret;
466
467 /* Reset module and interrupts only for first initialization */
468 if (!cpu_dai->active) {
469 ret = clk_prepare_enable(spdif_priv->coreclk);
470 if (ret) {
471 dev_err(&pdev->dev, "failed to enable core clock\n");
472 return ret;
473 }
474
475 ret = spdif_softreset(spdif_priv);
476 if (ret) {
477 dev_err(&pdev->dev, "failed to soft reset\n");
478 goto err;
479 }
480
481 /* Disable all the interrupts */
482 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
483 }
484
485 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
486 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
487 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
488 SCR_TXFIFO_FSEL_IF8;
489 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
490 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
491 SCR_TXFIFO_FSEL_MASK;
492 for (i = 0; i < SPDIF_TXRATE_MAX; i++)
493 clk_prepare_enable(spdif_priv->txclk[i]);
494 } else {
495 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
496 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
497 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
498 clk_prepare_enable(spdif_priv->rxclk);
499 }
500 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
501
502 /* Power up SPDIF module */
503 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
504
505 return 0;
506
507 err:
508 clk_disable_unprepare(spdif_priv->coreclk);
509
510 return ret;
511 }
512
513 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
514 struct snd_soc_dai *cpu_dai)
515 {
516 struct snd_soc_pcm_runtime *rtd = substream->private_data;
517 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
518 struct regmap *regmap = spdif_priv->regmap;
519 u32 scr, mask, i;
520
521 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
522 scr = 0;
523 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
524 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
525 SCR_TXFIFO_FSEL_MASK;
526 for (i = 0; i < SPDIF_TXRATE_MAX; i++)
527 clk_disable_unprepare(spdif_priv->txclk[i]);
528 } else {
529 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
530 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
531 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
532 clk_disable_unprepare(spdif_priv->rxclk);
533 }
534 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
535
536 /* Power down SPDIF module only if tx&rx are both inactive */
537 if (!cpu_dai->active) {
538 spdif_intr_status_clear(spdif_priv);
539 regmap_update_bits(regmap, REG_SPDIF_SCR,
540 SCR_LOW_POWER, SCR_LOW_POWER);
541 clk_disable_unprepare(spdif_priv->coreclk);
542 }
543 }
544
545 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
546 struct snd_pcm_hw_params *params,
547 struct snd_soc_dai *dai)
548 {
549 struct snd_soc_pcm_runtime *rtd = substream->private_data;
550 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
551 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
552 struct platform_device *pdev = spdif_priv->pdev;
553 u32 sample_rate = params_rate(params);
554 int ret = 0;
555
556 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
557 ret = spdif_set_sample_rate(substream, sample_rate);
558 if (ret) {
559 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
560 __func__, sample_rate);
561 return ret;
562 }
563 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
564 IEC958_AES3_CON_CLOCK_1000PPM);
565 spdif_write_channel_status(spdif_priv);
566 } else {
567 /* Setup rx clock source */
568 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
569 }
570
571 return ret;
572 }
573
574 static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
575 int cmd, struct snd_soc_dai *dai)
576 {
577 struct snd_soc_pcm_runtime *rtd = substream->private_data;
578 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
579 struct regmap *regmap = spdif_priv->regmap;
580 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
581 u32 intr = SIE_INTR_FOR(tx);
582 u32 dmaen = SCR_DMA_xX_EN(tx);
583
584 switch (cmd) {
585 case SNDRV_PCM_TRIGGER_START:
586 case SNDRV_PCM_TRIGGER_RESUME:
587 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
588 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
589 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
590 break;
591 case SNDRV_PCM_TRIGGER_STOP:
592 case SNDRV_PCM_TRIGGER_SUSPEND:
593 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
594 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
595 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
596 break;
597 default:
598 return -EINVAL;
599 }
600
601 return 0;
602 }
603
604 static struct snd_soc_dai_ops fsl_spdif_dai_ops = {
605 .startup = fsl_spdif_startup,
606 .hw_params = fsl_spdif_hw_params,
607 .trigger = fsl_spdif_trigger,
608 .shutdown = fsl_spdif_shutdown,
609 };
610
611
612 /*
613 * FSL SPDIF IEC958 controller(mixer) functions
614 *
615 * Channel status get/put control
616 * User bit value get/put control
617 * Valid bit value get control
618 * DPLL lock status get control
619 * User bit sync mode selection control
620 */
621
622 static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
623 struct snd_ctl_elem_info *uinfo)
624 {
625 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
626 uinfo->count = 1;
627
628 return 0;
629 }
630
631 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
632 struct snd_ctl_elem_value *uvalue)
633 {
634 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
635 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
636 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
637
638 uvalue->value.iec958.status[0] = ctrl->ch_status[0];
639 uvalue->value.iec958.status[1] = ctrl->ch_status[1];
640 uvalue->value.iec958.status[2] = ctrl->ch_status[2];
641 uvalue->value.iec958.status[3] = ctrl->ch_status[3];
642
643 return 0;
644 }
645
646 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
647 struct snd_ctl_elem_value *uvalue)
648 {
649 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
650 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
651 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
652
653 ctrl->ch_status[0] = uvalue->value.iec958.status[0];
654 ctrl->ch_status[1] = uvalue->value.iec958.status[1];
655 ctrl->ch_status[2] = uvalue->value.iec958.status[2];
656 ctrl->ch_status[3] = uvalue->value.iec958.status[3];
657
658 spdif_write_channel_status(spdif_priv);
659
660 return 0;
661 }
662
663 /* Get channel status from SPDIF_RX_CCHAN register */
664 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
665 struct snd_ctl_elem_value *ucontrol)
666 {
667 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
668 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
669 struct regmap *regmap = spdif_priv->regmap;
670 u32 cstatus, val;
671
672 regmap_read(regmap, REG_SPDIF_SIS, &val);
673 if (!(val & INT_CNEW))
674 return -EAGAIN;
675
676 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
677 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
678 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
679 ucontrol->value.iec958.status[2] = cstatus & 0xFF;
680
681 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
682 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
683 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
684 ucontrol->value.iec958.status[5] = cstatus & 0xFF;
685
686 /* Clear intr */
687 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
688
689 return 0;
690 }
691
692 /*
693 * Get User bits (subcode) from chip value which readed out
694 * in UChannel register.
695 */
696 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
697 struct snd_ctl_elem_value *ucontrol)
698 {
699 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
700 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
701 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
702 unsigned long flags;
703 int ret = -EAGAIN;
704
705 spin_lock_irqsave(&ctrl->ctl_lock, flags);
706 if (ctrl->ready_buf) {
707 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
708 memcpy(&ucontrol->value.iec958.subcode[0],
709 &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
710 ret = 0;
711 }
712 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
713
714 return ret;
715 }
716
717 /* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */
718 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
719 struct snd_ctl_elem_info *uinfo)
720 {
721 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
722 uinfo->count = SPDIF_QSUB_SIZE;
723
724 return 0;
725 }
726
727 /* Get Q subcode from chip value which readed out in QChannel register */
728 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
729 struct snd_ctl_elem_value *ucontrol)
730 {
731 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
732 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
733 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
734 unsigned long flags;
735 int ret = -EAGAIN;
736
737 spin_lock_irqsave(&ctrl->ctl_lock, flags);
738 if (ctrl->ready_buf) {
739 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
740 memcpy(&ucontrol->value.bytes.data[0],
741 &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
742 ret = 0;
743 }
744 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
745
746 return ret;
747 }
748
749 /* Valid bit infomation */
750 static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
751 struct snd_ctl_elem_info *uinfo)
752 {
753 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
754 uinfo->count = 1;
755 uinfo->value.integer.min = 0;
756 uinfo->value.integer.max = 1;
757
758 return 0;
759 }
760
761 /* Get valid good bit from interrupt status register */
762 static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
763 struct snd_ctl_elem_value *ucontrol)
764 {
765 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
766 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
767 struct regmap *regmap = spdif_priv->regmap;
768 u32 val;
769
770 regmap_read(regmap, REG_SPDIF_SIS, &val);
771 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
772 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
773
774 return 0;
775 }
776
777 /* DPLL lock infomation */
778 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
779 struct snd_ctl_elem_info *uinfo)
780 {
781 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
782 uinfo->count = 1;
783 uinfo->value.integer.min = 16000;
784 uinfo->value.integer.max = 96000;
785
786 return 0;
787 }
788
789 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
790 24, 16, 12, 8, 6, 4, 3,
791 };
792
793 /* Get RX data clock rate given the SPDIF bus_clk */
794 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
795 enum spdif_gainsel gainsel)
796 {
797 struct regmap *regmap = spdif_priv->regmap;
798 struct platform_device *pdev = spdif_priv->pdev;
799 u64 tmpval64, busclk_freq = 0;
800 u32 freqmeas, phaseconf;
801 u8 clksrc;
802
803 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
804 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
805
806 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
807
808 /* Get bus clock from system */
809 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
810 busclk_freq = clk_get_rate(spdif_priv->sysclk);
811
812 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
813 tmpval64 = (u64) busclk_freq * freqmeas;
814 do_div(tmpval64, gainsel_multi[gainsel] * 1024);
815 do_div(tmpval64, 128 * 1024);
816
817 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
818 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
819 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
820
821 return (int)tmpval64;
822 }
823
824 /*
825 * Get DPLL lock or not info from stable interrupt status register.
826 * User application must use this control to get locked,
827 * then can do next PCM operation
828 */
829 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
830 struct snd_ctl_elem_value *ucontrol)
831 {
832 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
833 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
834 int rate = 0;
835
836 if (spdif_priv->dpll_locked)
837 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
838
839 ucontrol->value.integer.value[0] = rate;
840
841 return 0;
842 }
843
844 /* User bit sync mode info */
845 static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
846 struct snd_ctl_elem_info *uinfo)
847 {
848 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
849 uinfo->count = 1;
850 uinfo->value.integer.min = 0;
851 uinfo->value.integer.max = 1;
852
853 return 0;
854 }
855
856 /*
857 * User bit sync mode:
858 * 1 CD User channel subcode
859 * 0 Non-CD data
860 */
861 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
862 struct snd_ctl_elem_value *ucontrol)
863 {
864 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
865 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
866 struct regmap *regmap = spdif_priv->regmap;
867 u32 val;
868
869 regmap_read(regmap, REG_SPDIF_SRCD, &val);
870 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
871
872 return 0;
873 }
874
875 /*
876 * User bit sync mode:
877 * 1 CD User channel subcode
878 * 0 Non-CD data
879 */
880 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
881 struct snd_ctl_elem_value *ucontrol)
882 {
883 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
884 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
885 struct regmap *regmap = spdif_priv->regmap;
886 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
887
888 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
889
890 return 0;
891 }
892
893 /* FSL SPDIF IEC958 controller defines */
894 static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
895 /* Status cchanel controller */
896 {
897 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
898 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
899 .access = SNDRV_CTL_ELEM_ACCESS_READ |
900 SNDRV_CTL_ELEM_ACCESS_WRITE |
901 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
902 .info = fsl_spdif_info,
903 .get = fsl_spdif_pb_get,
904 .put = fsl_spdif_pb_put,
905 },
906 {
907 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
908 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
909 .access = SNDRV_CTL_ELEM_ACCESS_READ |
910 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
911 .info = fsl_spdif_info,
912 .get = fsl_spdif_capture_get,
913 },
914 /* User bits controller */
915 {
916 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
917 .name = "IEC958 Subcode Capture Default",
918 .access = SNDRV_CTL_ELEM_ACCESS_READ |
919 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
920 .info = fsl_spdif_info,
921 .get = fsl_spdif_subcode_get,
922 },
923 {
924 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
925 .name = "IEC958 Q-subcode Capture Default",
926 .access = SNDRV_CTL_ELEM_ACCESS_READ |
927 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
928 .info = fsl_spdif_qinfo,
929 .get = fsl_spdif_qget,
930 },
931 /* Valid bit error controller */
932 {
933 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
934 .name = "IEC958 V-Bit Errors",
935 .access = SNDRV_CTL_ELEM_ACCESS_READ |
936 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
937 .info = fsl_spdif_vbit_info,
938 .get = fsl_spdif_vbit_get,
939 },
940 /* DPLL lock info get controller */
941 {
942 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
943 .name = "RX Sample Rate",
944 .access = SNDRV_CTL_ELEM_ACCESS_READ |
945 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
946 .info = fsl_spdif_rxrate_info,
947 .get = fsl_spdif_rxrate_get,
948 },
949 /* User bit sync mode set/get controller */
950 {
951 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
952 .name = "IEC958 USyncMode CDText",
953 .access = SNDRV_CTL_ELEM_ACCESS_READ |
954 SNDRV_CTL_ELEM_ACCESS_WRITE |
955 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
956 .info = fsl_spdif_usync_info,
957 .get = fsl_spdif_usync_get,
958 .put = fsl_spdif_usync_put,
959 },
960 };
961
962 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
963 {
964 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
965
966 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
967 &spdif_private->dma_params_rx);
968
969 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
970
971 return 0;
972 }
973
974 static struct snd_soc_dai_driver fsl_spdif_dai = {
975 .probe = &fsl_spdif_dai_probe,
976 .playback = {
977 .stream_name = "CPU-Playback",
978 .channels_min = 2,
979 .channels_max = 2,
980 .rates = FSL_SPDIF_RATES_PLAYBACK,
981 .formats = FSL_SPDIF_FORMATS_PLAYBACK,
982 },
983 .capture = {
984 .stream_name = "CPU-Capture",
985 .channels_min = 2,
986 .channels_max = 2,
987 .rates = FSL_SPDIF_RATES_CAPTURE,
988 .formats = FSL_SPDIF_FORMATS_CAPTURE,
989 },
990 .ops = &fsl_spdif_dai_ops,
991 };
992
993 static const struct snd_soc_component_driver fsl_spdif_component = {
994 .name = "fsl-spdif",
995 };
996
997 /* FSL SPDIF REGMAP */
998
999 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
1000 {
1001 switch (reg) {
1002 case REG_SPDIF_SCR:
1003 case REG_SPDIF_SRCD:
1004 case REG_SPDIF_SRPC:
1005 case REG_SPDIF_SIE:
1006 case REG_SPDIF_SIS:
1007 case REG_SPDIF_SRL:
1008 case REG_SPDIF_SRR:
1009 case REG_SPDIF_SRCSH:
1010 case REG_SPDIF_SRCSL:
1011 case REG_SPDIF_SRU:
1012 case REG_SPDIF_SRQ:
1013 case REG_SPDIF_STCSCH:
1014 case REG_SPDIF_STCSCL:
1015 case REG_SPDIF_SRFM:
1016 case REG_SPDIF_STC:
1017 return true;
1018 default:
1019 return false;
1020 }
1021 }
1022
1023 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
1024 {
1025 switch (reg) {
1026 case REG_SPDIF_SCR:
1027 case REG_SPDIF_SRCD:
1028 case REG_SPDIF_SRPC:
1029 case REG_SPDIF_SIE:
1030 case REG_SPDIF_SIC:
1031 case REG_SPDIF_STL:
1032 case REG_SPDIF_STR:
1033 case REG_SPDIF_STCSCH:
1034 case REG_SPDIF_STCSCL:
1035 case REG_SPDIF_STC:
1036 return true;
1037 default:
1038 return false;
1039 }
1040 }
1041
1042 static const struct regmap_config fsl_spdif_regmap_config = {
1043 .reg_bits = 32,
1044 .reg_stride = 4,
1045 .val_bits = 32,
1046
1047 .max_register = REG_SPDIF_STC,
1048 .readable_reg = fsl_spdif_readable_reg,
1049 .writeable_reg = fsl_spdif_writeable_reg,
1050 };
1051
1052 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
1053 struct clk *clk, u64 savesub,
1054 enum spdif_txrate index, bool round)
1055 {
1056 const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1057 bool is_sysclk = clk == spdif_priv->sysclk;
1058 u64 rate_ideal, rate_actual, sub;
1059 u32 sysclk_dfmin, sysclk_dfmax;
1060 u32 txclk_df, sysclk_df, arate;
1061
1062 /* The sysclk has an extra divisor [2, 512] */
1063 sysclk_dfmin = is_sysclk ? 2 : 1;
1064 sysclk_dfmax = is_sysclk ? 512 : 1;
1065
1066 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
1067 for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
1068 rate_ideal = rate[index] * (txclk_df + 1) * 64;
1069 if (round)
1070 rate_actual = clk_round_rate(clk, rate_ideal);
1071 else
1072 rate_actual = clk_get_rate(clk);
1073
1074 arate = rate_actual / 64;
1075 arate /= txclk_df * sysclk_df;
1076
1077 if (arate == rate[index]) {
1078 /* We are lucky */
1079 savesub = 0;
1080 spdif_priv->txclk_df[index] = txclk_df;
1081 spdif_priv->sysclk_df[index] = sysclk_df;
1082 spdif_priv->txrate[index] = arate;
1083 goto out;
1084 } else if (arate / rate[index] == 1) {
1085 /* A little bigger than expect */
1086 sub = (u64)(arate - rate[index]) * 100000;
1087 do_div(sub, rate[index]);
1088 if (sub >= savesub)
1089 continue;
1090 savesub = sub;
1091 spdif_priv->txclk_df[index] = txclk_df;
1092 spdif_priv->sysclk_df[index] = sysclk_df;
1093 spdif_priv->txrate[index] = arate;
1094 } else if (rate[index] / arate == 1) {
1095 /* A little smaller than expect */
1096 sub = (u64)(rate[index] - arate) * 100000;
1097 do_div(sub, rate[index]);
1098 if (sub >= savesub)
1099 continue;
1100 savesub = sub;
1101 spdif_priv->txclk_df[index] = txclk_df;
1102 spdif_priv->sysclk_df[index] = sysclk_df;
1103 spdif_priv->txrate[index] = arate;
1104 }
1105 }
1106 }
1107
1108 out:
1109 return savesub;
1110 }
1111
1112 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
1113 enum spdif_txrate index)
1114 {
1115 const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1116 struct platform_device *pdev = spdif_priv->pdev;
1117 struct device *dev = &pdev->dev;
1118 u64 savesub = 100000, ret;
1119 struct clk *clk;
1120 char tmp[16];
1121 int i;
1122
1123 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1124 sprintf(tmp, "rxtx%d", i);
1125 clk = devm_clk_get(&pdev->dev, tmp);
1126 if (IS_ERR(clk)) {
1127 dev_err(dev, "no rxtx%d clock in devicetree\n", i);
1128 return PTR_ERR(clk);
1129 }
1130 if (!clk_get_rate(clk))
1131 continue;
1132
1133 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
1134 i == STC_TXCLK_SPDIF_ROOT);
1135 if (savesub == ret)
1136 continue;
1137
1138 savesub = ret;
1139 spdif_priv->txclk[index] = clk;
1140 spdif_priv->txclk_src[index] = i;
1141
1142 /* To quick catch a divisor, we allow a 0.1% deviation */
1143 if (savesub < 100)
1144 break;
1145 }
1146
1147 dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
1148 spdif_priv->txclk_src[index], rate[index]);
1149 dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n",
1150 spdif_priv->txclk_df[index], rate[index]);
1151 if (spdif_priv->txclk[index] == spdif_priv->sysclk)
1152 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n",
1153 spdif_priv->sysclk_df[index], rate[index]);
1154 dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n",
1155 rate[index], spdif_priv->txrate[index]);
1156
1157 return 0;
1158 }
1159
1160 static int fsl_spdif_probe(struct platform_device *pdev)
1161 {
1162 struct device_node *np = pdev->dev.of_node;
1163 struct fsl_spdif_priv *spdif_priv;
1164 struct spdif_mixer_control *ctrl;
1165 struct resource *res;
1166 void __iomem *regs;
1167 int irq, ret, i;
1168
1169 if (!np)
1170 return -ENODEV;
1171
1172 spdif_priv = devm_kzalloc(&pdev->dev,
1173 sizeof(struct fsl_spdif_priv) + strlen(np->name) + 1,
1174 GFP_KERNEL);
1175 if (!spdif_priv)
1176 return -ENOMEM;
1177
1178 strcpy(spdif_priv->name, np->name);
1179
1180 spdif_priv->pdev = pdev;
1181
1182 /* Initialize this copy of the CPU DAI driver structure */
1183 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
1184 spdif_priv->cpu_dai_drv.name = spdif_priv->name;
1185
1186 /* Get the addresses and IRQ */
1187 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1188 regs = devm_ioremap_resource(&pdev->dev, res);
1189 if (IS_ERR(regs))
1190 return PTR_ERR(regs);
1191
1192 spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
1193 "core", regs, &fsl_spdif_regmap_config);
1194 if (IS_ERR(spdif_priv->regmap)) {
1195 dev_err(&pdev->dev, "regmap init failed\n");
1196 return PTR_ERR(spdif_priv->regmap);
1197 }
1198
1199 irq = platform_get_irq(pdev, 0);
1200 if (irq < 0) {
1201 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1202 return irq;
1203 }
1204
1205 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
1206 spdif_priv->name, spdif_priv);
1207 if (ret) {
1208 dev_err(&pdev->dev, "could not claim irq %u\n", irq);
1209 return ret;
1210 }
1211
1212 /* Get system clock for rx clock rate calculation */
1213 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5");
1214 if (IS_ERR(spdif_priv->sysclk)) {
1215 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
1216 return PTR_ERR(spdif_priv->sysclk);
1217 }
1218
1219 /* Get core clock for data register access via DMA */
1220 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
1221 if (IS_ERR(spdif_priv->coreclk)) {
1222 dev_err(&pdev->dev, "no core clock in devicetree\n");
1223 return PTR_ERR(spdif_priv->coreclk);
1224 }
1225
1226 /* Select clock source for rx/tx clock */
1227 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
1228 if (IS_ERR(spdif_priv->rxclk)) {
1229 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
1230 return PTR_ERR(spdif_priv->rxclk);
1231 }
1232 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
1233
1234 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
1235 ret = fsl_spdif_probe_txclk(spdif_priv, i);
1236 if (ret)
1237 return ret;
1238 }
1239
1240 /* Initial spinlock for control data */
1241 ctrl = &spdif_priv->fsl_spdif_control;
1242 spin_lock_init(&ctrl->ctl_lock);
1243
1244 /* Init tx channel status default value */
1245 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
1246 IEC958_AES0_CON_EMPHASIS_5015;
1247 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
1248 ctrl->ch_status[2] = 0x00;
1249 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
1250 IEC958_AES3_CON_CLOCK_1000PPM;
1251
1252 spdif_priv->dpll_locked = false;
1253
1254 spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
1255 spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
1256 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
1257 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
1258
1259 /* Register with ASoC */
1260 dev_set_drvdata(&pdev->dev, spdif_priv);
1261
1262 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
1263 &spdif_priv->cpu_dai_drv, 1);
1264 if (ret) {
1265 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1266 return ret;
1267 }
1268
1269 ret = imx_pcm_dma_init(pdev);
1270 if (ret)
1271 dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
1272
1273 return ret;
1274 }
1275
1276 static const struct of_device_id fsl_spdif_dt_ids[] = {
1277 { .compatible = "fsl,imx35-spdif", },
1278 { .compatible = "fsl,vf610-spdif", },
1279 {}
1280 };
1281 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
1282
1283 static struct platform_driver fsl_spdif_driver = {
1284 .driver = {
1285 .name = "fsl-spdif-dai",
1286 .of_match_table = fsl_spdif_dt_ids,
1287 },
1288 .probe = fsl_spdif_probe,
1289 };
1290
1291 module_platform_driver(fsl_spdif_driver);
1292
1293 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1294 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
1295 MODULE_LICENSE("GPL v2");
1296 MODULE_ALIAS("platform:fsl-spdif-dai");
Linux with added FPC-III support