sound/soc/intel/sst-haswell-dsp.c

   1 /*
   2  * Intel Haswell SST DSP driver
   3  *
   4  * Copyright (C) 2013, Intel Corporation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License version
   8  * 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/fs.h>
  19 #include <linux/slab.h>
  20 #include <linux/device.h>
  21 #include <linux/sched.h>
  22 #include <linux/export.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pci.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #include "sst-dsp.h"
  32 #include "sst-dsp-priv.h"
  33 #include "sst-haswell-ipc.h"
  34
  35 #include <trace/events/hswadsp.h>
  36
  37 #define SST_HSW_FW_SIGNATURE_SIZE       4
  38 #define SST_HSW_FW_SIGN                 "$SST"
  39 #define SST_HSW_FW_LIB_SIGN             "$LIB"
  40
  41 #define SST_WPT_SHIM_OFFSET     0xFB000
  42 #define SST_LP_SHIM_OFFSET      0xE7000
  43 #define SST_WPT_IRAM_OFFSET     0xA0000
  44 #define SST_LP_IRAM_OFFSET      0x80000
  45 #define SST_WPT_DSP_DRAM_OFFSET 0x400000
  46 #define SST_WPT_DSP_IRAM_OFFSET 0x00000
  47 #define SST_LPT_DSP_DRAM_OFFSET 0x400000
  48 #define SST_LPT_DSP_IRAM_OFFSET 0x00000
  49
  50 #define SST_SHIM_PM_REG         0x84
  51
  52 #define SST_HSW_IRAM    1
  53 #define SST_HSW_DRAM    2
  54 #define SST_HSW_REGS    3
  55
  56 struct dma_block_info {
  57         __le32 type;            /* IRAM/DRAM */
  58         __le32 size;            /* Bytes */
  59         __le32 ram_offset;      /* Offset in I/DRAM */
  60         __le32 rsvd;            /* Reserved field */
  61 } __attribute__((packed));
  62
  63 struct fw_module_info {
  64         __le32 persistent_size;
  65         __le32 scratch_size;
  66 } __attribute__((packed));
  67
  68 struct fw_header {
  69         unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* FW signature */
  70         __le32 file_size;               /* size of fw minus this header */
  71         __le32 modules;         /*  # of modules */
  72         __le32 file_format;     /* version of header format */
  73         __le32 reserved[4];
  74 } __attribute__((packed));
  75
  76 struct fw_module_header {
  77         unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* module signature */
  78         __le32 mod_size;        /* size of module */
  79         __le32 blocks;  /* # of blocks */
  80         __le16 padding;
  81         __le16 type;    /* codec type, pp lib */
  82         __le32 entry_point;
  83         struct fw_module_info info;
  84 } __attribute__((packed));
  85
  86 static void hsw_free(struct sst_dsp *sst);
  87
  88 static int hsw_parse_module(struct sst_dsp *dsp, struct sst_fw *fw,
  89         struct fw_module_header *module)
  90 {
  91         struct dma_block_info *block;
  92         struct sst_module *mod;
  93         struct sst_module_template template;
  94         int count, ret;
  95         void __iomem *ram;
  96
  97         /* TODO: allowed module types need to be configurable */
  98         if (module->type != SST_HSW_MODULE_BASE_FW
  99                 && module->type != SST_HSW_MODULE_PCM_SYSTEM
 100                 && module->type != SST_HSW_MODULE_PCM
 101                 && module->type != SST_HSW_MODULE_PCM_REFERENCE
 102                 && module->type != SST_HSW_MODULE_PCM_CAPTURE
 103                 && module->type != SST_HSW_MODULE_LPAL)
 104                 return 0;
 105
 106         dev_dbg(dsp->dev, "new module sign 0x%s size 0x%x blocks 0x%x type 0x%x\n",
 107                 module->signature, module->mod_size,
 108                 module->blocks, module->type);
 109         dev_dbg(dsp->dev, " entrypoint 0x%x\n", module->entry_point);
 110         dev_dbg(dsp->dev, " persistent 0x%x scratch 0x%x\n",
 111                 module->info.persistent_size, module->info.scratch_size);
 112
 113         memset(&template, 0, sizeof(template));
 114         template.id = module->type;
 115         template.entry = module->entry_point - 4;
 116         template.persistent_size = module->info.persistent_size;
 117         template.scratch_size = module->info.scratch_size;
 118
 119         mod = sst_module_new(fw, &template, NULL);
 120         if (mod == NULL)
 121                 return -ENOMEM;
 122
 123         block = (void *)module + sizeof(*module);
 124
 125         for (count = 0; count < module->blocks; count++) {
 126
 127                 if (block->size <= 0) {
 128                         dev_err(dsp->dev,
 129                                 "error: block %d size invalid\n", count);
 130                         sst_module_free(mod);
 131                         return -EINVAL;
 132                 }
 133
 134                 switch (block->type) {
 135                 case SST_HSW_IRAM:
 136                         ram = dsp->addr.lpe;
 137                         mod->offset =
 138                                 block->ram_offset + dsp->addr.iram_offset;
 139                         mod->type = SST_MEM_IRAM;
 140                         break;
 141                 case SST_HSW_DRAM:
 142                         ram = dsp->addr.lpe;
 143                         mod->offset = block->ram_offset;
 144                         mod->type = SST_MEM_DRAM;
 145                         break;
 146                 default:
 147                         dev_err(dsp->dev, "error: bad type 0x%x for block 0x%x\n",
 148                                 block->type, count);
 149                         sst_module_free(mod);
 150                         return -EINVAL;
 151                 }
 152
 153                 mod->size = block->size;
 154                 mod->data = (void *)block + sizeof(*block);
 155                 mod->data_offset = mod->data - fw->dma_buf;
 156
 157                 dev_dbg(dsp->dev, "module block %d type 0x%x "
 158                         "size 0x%x ==> ram %p offset 0x%x\n",
 159                         count, mod->type, block->size, ram,
 160                         block->ram_offset);
 161
 162                 ret = sst_module_alloc_blocks(mod);
 163                 if (ret < 0) {
 164                         dev_err(dsp->dev, "error: could not allocate blocks for module %d\n",
 165                                 count);
 166                         sst_module_free(mod);
 167                         return ret;
 168                 }
 169
 170                 block = (void *)block + sizeof(*block) + block->size;
 171         }
 172
 173         return 0;
 174 }
 175
 176 static int hsw_parse_fw_image(struct sst_fw *sst_fw)
 177 {
 178         struct fw_header *header;
 179         struct fw_module_header *module;
 180         struct sst_dsp *dsp = sst_fw->dsp;
 181         int ret, count;
 182
 183         /* Read the header information from the data pointer */
 184         header = (struct fw_header *)sst_fw->dma_buf;
 185
 186         /* verify FW */
 187         if ((strncmp(header->signature, SST_HSW_FW_SIGN, 4) != 0) ||
 188                 (sst_fw->size != header->file_size + sizeof(*header))) {
 189                 dev_err(dsp->dev, "error: invalid fw sign/filesize mismatch\n");
 190                 return -EINVAL;
 191         }
 192
 193         dev_dbg(dsp->dev, "header size=0x%x modules=0x%x fmt=0x%x size=%zu\n",
 194                 header->file_size, header->modules,
 195                 header->file_format, sizeof(*header));
 196
 197         /* parse each module */
 198         module = (void *)sst_fw->dma_buf + sizeof(*header);
 199         for (count = 0; count < header->modules; count++) {
 200
 201                 /* module */
 202                 ret = hsw_parse_module(dsp, sst_fw, module);
 203                 if (ret < 0) {
 204                         dev_err(dsp->dev, "error: invalid module %d\n", count);
 205                         return ret;
 206                 }
 207                 module = (void *)module + sizeof(*module) + module->mod_size;
 208         }
 209
 210         /* allocate scratch mem regions */
 211         sst_block_alloc_scratch(dsp);
 212
 213         return 0;
 214 }
 215
 216 static irqreturn_t hsw_irq(int irq, void *context)
 217 {
 218         struct sst_dsp *sst = (struct sst_dsp *) context;
 219         u32 isr;
 220         int ret = IRQ_NONE;
 221
 222         spin_lock(&sst->spinlock);
 223
 224         /* Interrupt arrived, check src */
 225         isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
 226         if (isr & SST_ISRX_DONE) {
 227                 trace_sst_irq_done(isr,
 228                         sst_dsp_shim_read_unlocked(sst, SST_IMRX));
 229
 230                 /* Mask Done interrupt before return */
 231                 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
 232                         SST_IMRX_DONE, SST_IMRX_DONE);
 233                 ret = IRQ_WAKE_THREAD;
 234         }
 235
 236         if (isr & SST_ISRX_BUSY) {
 237                 trace_sst_irq_busy(isr,
 238                         sst_dsp_shim_read_unlocked(sst, SST_IMRX));
 239
 240                 /* Mask Busy interrupt before return */
 241                 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
 242                         SST_IMRX_BUSY, SST_IMRX_BUSY);
 243                 ret = IRQ_WAKE_THREAD;
 244         }
 245
 246         spin_unlock(&sst->spinlock);
 247         return ret;
 248 }
 249
 250 static void hsw_set_dsp_D3(struct sst_dsp *sst)
 251 {
 252         u32 val;
 253         u32 reg;
 254
 255         /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
 256         reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 257         reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE);
 258         writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
 259
 260         /* enable power gating and switch off DRAM & IRAM blocks */
 261         val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
 262         val |= SST_VDRTCL0_DSRAMPGE_MASK |
 263                 SST_VDRTCL0_ISRAMPGE_MASK;
 264         val &= ~(SST_VDRTCL0_D3PGD | SST_VDRTCL0_D3SRAMPGD);
 265         writel(val, sst->addr.pci_cfg + SST_VDRTCTL0);
 266
 267         /* switch off audio PLL */
 268         val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 269         val |= SST_VDRTCL2_APLLSE_MASK;
 270         writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
 271
 272         /* disable MCLK(clkctl.smos = 0) */
 273         sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
 274                 SST_CLKCTL_MASK, 0);
 275
 276         /* Set D3 state, delay 50 us */
 277         val = readl(sst->addr.pci_cfg + SST_PMCS);
 278         val |= SST_PMCS_PS_MASK;
 279         writel(val, sst->addr.pci_cfg + SST_PMCS);
 280         udelay(50);
 281
 282         /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
 283         reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 284         reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE;
 285         writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
 286
 287         udelay(50);
 288
 289 }
 290
 291 static void hsw_reset(struct sst_dsp *sst)
 292 {
 293         /* put DSP into reset and stall */
 294         sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
 295                 SST_CSR_RST | SST_CSR_STALL,
 296                 SST_CSR_RST | SST_CSR_STALL);
 297
 298         /* keep in reset for 10ms */
 299         mdelay(10);
 300
 301         /* take DSP out of reset and keep stalled for FW loading */
 302         sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
 303                 SST_CSR_RST | SST_CSR_STALL, SST_CSR_STALL);
 304 }
 305
 306 static int hsw_set_dsp_D0(struct sst_dsp *sst)
 307 {
 308         int tries = 10;
 309         u32 reg;
 310
 311         /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
 312         reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 313         reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE);
 314         writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
 315
 316         /* Disable D3PG (VDRTCTL0.D3PGD = 1) */
 317         reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
 318         reg |= SST_VDRTCL0_D3PGD;
 319         writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0);
 320
 321         /* Set D0 state */
 322         reg = readl(sst->addr.pci_cfg + SST_PMCS);
 323         reg &= ~SST_PMCS_PS_MASK;
 324         writel(reg, sst->addr.pci_cfg + SST_PMCS);
 325
 326         /* check that ADSP shim is enabled */
 327         while (tries--) {
 328                 reg = readl(sst->addr.pci_cfg + SST_PMCS) & SST_PMCS_PS_MASK;
 329                 if (reg == 0)
 330                         goto finish;
 331
 332                 msleep(1);
 333         }
 334
 335         return -ENODEV;
 336
 337 finish:
 338         /* select SSP1 19.2MHz base clock, SSP clock 0, turn off Low Power Clock */
 339         sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
 340                 SST_CSR_S1IOCS | SST_CSR_SBCS1 | SST_CSR_LPCS, 0x0);
 341
 342         /* stall DSP core, set clk to 192/96Mhz */
 343         sst_dsp_shim_update_bits_unlocked(sst,
 344                 SST_CSR, SST_CSR_STALL | SST_CSR_DCS_MASK,
 345                 SST_CSR_STALL | SST_CSR_DCS(4));
 346
 347         /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
 348         sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
 349                 SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0,
 350                 SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0);
 351
 352         /* Stall and reset core, set CSR */
 353         hsw_reset(sst);
 354
 355         /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
 356         reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 357         reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE;
 358         writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
 359
 360         udelay(50);
 361
 362         /* switch on audio PLL */
 363         reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 364         reg &= ~SST_VDRTCL2_APLLSE_MASK;
 365         writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
 366
 367         /* set default power gating control, enable power gating control for all blocks. that is,
 368         can't be accessed, please enable each block before accessing. */
 369         reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
 370         reg |= SST_VDRTCL0_DSRAMPGE_MASK | SST_VDRTCL0_ISRAMPGE_MASK;
 371         writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0);
 372
 373
 374         /* disable DMA finish function for SSP0 & SSP1 */
 375         sst_dsp_shim_update_bits_unlocked(sst, SST_CSR2, SST_CSR2_SDFD_SSP1,
 376                 SST_CSR2_SDFD_SSP1);
 377
 378         /* set on-demond mode on engine 0,1 for all channels */
 379         sst_dsp_shim_update_bits(sst, SST_HMDC,
 380                         SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
 381                         SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
 382
 383         /* Enable Interrupt from both sides */
 384         sst_dsp_shim_update_bits(sst, SST_IMRX, (SST_IMRX_BUSY | SST_IMRX_DONE),
 385                                  0x0);
 386         sst_dsp_shim_update_bits(sst, SST_IMRD, (SST_IMRD_DONE | SST_IMRD_BUSY |
 387                                 SST_IMRD_SSP0 | SST_IMRD_DMAC), 0x0);
 388
 389         /* clear IPC registers */
 390         sst_dsp_shim_write(sst, SST_IPCX, 0x0);
 391         sst_dsp_shim_write(sst, SST_IPCD, 0x0);
 392         sst_dsp_shim_write(sst, 0x80, 0x6);
 393         sst_dsp_shim_write(sst, 0xe0, 0x300a);
 394
 395         return 0;
 396 }
 397
 398 static void hsw_boot(struct sst_dsp *sst)
 399 {
 400         /* set oportunistic mode on engine 0,1 for all channels */
 401         sst_dsp_shim_update_bits(sst, SST_HMDC,
 402                         SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH, 0);
 403
 404         /* set DSP to RUN */
 405         sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, SST_CSR_STALL, 0x0);
 406 }
 407
 408 static void hsw_stall(struct sst_dsp *sst)
 409 {
 410         /* stall DSP */
 411         sst_dsp_shim_update_bits(sst, SST_CSR,
 412                 SST_CSR_24MHZ_LPCS | SST_CSR_STALL,
 413                 SST_CSR_STALL | SST_CSR_24MHZ_LPCS);
 414 }
 415
 416 static void hsw_sleep(struct sst_dsp *sst)
 417 {
 418         dev_dbg(sst->dev, "HSW_PM dsp runtime suspend\n");
 419
 420         /* put DSP into reset and stall */
 421         sst_dsp_shim_update_bits(sst, SST_CSR,
 422                 SST_CSR_24MHZ_LPCS | SST_CSR_RST | SST_CSR_STALL,
 423                 SST_CSR_RST | SST_CSR_STALL | SST_CSR_24MHZ_LPCS);
 424
 425         hsw_set_dsp_D3(sst);
 426         dev_dbg(sst->dev, "HSW_PM dsp runtime suspend exit\n");
 427 }
 428
 429 static int hsw_wake(struct sst_dsp *sst)
 430 {
 431         int ret;
 432
 433         dev_dbg(sst->dev, "HSW_PM dsp runtime resume\n");
 434
 435         ret = hsw_set_dsp_D0(sst);
 436         if (ret < 0)
 437                 return ret;
 438
 439         dev_dbg(sst->dev, "HSW_PM dsp runtime resume exit\n");
 440
 441         return 0;
 442 }
 443
 444 struct sst_adsp_memregion {
 445         u32 start;
 446         u32 end;
 447         int blocks;
 448         enum sst_mem_type type;
 449 };
 450
 451 /* lynx point ADSP mem regions */
 452 static const struct sst_adsp_memregion lp_region[] = {
 453         {0x00000, 0x40000, 8, SST_MEM_DRAM}, /* D-SRAM0 - 8 * 32kB */
 454         {0x40000, 0x80000, 8, SST_MEM_DRAM}, /* D-SRAM1 - 8 * 32kB */
 455         {0x80000, 0xE0000, 12, SST_MEM_IRAM}, /* I-SRAM - 12 * 32kB */
 456 };
 457
 458 /* wild cat point ADSP mem regions */
 459 static const struct sst_adsp_memregion wpt_region[] = {
 460         {0x00000, 0xA0000, 20, SST_MEM_DRAM}, /* D-SRAM0,D-SRAM1,D-SRAM2 - 20 * 32kB */
 461         {0xA0000, 0xF0000, 10, SST_MEM_IRAM}, /* I-SRAM - 10 * 32kB */
 462 };
 463
 464 static int hsw_acpi_resource_map(struct sst_dsp *sst, struct sst_pdata *pdata)
 465 {
 466         /* ADSP DRAM & IRAM */
 467         sst->addr.lpe_base = pdata->lpe_base;
 468         sst->addr.lpe = ioremap(pdata->lpe_base, pdata->lpe_size);
 469         if (!sst->addr.lpe)
 470                 return -ENODEV;
 471
 472         /* ADSP PCI MMIO config space */
 473         sst->addr.pci_cfg = ioremap(pdata->pcicfg_base, pdata->pcicfg_size);
 474         if (!sst->addr.pci_cfg) {
 475                 iounmap(sst->addr.lpe);
 476                 return -ENODEV;
 477         }
 478
 479         /* SST Shim */
 480         sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset;
 481         return 0;
 482 }
 483
 484 struct sst_sram_shift {
 485         u32 dev_id;     /* SST Device IDs  */
 486         u32 iram_shift;
 487         u32 dram_shift;
 488 };
 489
 490 static const struct sst_sram_shift sram_shift[] = {
 491         {SST_DEV_ID_LYNX_POINT, 6, 16}, /* lp */
 492         {SST_DEV_ID_WILDCAT_POINT, 2, 12}, /* wpt */
 493 };
 494 static u32 hsw_block_get_bit(struct sst_mem_block *block)
 495 {
 496         u32 bit = 0, shift = 0, index;
 497         struct sst_dsp *sst = block->dsp;
 498
 499         for (index = 0; index < ARRAY_SIZE(sram_shift); index++) {
 500                 if (sram_shift[index].dev_id == sst->id)
 501                         break;
 502         }
 503
 504         if (index < ARRAY_SIZE(sram_shift)) {
 505                 switch (block->type) {
 506                 case SST_MEM_DRAM:
 507                         shift = sram_shift[index].dram_shift;
 508                         break;
 509                 case SST_MEM_IRAM:
 510                         shift = sram_shift[index].iram_shift;
 511                         break;
 512                 default:
 513                         shift = 0;
 514                 }
 515         } else
 516                 shift = 0;
 517
 518         bit = 1 << (block->index + shift);
 519
 520         return bit;
 521 }
 522
 523 /*dummy read a SRAM block.*/
 524 static void sst_mem_block_dummy_read(struct sst_mem_block *block)
 525 {
 526         u32 size;
 527         u8 tmp_buf[4];
 528         struct sst_dsp *sst = block->dsp;
 529
 530         size = block->size > 4 ? 4 : block->size;
 531         memcpy_fromio(tmp_buf, sst->addr.lpe + block->offset, size);
 532 }
 533
 534 /* enable 32kB memory block - locks held by caller */
 535 static int hsw_block_enable(struct sst_mem_block *block)
 536 {
 537         struct sst_dsp *sst = block->dsp;
 538         u32 bit, val;
 539
 540         if (block->users++ > 0)
 541                 return 0;
 542
 543         dev_dbg(block->dsp->dev, " enabled block %d:%d at offset 0x%x\n",
 544                 block->type, block->index, block->offset);
 545
 546         /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
 547         val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 548         val &= ~SST_VDRTCL2_DCLCGE;
 549         writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
 550
 551         val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
 552         bit = hsw_block_get_bit(block);
 553         writel(val & ~bit, sst->addr.pci_cfg + SST_VDRTCTL0);
 554
 555         /* wait 18 DSP clock ticks */
 556         udelay(10);
 557
 558         /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
 559         val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 560         val |= SST_VDRTCL2_DCLCGE;
 561         writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
 562
 563         udelay(50);
 564
 565         /*add a dummy read before the SRAM block is written, otherwise the writing may miss bytes sometimes.*/
 566         sst_mem_block_dummy_read(block);
 567         return 0;
 568 }
 569
 570 /* disable 32kB memory block - locks held by caller */
 571 static int hsw_block_disable(struct sst_mem_block *block)
 572 {
 573         struct sst_dsp *sst = block->dsp;
 574         u32 bit, val;
 575
 576         if (--block->users > 0)
 577                 return 0;
 578
 579         dev_dbg(block->dsp->dev, " disabled block %d:%d at offset 0x%x\n",
 580                 block->type, block->index, block->offset);
 581
 582         /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
 583         val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 584         val &= ~SST_VDRTCL2_DCLCGE;
 585         writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
 586
 587
 588         val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
 589         bit = hsw_block_get_bit(block);
 590         writel(val | bit, sst->addr.pci_cfg + SST_VDRTCTL0);
 591
 592         /* wait 18 DSP clock ticks */
 593         udelay(10);
 594
 595         /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
 596         val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 597         val |= SST_VDRTCL2_DCLCGE;
 598         writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
 599
 600         udelay(50);
 601
 602         return 0;
 603 }
 604
 605 static struct sst_block_ops sst_hsw_ops = {
 606         .enable = hsw_block_enable,
 607         .disable = hsw_block_disable,
 608 };
 609
 610 static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata)
 611 {
 612         const struct sst_adsp_memregion *region;
 613         struct device *dev;
 614         int ret = -ENODEV, i, j, region_count;
 615         u32 offset, size;
 616
 617         dev = sst->dma_dev;
 618
 619         switch (sst->id) {
 620         case SST_DEV_ID_LYNX_POINT:
 621                 region = lp_region;
 622                 region_count = ARRAY_SIZE(lp_region);
 623                 sst->addr.iram_offset = SST_LP_IRAM_OFFSET;
 624                 sst->addr.dsp_iram_offset = SST_LPT_DSP_IRAM_OFFSET;
 625                 sst->addr.dsp_dram_offset = SST_LPT_DSP_DRAM_OFFSET;
 626                 sst->addr.shim_offset = SST_LP_SHIM_OFFSET;
 627                 break;
 628         case SST_DEV_ID_WILDCAT_POINT:
 629                 region = wpt_region;
 630                 region_count = ARRAY_SIZE(wpt_region);
 631                 sst->addr.iram_offset = SST_WPT_IRAM_OFFSET;
 632                 sst->addr.dsp_iram_offset = SST_WPT_DSP_IRAM_OFFSET;
 633                 sst->addr.dsp_dram_offset = SST_WPT_DSP_DRAM_OFFSET;
 634                 sst->addr.shim_offset = SST_WPT_SHIM_OFFSET;
 635                 break;
 636         default:
 637                 dev_err(dev, "error: failed to get mem resources\n");
 638                 return ret;
 639         }
 640
 641         ret = hsw_acpi_resource_map(sst, pdata);
 642         if (ret < 0) {
 643                 dev_err(dev, "error: failed to map resources\n");
 644                 return ret;
 645         }
 646
 647         /* enable the DSP SHIM */
 648         ret = hsw_set_dsp_D0(sst);
 649         if (ret < 0) {
 650                 dev_err(dev, "error: failed to set DSP D0 and reset SHIM\n");
 651                 return ret;
 652         }
 653
 654         ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(31));
 655         if (ret)
 656                 return ret;
 657
 658
 659         /* register DSP memory blocks - ideally we should get this from ACPI */
 660         for (i = 0; i < region_count; i++) {
 661                 offset = region[i].start;
 662                 size = (region[i].end - region[i].start) / region[i].blocks;
 663
 664                 /* register individual memory blocks */
 665                 for (j = 0; j < region[i].blocks; j++) {
 666                         sst_mem_block_register(sst, offset, size,
 667                                 region[i].type, &sst_hsw_ops, j, sst);
 668                         offset += size;
 669                 }
 670         }
 671
 672         /* set default power gating control, enable power gating control for all blocks. that is,
 673         can't be accessed, please enable each block before accessing. */
 674         writel(0xffffffff, sst->addr.pci_cfg + SST_VDRTCTL0);
 675
 676         return 0;
 677 }
 678
 679 static void hsw_free(struct sst_dsp *sst)
 680 {
 681         sst_mem_block_unregister_all(sst);
 682         iounmap(sst->addr.lpe);
 683         iounmap(sst->addr.pci_cfg);
 684 }
 685
 686 struct sst_ops haswell_ops = {
 687         .reset = hsw_reset,
 688         .boot = hsw_boot,
 689         .stall = hsw_stall,
 690         .wake = hsw_wake,
 691         .sleep = hsw_sleep,
 692         .write = sst_shim32_write,
 693         .read = sst_shim32_read,
 694         .write64 = sst_shim32_write64,
 695         .read64 = sst_shim32_read64,
 696         .ram_read = sst_memcpy_fromio_32,
 697         .ram_write = sst_memcpy_toio_32,
 698         .irq_handler = hsw_irq,
 699         .init = hsw_init,
 700         .free = hsw_free,
 701         .parse_fw = hsw_parse_fw_image,
 702 };