sound/soc/intel/sst-haswell-ipc.h

   1 /*
   2  * Intel SST Haswell/Broadwell IPC Support
   3  *
   4  * Copyright (C) 2013, Intel Corporation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License version
   8  * 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #ifndef __SST_HASWELL_IPC_H
  18 #define __SST_HASWELL_IPC_H
  19
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/platform_device.h>
  23
  24 #define SST_HSW_NO_CHANNELS             4
  25 #define SST_HSW_MAX_DX_REGIONS          14
  26 #define SST_HSW_DX_CONTEXT_SIZE        (640 * 1024)
  27 #define SST_HSW_CHANNELS_ALL            0xffffffff
  28
  29 #define SST_HSW_FW_LOG_CONFIG_DWORDS    12
  30 #define SST_HSW_GLOBAL_LOG              15
  31
  32 /**
  33  * Upfront defined maximum message size that is
  34  * expected by the in/out communication pipes in FW.
  35  */
  36 #define SST_HSW_IPC_MAX_PAYLOAD_SIZE    400
  37 #define SST_HSW_MAX_INFO_SIZE           64
  38 #define SST_HSW_BUILD_HASH_LENGTH       40
  39
  40 struct sst_hsw;
  41 struct sst_hsw_stream;
  42 struct sst_hsw_log_stream;
  43 struct sst_pdata;
  44 struct sst_module;
  45 struct sst_module_runtime;
  46 extern struct sst_ops haswell_ops;
  47
  48 /* Stream Allocate Path ID */
  49 enum sst_hsw_stream_path_id {
  50         SST_HSW_STREAM_PATH_SSP0_OUT = 0,
  51         SST_HSW_STREAM_PATH_SSP0_IN = 1,
  52         SST_HSW_STREAM_PATH_MAX_PATH_ID = 2,
  53 };
  54
  55 /* Stream Allocate Stream Type */
  56 enum sst_hsw_stream_type {
  57         SST_HSW_STREAM_TYPE_RENDER = 0,
  58         SST_HSW_STREAM_TYPE_SYSTEM = 1,
  59         SST_HSW_STREAM_TYPE_CAPTURE = 2,
  60         SST_HSW_STREAM_TYPE_LOOPBACK = 3,
  61         SST_HSW_STREAM_TYPE_MAX_STREAM_TYPE = 4,
  62 };
  63
  64 /* Stream Allocate Stream Format */
  65 enum sst_hsw_stream_format {
  66         SST_HSW_STREAM_FORMAT_PCM_FORMAT = 0,
  67         SST_HSW_STREAM_FORMAT_MP3_FORMAT = 1,
  68         SST_HSW_STREAM_FORMAT_AAC_FORMAT = 2,
  69         SST_HSW_STREAM_FORMAT_MAX_FORMAT_ID = 3,
  70 };
  71
  72 /* Device ID */
  73 enum sst_hsw_device_id {
  74         SST_HSW_DEVICE_SSP_0   = 0,
  75         SST_HSW_DEVICE_SSP_1   = 1,
  76 };
  77
  78 /* Device Master Clock Frequency */
  79 enum sst_hsw_device_mclk {
  80         SST_HSW_DEVICE_MCLK_OFF         = 0,
  81         SST_HSW_DEVICE_MCLK_FREQ_6_MHZ  = 1,
  82         SST_HSW_DEVICE_MCLK_FREQ_12_MHZ = 2,
  83         SST_HSW_DEVICE_MCLK_FREQ_24_MHZ = 3,
  84 };
  85
  86 /* Device Clock Master */
  87 enum sst_hsw_device_mode {
  88         SST_HSW_DEVICE_CLOCK_SLAVE   = 0,
  89         SST_HSW_DEVICE_CLOCK_MASTER  = 1,
  90         SST_HSW_DEVICE_TDM_CLOCK_MASTER = 2,
  91 };
  92
  93 /* DX Power State */
  94 enum sst_hsw_dx_state {
  95         SST_HSW_DX_STATE_D0     = 0,
  96         SST_HSW_DX_STATE_D1     = 1,
  97         SST_HSW_DX_STATE_D3     = 3,
  98         SST_HSW_DX_STATE_MAX    = 3,
  99 };
 100
 101 /* Audio stream stage IDs */
 102 enum sst_hsw_fx_stage_id {
 103         SST_HSW_STAGE_ID_WAVES = 0,
 104         SST_HSW_STAGE_ID_DTS   = 1,
 105         SST_HSW_STAGE_ID_DOLBY = 2,
 106         SST_HSW_STAGE_ID_BOOST = 3,
 107         SST_HSW_STAGE_ID_MAX_FX_ID
 108 };
 109
 110 /* DX State Type */
 111 enum sst_hsw_dx_type {
 112         SST_HSW_DX_TYPE_FW_IMAGE = 0,
 113         SST_HSW_DX_TYPE_MEMORY_DUMP = 1
 114 };
 115
 116 /* Volume Curve Type*/
 117 enum sst_hsw_volume_curve {
 118         SST_HSW_VOLUME_CURVE_NONE = 0,
 119         SST_HSW_VOLUME_CURVE_FADE = 1
 120 };
 121
 122 /* Sample ordering */
 123 enum sst_hsw_interleaving {
 124         SST_HSW_INTERLEAVING_PER_CHANNEL = 0,
 125         SST_HSW_INTERLEAVING_PER_SAMPLE  = 1,
 126 };
 127
 128 /* Channel indices */
 129 enum sst_hsw_channel_index {
 130         SST_HSW_CHANNEL_LEFT            = 0,
 131         SST_HSW_CHANNEL_CENTER          = 1,
 132         SST_HSW_CHANNEL_RIGHT           = 2,
 133         SST_HSW_CHANNEL_LEFT_SURROUND   = 3,
 134         SST_HSW_CHANNEL_CENTER_SURROUND = 3,
 135         SST_HSW_CHANNEL_RIGHT_SURROUND  = 4,
 136         SST_HSW_CHANNEL_LFE             = 7,
 137         SST_HSW_CHANNEL_INVALID         = 0xF,
 138 };
 139
 140 /* List of supported channel maps. */
 141 enum sst_hsw_channel_config {
 142         SST_HSW_CHANNEL_CONFIG_MONO      = 0, /* mono only. */
 143         SST_HSW_CHANNEL_CONFIG_STEREO    = 1, /* L & R. */
 144         SST_HSW_CHANNEL_CONFIG_2_POINT_1 = 2, /* L, R & LFE; PCM only. */
 145         SST_HSW_CHANNEL_CONFIG_3_POINT_0 = 3, /* L, C & R; MP3 & AAC only. */
 146         SST_HSW_CHANNEL_CONFIG_3_POINT_1 = 4, /* L, C, R & LFE; PCM only. */
 147         SST_HSW_CHANNEL_CONFIG_QUATRO    = 5, /* L, R, Ls & Rs; PCM only. */
 148         SST_HSW_CHANNEL_CONFIG_4_POINT_0 = 6, /* L, C, R & Cs; MP3 & AAC only. */
 149         SST_HSW_CHANNEL_CONFIG_5_POINT_0 = 7, /* L, C, R, Ls & Rs. */
 150         SST_HSW_CHANNEL_CONFIG_5_POINT_1 = 8, /* L, C, R, Ls, Rs & LFE. */
 151         SST_HSW_CHANNEL_CONFIG_DUAL_MONO = 9, /* One channel replicated in two. */
 152         SST_HSW_CHANNEL_CONFIG_INVALID,
 153 };
 154
 155 /* List of supported bit depths. */
 156 enum sst_hsw_bitdepth {
 157         SST_HSW_DEPTH_8BIT  = 8,
 158         SST_HSW_DEPTH_16BIT = 16,
 159         SST_HSW_DEPTH_24BIT = 24, /* Default. */
 160         SST_HSW_DEPTH_32BIT = 32,
 161         SST_HSW_DEPTH_INVALID = 33,
 162 };
 163
 164 enum sst_hsw_module_id {
 165         SST_HSW_MODULE_BASE_FW = 0x0,
 166         SST_HSW_MODULE_MP3     = 0x1,
 167         SST_HSW_MODULE_AAC_5_1 = 0x2,
 168         SST_HSW_MODULE_AAC_2_0 = 0x3,
 169         SST_HSW_MODULE_SRC     = 0x4,
 170         SST_HSW_MODULE_WAVES   = 0x5,
 171         SST_HSW_MODULE_DOLBY   = 0x6,
 172         SST_HSW_MODULE_BOOST   = 0x7,
 173         SST_HSW_MODULE_LPAL    = 0x8,
 174         SST_HSW_MODULE_DTS     = 0x9,
 175         SST_HSW_MODULE_PCM_CAPTURE = 0xA,
 176         SST_HSW_MODULE_PCM_SYSTEM = 0xB,
 177         SST_HSW_MODULE_PCM_REFERENCE = 0xC,
 178         SST_HSW_MODULE_PCM = 0xD,
 179         SST_HSW_MODULE_BLUETOOTH_RENDER_MODULE = 0xE,
 180         SST_HSW_MODULE_BLUETOOTH_CAPTURE_MODULE = 0xF,
 181         SST_HSW_MAX_MODULE_ID,
 182 };
 183
 184 enum sst_hsw_performance_action {
 185         SST_HSW_PERF_START = 0,
 186         SST_HSW_PERF_STOP = 1,
 187 };
 188
 189 /* SST firmware module info */
 190 struct sst_hsw_module_info {
 191         u8 name[SST_HSW_MAX_INFO_SIZE];
 192         u8 version[SST_HSW_MAX_INFO_SIZE];
 193 } __attribute__((packed));
 194
 195 /* Module entry point */
 196 struct sst_hsw_module_entry {
 197         enum sst_hsw_module_id module_id;
 198         u32 entry_point;
 199 } __attribute__((packed));
 200
 201 /* Module map - alignement matches DSP */
 202 struct sst_hsw_module_map {
 203         u8 module_entries_count;
 204         struct sst_hsw_module_entry module_entries[1];
 205 } __attribute__((packed));
 206
 207 struct sst_hsw_memory_info {
 208         u32 offset;
 209         u32 size;
 210 } __attribute__((packed));
 211
 212 struct sst_hsw_fx_enable {
 213         struct sst_hsw_module_map module_map;
 214         struct sst_hsw_memory_info persistent_mem;
 215 } __attribute__((packed));
 216
 217 struct sst_hsw_get_fx_param {
 218         u32 parameter_id;
 219         u32 param_size;
 220 } __attribute__((packed));
 221
 222 struct sst_hsw_perf_action {
 223         u32 action;
 224 } __attribute__((packed));
 225
 226 struct sst_hsw_perf_data {
 227         u64 timestamp;
 228         u64 cycles;
 229         u64 datatime;
 230 } __attribute__((packed));
 231
 232 /* FW version */
 233 struct sst_hsw_ipc_fw_version {
 234         u8 build;
 235         u8 minor;
 236         u8 major;
 237         u8 type;
 238         u8 fw_build_hash[SST_HSW_BUILD_HASH_LENGTH];
 239         u32 fw_log_providers_hash;
 240 } __attribute__((packed));
 241
 242 /* Stream ring info */
 243 struct sst_hsw_ipc_stream_ring {
 244         u32 ring_pt_address;
 245         u32 num_pages;
 246         u32 ring_size;
 247         u32 ring_offset;
 248         u32 ring_first_pfn;
 249 } __attribute__((packed));
 250
 251 /* Debug Dump Log Enable Request */
 252 struct sst_hsw_ipc_debug_log_enable_req {
 253         struct sst_hsw_ipc_stream_ring ringinfo;
 254         u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
 255 } __attribute__((packed));
 256
 257 /* Debug Dump Log Reply */
 258 struct sst_hsw_ipc_debug_log_reply {
 259         u32 log_buffer_begining;
 260         u32 log_buffer_size;
 261 } __attribute__((packed));
 262
 263 /* Stream glitch position */
 264 struct sst_hsw_ipc_stream_glitch_position {
 265         u32 glitch_type;
 266         u32 present_pos;
 267         u32 write_pos;
 268 } __attribute__((packed));
 269
 270 /* Stream get position */
 271 struct sst_hsw_ipc_stream_get_position {
 272         u32 position;
 273         u32 fw_cycle_count;
 274 } __attribute__((packed));
 275
 276 /* Stream set position */
 277 struct sst_hsw_ipc_stream_set_position {
 278         u32 position;
 279         u32 end_of_buffer;
 280 } __attribute__((packed));
 281
 282 /* Stream Free Request */
 283 struct sst_hsw_ipc_stream_free_req {
 284         u8 stream_id;
 285         u8 reserved[3];
 286 } __attribute__((packed));
 287
 288 /* Set Volume Request */
 289 struct sst_hsw_ipc_volume_req {
 290         u32 channel;
 291         u32 target_volume;
 292         u64 curve_duration;
 293         u32 curve_type;
 294 } __attribute__((packed));
 295
 296 /* Device Configuration Request */
 297 struct sst_hsw_ipc_device_config_req {
 298         u32 ssp_interface;
 299         u32 clock_frequency;
 300         u32 mode;
 301         u16 clock_divider;
 302         u8 channels;
 303         u8 reserved;
 304 } __attribute__((packed));
 305
 306 /* Audio Data formats */
 307 struct sst_hsw_audio_data_format_ipc {
 308         u32 frequency;
 309         u32 bitdepth;
 310         u32 map;
 311         u32 config;
 312         u32 style;
 313         u8 ch_num;
 314         u8 valid_bit;
 315         u8 reserved[2];
 316 } __attribute__((packed));
 317
 318 /* Stream Allocate Request */
 319 struct sst_hsw_ipc_stream_alloc_req {
 320         u8 path_id;
 321         u8 stream_type;
 322         u8 format_id;
 323         u8 reserved;
 324         struct sst_hsw_audio_data_format_ipc format;
 325         struct sst_hsw_ipc_stream_ring ringinfo;
 326         struct sst_hsw_module_map map;
 327         struct sst_hsw_memory_info persistent_mem;
 328         struct sst_hsw_memory_info scratch_mem;
 329         u32 number_of_notifications;
 330 } __attribute__((packed));
 331
 332 /* Stream Allocate Reply */
 333 struct sst_hsw_ipc_stream_alloc_reply {
 334         u32 stream_hw_id;
 335         u32 mixer_hw_id; // returns rate ????
 336         u32 read_position_register_address;
 337         u32 presentation_position_register_address;
 338         u32 peak_meter_register_address[SST_HSW_NO_CHANNELS];
 339         u32 volume_register_address[SST_HSW_NO_CHANNELS];
 340 } __attribute__((packed));
 341
 342 /* Get Mixer Stream Info */
 343 struct sst_hsw_ipc_stream_info_reply {
 344         u32 mixer_hw_id;
 345         u32 peak_meter_register_address[SST_HSW_NO_CHANNELS];
 346         u32 volume_register_address[SST_HSW_NO_CHANNELS];
 347 } __attribute__((packed));
 348
 349 /* DX State Request */
 350 struct sst_hsw_ipc_dx_req {
 351         u8 state;
 352         u8 reserved[3];
 353 } __attribute__((packed));
 354
 355 /* DX State Reply Memory Info Item */
 356 struct sst_hsw_ipc_dx_memory_item {
 357         u32 offset;
 358         u32 size;
 359         u32 source;
 360 } __attribute__((packed));
 361
 362 /* DX State Reply */
 363 struct sst_hsw_ipc_dx_reply {
 364         u32 entries_no;
 365         struct sst_hsw_ipc_dx_memory_item mem_info[SST_HSW_MAX_DX_REGIONS];
 366 } __attribute__((packed));
 367
 368 struct sst_hsw_ipc_fw_version;
 369
 370 /* SST Init & Free */
 371 struct sst_hsw *sst_hsw_new(struct device *dev, const u8 *fw, size_t fw_length,
 372         u32 fw_offset);
 373 void sst_hsw_free(struct sst_hsw *hsw);
 374 int sst_hsw_fw_get_version(struct sst_hsw *hsw,
 375         struct sst_hsw_ipc_fw_version *version);
 376 u32 create_channel_map(enum sst_hsw_channel_config config);
 377
 378 /* Stream Mixer Controls - */
 379 int sst_hsw_stream_mute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 380         u32 stage_id, u32 channel);
 381 int sst_hsw_stream_unmute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 382         u32 stage_id, u32 channel);
 383
 384 int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
 385         struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume);
 386 int sst_hsw_stream_get_volume(struct sst_hsw *hsw,
 387         struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 *volume);
 388
 389 int sst_hsw_stream_set_volume_curve(struct sst_hsw *hsw,
 390         struct sst_hsw_stream *stream, u64 curve_duration,
 391         enum sst_hsw_volume_curve curve);
 392
 393 /* Global Mixer Controls - */
 394 int sst_hsw_mixer_mute(struct sst_hsw *hsw, u32 stage_id, u32 channel);
 395 int sst_hsw_mixer_unmute(struct sst_hsw *hsw, u32 stage_id, u32 channel);
 396
 397 int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
 398         u32 volume);
 399 int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
 400         u32 *volume);
 401
 402 int sst_hsw_mixer_set_volume_curve(struct sst_hsw *hsw,
 403         u64 curve_duration, enum sst_hsw_volume_curve curve);
 404
 405 /* Stream API */
 406 struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
 407         u32 (*get_write_position)(struct sst_hsw_stream *stream, void *data),
 408         void *data);
 409
 410 int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
 411
 412 /* Stream Configuration */
 413 int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 414         enum sst_hsw_stream_path_id path_id,
 415         enum sst_hsw_stream_type stream_type,
 416         enum sst_hsw_stream_format format_id);
 417
 418 int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 419         u32 ring_pt_address, u32 num_pages,
 420         u32 ring_size, u32 ring_offset, u32 ring_first_pfn);
 421
 422 int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
 423
 424 int sst_hsw_stream_set_valid(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 425         u32 bits);
 426 int sst_hsw_stream_set_rate(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 427         int rate);
 428 int sst_hsw_stream_set_bits(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 429         enum sst_hsw_bitdepth bits);
 430 int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
 431         struct sst_hsw_stream *stream, int channels);
 432 int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
 433         struct sst_hsw_stream *stream, u32 map,
 434         enum sst_hsw_channel_config config);
 435 int sst_hsw_stream_set_style(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 436         enum sst_hsw_interleaving style);
 437 int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
 438         struct sst_hsw_stream *stream, struct sst_module_runtime *runtime);
 439 int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw,
 440         struct sst_hsw_stream *stream, u32 offset, u32 size);
 441 int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw,
 442         struct sst_hsw_stream *stream, u32 offset, u32 size);
 443 int sst_hsw_stream_get_hw_id(struct sst_hsw *hsw,
 444         struct sst_hsw_stream *stream);
 445 int sst_hsw_stream_get_mixer_id(struct sst_hsw *hsw,
 446         struct sst_hsw_stream *stream);
 447 u32 sst_hsw_stream_get_read_reg(struct sst_hsw *hsw,
 448         struct sst_hsw_stream *stream);
 449 u32 sst_hsw_stream_get_pointer_reg(struct sst_hsw *hsw,
 450         struct sst_hsw_stream *stream);
 451 u32 sst_hsw_stream_get_peak_reg(struct sst_hsw *hsw,
 452         struct sst_hsw_stream *stream, u32 channel);
 453 u32 sst_hsw_stream_get_vol_reg(struct sst_hsw *hsw,
 454         struct sst_hsw_stream *stream, u32 channel);
 455 int sst_hsw_mixer_get_info(struct sst_hsw *hsw);
 456
 457 /* Stream ALSA trigger operations */
 458 int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 459         int wait);
 460 int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 461         int wait);
 462 int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
 463
 464 /* Stream pointer positions */
 465 int sst_hsw_stream_get_read_pos(struct sst_hsw *hsw,
 466         struct sst_hsw_stream *stream, u32 *position);
 467 int sst_hsw_stream_get_write_pos(struct sst_hsw *hsw,
 468         struct sst_hsw_stream *stream, u32 *position);
 469 int sst_hsw_stream_set_write_position(struct sst_hsw *hsw,
 470         struct sst_hsw_stream *stream, u32 stage_id, u32 position);
 471 u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
 472         struct sst_hsw_stream *stream);
 473 u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
 474         struct sst_hsw_stream *stream);
 475
 476 /* HW port config */
 477 int sst_hsw_device_set_config(struct sst_hsw *hsw,
 478         enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
 479         enum sst_hsw_device_mode mode, u32 clock_divider);
 480
 481 /* DX Config */
 482 int sst_hsw_dx_set_state(struct sst_hsw *hsw,
 483         enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx);
 484 int sst_hsw_dx_get_state(struct sst_hsw *hsw, u32 item,
 485         u32 *offset, u32 *size, u32 *source);
 486
 487 /* init */
 488 int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata);
 489 void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata);
 490 struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw);
 491
 492 /* runtime module management */
 493 struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
 494         int mod_id, int offset);
 495 void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime);
 496
 497 /* PM */
 498 int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw);
 499 int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw);
 500 int sst_hsw_dsp_load(struct sst_hsw *hsw);
 501 int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw);
 502
 503 #endif