ixgbevf: Fix checksum error when using stacked vlan
[linux/fpc-iii.git] / sound / soc / ux500 / ux500_msp_dai.h
blob312ae535e35144c014a834bd62f7f0858b2a37b3
1 /*
2 * Copyright (C) ST-Ericsson SA 2012
4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
5 * Roger Nilsson <roger.xr.nilsson@stericsson.com>
6 * for ST-Ericsson.
8 * License terms:
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
15 #ifndef UX500_msp_dai_H
16 #define UX500_msp_dai_H
18 #include <linux/types.h>
19 #include <linux/spinlock.h>
21 #include "ux500_msp_i2s.h"
23 #define UX500_NBR_OF_DAI 4
25 #define UX500_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | \
26 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
28 #define UX500_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
30 #define FRAME_PER_SINGLE_SLOT_8_KHZ 31
31 #define FRAME_PER_SINGLE_SLOT_16_KHZ 124
32 #define FRAME_PER_SINGLE_SLOT_44_1_KHZ 63
33 #define FRAME_PER_SINGLE_SLOT_48_KHZ 49
34 #define FRAME_PER_2_SLOTS 31
35 #define FRAME_PER_8_SLOTS 138
36 #define FRAME_PER_16_SLOTS 277
38 #define UX500_MSP_INTERNAL_CLOCK_FREQ 40000000
39 #define UX500_MSP1_INTERNAL_CLOCK_FREQ UX500_MSP_INTERNAL_CLOCK_FREQ
41 #define UX500_MSP_MIN_CHANNELS 1
42 #define UX500_MSP_MAX_CHANNELS 8
44 #define PLAYBACK_CONFIGURED 1
45 #define CAPTURE_CONFIGURED 2
47 enum ux500_msp_clock_id {
48 UX500_MSP_MASTER_CLOCK,
51 struct ux500_msp_i2s_drvdata {
52 struct ux500_msp *msp;
53 struct regulator *reg_vape;
54 unsigned int fmt;
55 unsigned int tx_mask;
56 unsigned int rx_mask;
57 int slots;
58 int slot_width;
60 /* Clocks */
61 unsigned int master_clk;
62 struct clk *clk;
63 struct clk *pclk;
65 /* Regulators */
66 int vape_opp_constraint;
69 int ux500_msp_dai_set_data_delay(struct snd_soc_dai *dai, int delay);
71 #endif