1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2013 Freescale Semiconductor, Inc.
5 * CPU Frequency Scaling driver for Freescale QorIQ SoCs.
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/cpufreq.h>
13 #include <linux/errno.h>
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
19 #include <linux/slab.h>
20 #include <linux/smp.h>
21 #include <linux/platform_device.h>
25 * @pclk: the parent clock of cpu
26 * @table: frequency table
30 struct cpufreq_frequency_table
*table
;
34 * struct soc_data - SoC specific data
41 static u32
get_bus_freq(void)
43 struct device_node
*soc
;
48 /* get platform freq by searching bus-frequency property */
49 soc
= of_find_node_by_type(NULL
, "soc");
51 ret
= of_property_read_u32(soc
, "bus-frequency", &sysfreq
);
57 /* get platform freq by its clock name */
58 pltclk
= clk_get(NULL
, "cg-pll0-div1");
60 pr_err("%s: can't get bus frequency %ld\n",
61 __func__
, PTR_ERR(pltclk
));
62 return PTR_ERR(pltclk
);
65 return clk_get_rate(pltclk
);
68 static struct clk
*cpu_to_clk(int cpu
)
70 struct device_node
*np
;
73 if (!cpu_present(cpu
))
76 np
= of_get_cpu_node(cpu
, NULL
);
80 clk
= of_clk_get(np
, 0);
85 /* traverse cpu nodes to get cpu mask of sharing clock wire */
86 static void set_affected_cpus(struct cpufreq_policy
*policy
)
88 struct cpumask
*dstp
= policy
->cpus
;
92 for_each_present_cpu(i
) {
95 pr_err("%s: no clock for cpu %d\n", __func__
, i
);
99 if (clk_is_match(policy
->clk
, clk
))
100 cpumask_set_cpu(i
, dstp
);
104 /* reduce the duplicated frequencies in frequency table */
105 static void freq_table_redup(struct cpufreq_frequency_table
*freq_table
,
110 for (i
= 1; i
< count
; i
++) {
111 for (j
= 0; j
< i
; j
++) {
112 if (freq_table
[j
].frequency
== CPUFREQ_ENTRY_INVALID
||
113 freq_table
[j
].frequency
!=
114 freq_table
[i
].frequency
)
117 freq_table
[i
].frequency
= CPUFREQ_ENTRY_INVALID
;
123 /* sort the frequencies in frequency table in descenting order */
124 static void freq_table_sort(struct cpufreq_frequency_table
*freq_table
,
128 unsigned int freq
, max_freq
;
129 struct cpufreq_frequency_table table
;
131 for (i
= 0; i
< count
- 1; i
++) {
132 max_freq
= freq_table
[i
].frequency
;
134 for (j
= i
+ 1; j
< count
; j
++) {
135 freq
= freq_table
[j
].frequency
;
136 if (freq
== CPUFREQ_ENTRY_INVALID
||
144 /* exchange the frequencies */
145 table
.driver_data
= freq_table
[i
].driver_data
;
146 table
.frequency
= freq_table
[i
].frequency
;
147 freq_table
[i
].driver_data
= freq_table
[ind
].driver_data
;
148 freq_table
[i
].frequency
= freq_table
[ind
].frequency
;
149 freq_table
[ind
].driver_data
= table
.driver_data
;
150 freq_table
[ind
].frequency
= table
.frequency
;
155 static int qoriq_cpufreq_cpu_init(struct cpufreq_policy
*policy
)
157 struct device_node
*np
;
161 const struct clk_hw
*hwclk
;
162 struct cpufreq_frequency_table
*table
;
163 struct cpu_data
*data
;
164 unsigned int cpu
= policy
->cpu
;
167 np
= of_get_cpu_node(cpu
, NULL
);
171 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
175 policy
->clk
= of_clk_get(np
, 0);
176 if (IS_ERR(policy
->clk
)) {
177 pr_err("%s: no clock information\n", __func__
);
181 hwclk
= __clk_get_hw(policy
->clk
);
182 count
= clk_hw_get_num_parents(hwclk
);
184 data
->pclk
= kcalloc(count
, sizeof(struct clk
*), GFP_KERNEL
);
188 table
= kcalloc(count
+ 1, sizeof(*table
), GFP_KERNEL
);
192 for (i
= 0; i
< count
; i
++) {
193 clk
= clk_hw_get_parent_by_index(hwclk
, i
)->clk
;
195 freq
= clk_get_rate(clk
);
196 table
[i
].frequency
= freq
/ 1000;
197 table
[i
].driver_data
= i
;
199 freq_table_redup(table
, count
);
200 freq_table_sort(table
, count
);
201 table
[i
].frequency
= CPUFREQ_TABLE_END
;
202 policy
->freq_table
= table
;
205 /* update ->cpus if we have cluster, no harm if not */
206 set_affected_cpus(policy
);
207 policy
->driver_data
= data
;
209 /* Minimum transition latency is 12 platform clocks */
210 u64temp
= 12ULL * NSEC_PER_SEC
;
211 do_div(u64temp
, get_bus_freq());
212 policy
->cpuinfo
.transition_latency
= u64temp
+ 1;
228 static int qoriq_cpufreq_cpu_exit(struct cpufreq_policy
*policy
)
230 struct cpu_data
*data
= policy
->driver_data
;
235 policy
->driver_data
= NULL
;
240 static int qoriq_cpufreq_target(struct cpufreq_policy
*policy
,
244 struct cpu_data
*data
= policy
->driver_data
;
246 parent
= data
->pclk
[data
->table
[index
].driver_data
];
247 return clk_set_parent(policy
->clk
, parent
);
250 static struct cpufreq_driver qoriq_cpufreq_driver
= {
251 .name
= "qoriq_cpufreq",
252 .flags
= CPUFREQ_CONST_LOOPS
|
253 CPUFREQ_IS_COOLING_DEV
,
254 .init
= qoriq_cpufreq_cpu_init
,
255 .exit
= qoriq_cpufreq_cpu_exit
,
256 .verify
= cpufreq_generic_frequency_table_verify
,
257 .target_index
= qoriq_cpufreq_target
,
258 .get
= cpufreq_generic_get
,
259 .attr
= cpufreq_generic_attr
,
262 static const struct of_device_id qoriq_cpufreq_blacklist
[] = {
263 /* e6500 cannot use cpufreq due to erratum A-008083 */
264 { .compatible
= "fsl,b4420-clockgen", },
265 { .compatible
= "fsl,b4860-clockgen", },
266 { .compatible
= "fsl,t2080-clockgen", },
267 { .compatible
= "fsl,t4240-clockgen", },
271 static int qoriq_cpufreq_probe(struct platform_device
*pdev
)
274 struct device_node
*np
;
276 np
= of_find_matching_node(NULL
, qoriq_cpufreq_blacklist
);
278 dev_info(&pdev
->dev
, "Disabling due to erratum A-008083");
282 ret
= cpufreq_register_driver(&qoriq_cpufreq_driver
);
286 dev_info(&pdev
->dev
, "Freescale QorIQ CPU frequency scaling driver\n");
290 static int qoriq_cpufreq_remove(struct platform_device
*pdev
)
292 cpufreq_unregister_driver(&qoriq_cpufreq_driver
);
297 static struct platform_driver qoriq_cpufreq_platform_driver
= {
299 .name
= "qoriq-cpufreq",
301 .probe
= qoriq_cpufreq_probe
,
302 .remove
= qoriq_cpufreq_remove
,
304 module_platform_driver(qoriq_cpufreq_platform_driver
);
306 MODULE_ALIAS("platform:qoriq-cpufreq");
307 MODULE_LICENSE("GPL");
308 MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
309 MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");