?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'io_uring-5.11-2021-01-16' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / crypto / hisilicon / qm.c
blobf21ccae0e8ea8af257e7a2a68b02874d01040d3f
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 HiSilicon Limited. */
3 #include <asm/page.h>
4 #include <linux/acpi.h>
5 #include <linux/aer.h>
6 #include <linux/bitmap.h>
7 #include <linux/debugfs.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/idr.h>
10 #include <linux/io.h>
11 #include <linux/irqreturn.h>
12 #include <linux/log2.h>
13 #include <linux/seq_file.h>
14 #include <linux/slab.h>
15 #include <linux/uacce.h>
16 #include <linux/uaccess.h>
17 #include <uapi/misc/uacce/hisi_qm.h>
18 #include "qm.h"
19
20 /* eq/aeq irq enable */
21 #define QM_VF_AEQ_INT_SOURCE 0x0
22 #define QM_VF_AEQ_INT_MASK 0x4
23 #define QM_VF_EQ_INT_SOURCE 0x8
24 #define QM_VF_EQ_INT_MASK 0xc
25 #define QM_IRQ_NUM_V1 1
26 #define QM_IRQ_NUM_PF_V2 4
27 #define QM_IRQ_NUM_VF_V2 2
28
29 #define QM_EQ_EVENT_IRQ_VECTOR 0
30 #define QM_AEQ_EVENT_IRQ_VECTOR 1
31 #define QM_ABNORMAL_EVENT_IRQ_VECTOR 3
32
33 /* mailbox */
34 #define QM_MB_CMD_SQC 0x0
35 #define QM_MB_CMD_CQC 0x1
36 #define QM_MB_CMD_EQC 0x2
37 #define QM_MB_CMD_AEQC 0x3
38 #define QM_MB_CMD_SQC_BT 0x4
39 #define QM_MB_CMD_CQC_BT 0x5
40 #define QM_MB_CMD_SQC_VFT_V2 0x6
41
42 #define QM_MB_CMD_SEND_BASE 0x300
43 #define QM_MB_EVENT_SHIFT 8
44 #define QM_MB_BUSY_SHIFT 13
45 #define QM_MB_OP_SHIFT 14
46 #define QM_MB_CMD_DATA_ADDR_L 0x304
47 #define QM_MB_CMD_DATA_ADDR_H 0x308
48
49 /* sqc shift */
50 #define QM_SQ_HOP_NUM_SHIFT 0
51 #define QM_SQ_PAGE_SIZE_SHIFT 4
52 #define QM_SQ_BUF_SIZE_SHIFT 8
53 #define QM_SQ_SQE_SIZE_SHIFT 12
54 #define QM_SQ_PRIORITY_SHIFT 0
55 #define QM_SQ_ORDERS_SHIFT 4
56 #define QM_SQ_TYPE_SHIFT 8
57
58 #define QM_SQ_TYPE_MASK GENMASK(3, 0)
59 #define QM_SQ_TAIL_IDX(sqc) ((le16_to_cpu((sqc)->w11) >> 6) & 0x1)
60
61 /* cqc shift */
62 #define QM_CQ_HOP_NUM_SHIFT 0
63 #define QM_CQ_PAGE_SIZE_SHIFT 4
64 #define QM_CQ_BUF_SIZE_SHIFT 8
65 #define QM_CQ_CQE_SIZE_SHIFT 12
66 #define QM_CQ_PHASE_SHIFT 0
67 #define QM_CQ_FLAG_SHIFT 1
68
69 #define QM_CQE_PHASE(cqe) (le16_to_cpu((cqe)->w7) & 0x1)
70 #define QM_QC_CQE_SIZE 4
71 #define QM_CQ_TAIL_IDX(cqc) ((le16_to_cpu((cqc)->w11) >> 6) & 0x1)
72
73 /* eqc shift */
74 #define QM_EQE_AEQE_SIZE (2UL << 12)
75 #define QM_EQC_PHASE_SHIFT 16
76
77 #define QM_EQE_PHASE(eqe) ((le32_to_cpu((eqe)->dw0) >> 16) & 0x1)
78 #define QM_EQE_CQN_MASK GENMASK(15, 0)
79
80 #define QM_AEQE_PHASE(aeqe) ((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1)
81 #define QM_AEQE_TYPE_SHIFT 17
82
83 #define QM_DOORBELL_CMD_SQ 0
84 #define QM_DOORBELL_CMD_CQ 1
85 #define QM_DOORBELL_CMD_EQ 2
86 #define QM_DOORBELL_CMD_AEQ 3
87
88 #define QM_DOORBELL_BASE_V1 0x340
89 #define QM_DB_CMD_SHIFT_V1 16
90 #define QM_DB_INDEX_SHIFT_V1 32
91 #define QM_DB_PRIORITY_SHIFT_V1 48
92 #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
93 #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
94 #define QM_DB_CMD_SHIFT_V2 12
95 #define QM_DB_RAND_SHIFT_V2 16
96 #define QM_DB_INDEX_SHIFT_V2 32
97 #define QM_DB_PRIORITY_SHIFT_V2 48
98
99 #define QM_MEM_START_INIT 0x100040
100 #define QM_MEM_INIT_DONE 0x100044
101 #define QM_VFT_CFG_RDY 0x10006c
102 #define QM_VFT_CFG_OP_WR 0x100058
103 #define QM_VFT_CFG_TYPE 0x10005c
104 #define QM_SQC_VFT 0x0
105 #define QM_CQC_VFT 0x1
106 #define QM_VFT_CFG 0x100060
107 #define QM_VFT_CFG_OP_ENABLE 0x100054
108
109 #define QM_VFT_CFG_DATA_L 0x100064
110 #define QM_VFT_CFG_DATA_H 0x100068
111 #define QM_SQC_VFT_BUF_SIZE (7ULL << 8)
112 #define QM_SQC_VFT_SQC_SIZE (5ULL << 12)
113 #define QM_SQC_VFT_INDEX_NUMBER (1ULL << 16)
114 #define QM_SQC_VFT_START_SQN_SHIFT 28
115 #define QM_SQC_VFT_VALID (1ULL << 44)
116 #define QM_SQC_VFT_SQN_SHIFT 45
117 #define QM_CQC_VFT_BUF_SIZE (7ULL << 8)
118 #define QM_CQC_VFT_SQC_SIZE (5ULL << 12)
119 #define QM_CQC_VFT_INDEX_NUMBER (1ULL << 16)
120 #define QM_CQC_VFT_VALID (1ULL << 28)
121
122 #define QM_SQC_VFT_BASE_SHIFT_V2 28
123 #define QM_SQC_VFT_BASE_MASK_V2 GENMASK(5, 0)
124 #define QM_SQC_VFT_NUM_SHIFT_V2 45
125 #define QM_SQC_VFT_NUM_MASK_v2 GENMASK(9, 0)
126
127 #define QM_DFX_CNT_CLR_CE 0x100118
128
129 #define QM_ABNORMAL_INT_SOURCE 0x100000
130 #define QM_ABNORMAL_INT_SOURCE_CLR GENMASK(12, 0)
131 #define QM_ABNORMAL_INT_MASK 0x100004
132 #define QM_ABNORMAL_INT_MASK_VALUE 0x1fff
133 #define QM_ABNORMAL_INT_STATUS 0x100008
134 #define QM_ABNORMAL_INT_SET 0x10000c
135 #define QM_ABNORMAL_INF00 0x100010
136 #define QM_FIFO_OVERFLOW_TYPE 0xc0
137 #define QM_FIFO_OVERFLOW_TYPE_SHIFT 6
138 #define QM_FIFO_OVERFLOW_VF 0x3f
139 #define QM_ABNORMAL_INF01 0x100014
140 #define QM_DB_TIMEOUT_TYPE 0xc0
141 #define QM_DB_TIMEOUT_TYPE_SHIFT 6
142 #define QM_DB_TIMEOUT_VF 0x3f
143 #define QM_RAS_CE_ENABLE 0x1000ec
144 #define QM_RAS_FE_ENABLE 0x1000f0
145 #define QM_RAS_NFE_ENABLE 0x1000f4
146 #define QM_RAS_CE_THRESHOLD 0x1000f8
147 #define QM_RAS_CE_TIMES_PER_IRQ 1
148 #define QM_RAS_MSI_INT_SEL 0x1040f4
149
150 #define QM_DEV_RESET_FLAG 0
151 #define QM_RESET_WAIT_TIMEOUT 400
152 #define QM_PEH_VENDOR_ID 0x1000d8
153 #define ACC_VENDOR_ID_VALUE 0x5a5a
154 #define QM_PEH_DFX_INFO0 0x1000fc
155 #define ACC_PEH_SRIOV_CTRL_VF_MSE_SHIFT 3
156 #define ACC_PEH_MSI_DISABLE GENMASK(31, 0)
157 #define ACC_MASTER_GLOBAL_CTRL_SHUTDOWN 0x1
158 #define ACC_MASTER_TRANS_RETURN_RW 3
159 #define ACC_MASTER_TRANS_RETURN 0x300150
160 #define ACC_MASTER_GLOBAL_CTRL 0x300000
161 #define ACC_AM_CFG_PORT_WR_EN 0x30001c
162 #define QM_RAS_NFE_MBIT_DISABLE ~QM_ECC_MBIT
163 #define ACC_AM_ROB_ECC_INT_STS 0x300104
164 #define ACC_ROB_ECC_ERR_MULTPL BIT(1)
165
166 #define POLL_PERIOD 10
167 #define POLL_TIMEOUT 1000
168 #define WAIT_PERIOD_US_MAX 200
169 #define WAIT_PERIOD_US_MIN 100
170 #define MAX_WAIT_COUNTS 1000
171 #define QM_CACHE_WB_START 0x204
172 #define QM_CACHE_WB_DONE 0x208
173
174 #define PCI_BAR_2 2
175 #define QM_SQE_DATA_ALIGN_MASK GENMASK(6, 0)
176 #define QMC_ALIGN(sz) ALIGN(sz, 32)
177
178 #define QM_DBG_READ_LEN 256
179 #define QM_DBG_WRITE_LEN 1024
180 #define QM_DBG_TMP_BUF_LEN 22
181 #define QM_PCI_COMMAND_INVALID ~0
182
183 #define WAIT_PERIOD 20
184 #define REMOVE_WAIT_DELAY 10
185 #define QM_SQE_ADDR_MASK GENMASK(7, 0)
186 #define QM_EQ_DEPTH (1024 * 2)
187
188 #define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \
189 (((hop_num) << QM_CQ_HOP_NUM_SHIFT) | \
190 ((pg_sz) << QM_CQ_PAGE_SIZE_SHIFT) | \
191 ((buf_sz) << QM_CQ_BUF_SIZE_SHIFT) | \
192 ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT))
193
194 #define QM_MK_CQC_DW3_V2(cqe_sz) \
195 ((QM_Q_DEPTH - 1) | ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT))
196
197 #define QM_MK_SQC_W13(priority, orders, alg_type) \
198 (((priority) << QM_SQ_PRIORITY_SHIFT) | \
199 ((orders) << QM_SQ_ORDERS_SHIFT) | \
200 (((alg_type) & QM_SQ_TYPE_MASK) << QM_SQ_TYPE_SHIFT))
201
202 #define QM_MK_SQC_DW3_V1(hop_num, pg_sz, buf_sz, sqe_sz) \
203 (((hop_num) << QM_SQ_HOP_NUM_SHIFT) | \
204 ((pg_sz) << QM_SQ_PAGE_SIZE_SHIFT) | \
205 ((buf_sz) << QM_SQ_BUF_SIZE_SHIFT) | \
206 ((u32)ilog2(sqe_sz) << QM_SQ_SQE_SIZE_SHIFT))
207
208 #define QM_MK_SQC_DW3_V2(sqe_sz) \
209 ((QM_Q_DEPTH - 1) | ((u32)ilog2(sqe_sz) << QM_SQ_SQE_SIZE_SHIFT))
210
211 #define INIT_QC_COMMON(qc, base, pasid) do { \
212 (qc)->head = 0; \
213 (qc)->tail = 0; \
214 (qc)->base_l = cpu_to_le32(lower_32_bits(base)); \
215 (qc)->base_h = cpu_to_le32(upper_32_bits(base)); \
216 (qc)->dw3 = 0; \
217 (qc)->w8 = 0; \
218 (qc)->rsvd0 = 0; \
219 (qc)->pasid = cpu_to_le16(pasid); \
220 (qc)->w11 = 0; \
221 (qc)->rsvd1 = 0; \
222 } while (0)
223
224 enum vft_type {
225 SQC_VFT = 0,
226 CQC_VFT,
227 };
228
229 enum acc_err_result {
230 ACC_ERR_NONE,
231 ACC_ERR_NEED_RESET,
232 ACC_ERR_RECOVERED,
233 };
234
235 struct qm_cqe {
236 __le32 rsvd0;
237 __le16 cmd_id;
238 __le16 rsvd1;
239 __le16 sq_head;
240 __le16 sq_num;
241 __le16 rsvd2;
242 __le16 w7;
243 };
244
245 struct qm_eqe {
246 __le32 dw0;
247 };
248
249 struct qm_aeqe {
250 __le32 dw0;
251 };
252
253 struct qm_sqc {
254 __le16 head;
255 __le16 tail;
256 __le32 base_l;
257 __le32 base_h;
258 __le32 dw3;
259 __le16 w8;
260 __le16 rsvd0;
261 __le16 pasid;
262 __le16 w11;
263 __le16 cq_num;
264 __le16 w13;
265 __le32 rsvd1;
266 };
267
268 struct qm_cqc {
269 __le16 head;
270 __le16 tail;
271 __le32 base_l;
272 __le32 base_h;
273 __le32 dw3;
274 __le16 w8;
275 __le16 rsvd0;
276 __le16 pasid;
277 __le16 w11;
278 __le32 dw6;
279 __le32 rsvd1;
280 };
281
282 struct qm_eqc {
283 __le16 head;
284 __le16 tail;
285 __le32 base_l;
286 __le32 base_h;
287 __le32 dw3;
288 __le32 rsvd[2];
289 __le32 dw6;
290 };
291
292 struct qm_aeqc {
293 __le16 head;
294 __le16 tail;
295 __le32 base_l;
296 __le32 base_h;
297 __le32 dw3;
298 __le32 rsvd[2];
299 __le32 dw6;
300 };
301
302 struct qm_mailbox {
303 __le16 w0;
304 __le16 queue_num;
305 __le32 base_l;
306 __le32 base_h;
307 __le32 rsvd;
308 };
309
310 struct qm_doorbell {
311 __le16 queue_num;
312 __le16 cmd;
313 __le16 index;
314 __le16 priority;
315 };
316
317 struct hisi_qm_resource {
318 struct hisi_qm *qm;
319 int distance;
320 struct list_head list;
321 };
322
323 struct hisi_qm_hw_ops {
324 int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number);
325 void (*qm_db)(struct hisi_qm *qm, u16 qn,
326 u8 cmd, u16 index, u8 priority);
327 u32 (*get_irq_num)(struct hisi_qm *qm);
328 int (*debug_init)(struct hisi_qm *qm);
329 void (*hw_error_init)(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe);
330 void (*hw_error_uninit)(struct hisi_qm *qm);
331 enum acc_err_result (*hw_error_handle)(struct hisi_qm *qm);
332 };
333
334 struct qm_dfx_item {
335 const char *name;
336 u32 offset;
337 };
338
339 static struct qm_dfx_item qm_dfx_files[] = {
340 {"err_irq", offsetof(struct qm_dfx, err_irq_cnt)},
341 {"aeq_irq", offsetof(struct qm_dfx, aeq_irq_cnt)},
342 {"abnormal_irq", offsetof(struct qm_dfx, abnormal_irq_cnt)},
343 {"create_qp_err", offsetof(struct qm_dfx, create_qp_err_cnt)},
344 {"mb_err", offsetof(struct qm_dfx, mb_err_cnt)},
345 };
346
347 static const char * const qm_debug_file_name[] = {
348 [CURRENT_Q] = "current_q",
349 [CLEAR_ENABLE] = "clear_enable",
350 };
351
352 struct hisi_qm_hw_error {
353 u32 int_msk;
354 const char *msg;
355 };
356
357 static const struct hisi_qm_hw_error qm_hw_error[] = {
358 { .int_msk = BIT(0), .msg = "qm_axi_rresp" },
359 { .int_msk = BIT(1), .msg = "qm_axi_bresp" },
360 { .int_msk = BIT(2), .msg = "qm_ecc_mbit" },
361 { .int_msk = BIT(3), .msg = "qm_ecc_1bit" },
362 { .int_msk = BIT(4), .msg = "qm_acc_get_task_timeout" },
363 { .int_msk = BIT(5), .msg = "qm_acc_do_task_timeout" },
364 { .int_msk = BIT(6), .msg = "qm_acc_wb_not_ready_timeout" },
365 { .int_msk = BIT(7), .msg = "qm_sq_cq_vf_invalid" },
366 { .int_msk = BIT(8), .msg = "qm_cq_vf_invalid" },
367 { .int_msk = BIT(9), .msg = "qm_sq_vf_invalid" },
368 { .int_msk = BIT(10), .msg = "qm_db_timeout" },
369 { .int_msk = BIT(11), .msg = "qm_of_fifo_of" },
370 { .int_msk = BIT(12), .msg = "qm_db_random_invalid" },
371 { /* sentinel */ }
372 };
373
374 static const char * const qm_db_timeout[] = {
375 "sq", "cq", "eq", "aeq",
376 };
377
378 static const char * const qm_fifo_overflow[] = {
379 "cq", "eq", "aeq",
380 };
381
382 static const char * const qm_s[] = {
383 "init", "start", "close", "stop",
384 };
385
386 static const char * const qp_s[] = {
387 "none", "init", "start", "stop", "close",
388 };
389
390 static bool qm_avail_state(struct hisi_qm *qm, enum qm_state new)
391 {
392 enum qm_state curr = atomic_read(&qm->status.flags);
393 bool avail = false;
394
395 switch (curr) {
396 case QM_INIT:
397 if (new == QM_START || new == QM_CLOSE)
398 avail = true;
399 break;
400 case QM_START:
401 if (new == QM_STOP)
402 avail = true;
403 break;
404 case QM_STOP:
405 if (new == QM_CLOSE || new == QM_START)
406 avail = true;
407 break;
408 default:
409 break;
410 }
411
412 dev_dbg(&qm->pdev->dev, "change qm state from %s to %s\n",
413 qm_s[curr], qm_s[new]);
414
415 if (!avail)
416 dev_warn(&qm->pdev->dev, "Can not change qm state from %s to %s\n",
417 qm_s[curr], qm_s[new]);
418
419 return avail;
420 }
421
422 static bool qm_qp_avail_state(struct hisi_qm *qm, struct hisi_qp *qp,
423 enum qp_state new)
424 {
425 enum qm_state qm_curr = atomic_read(&qm->status.flags);
426 enum qp_state qp_curr = 0;
427 bool avail = false;
428
429 if (qp)
430 qp_curr = atomic_read(&qp->qp_status.flags);
431
432 switch (new) {
433 case QP_INIT:
434 if (qm_curr == QM_START || qm_curr == QM_INIT)
435 avail = true;
436 break;
437 case QP_START:
438 if ((qm_curr == QM_START && qp_curr == QP_INIT) ||
439 (qm_curr == QM_START && qp_curr == QP_STOP))
440 avail = true;
441 break;
442 case QP_STOP:
443 if ((qm_curr == QM_START && qp_curr == QP_START) ||
444 (qp_curr == QP_INIT))
445 avail = true;
446 break;
447 case QP_CLOSE:
448 if ((qm_curr == QM_START && qp_curr == QP_INIT) ||
449 (qm_curr == QM_START && qp_curr == QP_STOP) ||
450 (qm_curr == QM_STOP && qp_curr == QP_STOP) ||
451 (qm_curr == QM_STOP && qp_curr == QP_INIT))
452 avail = true;
453 break;
454 default:
455 break;
456 }
457
458 dev_dbg(&qm->pdev->dev, "change qp state from %s to %s in QM %s\n",
459 qp_s[qp_curr], qp_s[new], qm_s[qm_curr]);
460
461 if (!avail)
462 dev_warn(&qm->pdev->dev,
463 "Can not change qp state from %s to %s in QM %s\n",
464 qp_s[qp_curr], qp_s[new], qm_s[qm_curr]);
465
466 return avail;
467 }
468
469 /* return 0 mailbox ready, -ETIMEDOUT hardware timeout */
470 static int qm_wait_mb_ready(struct hisi_qm *qm)
471 {
472 u32 val;
473
474 return readl_relaxed_poll_timeout(qm->io_base + QM_MB_CMD_SEND_BASE,
475 val, !((val >> QM_MB_BUSY_SHIFT) &
476 0x1), POLL_PERIOD, POLL_TIMEOUT);
477 }
478
479 /* 128 bit should be written to hardware at one time to trigger a mailbox */
480 static void qm_mb_write(struct hisi_qm *qm, const void *src)
481 {
482 void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
483 unsigned long tmp0 = 0, tmp1 = 0;
484
485 if (!IS_ENABLED(CONFIG_ARM64)) {
486 memcpy_toio(fun_base, src, 16);
487 wmb();
488 return;
489 }
490
491 asm volatile("ldp %0, %1, %3\n"
492 "stp %0, %1, %2\n"
493 "dsb sy\n"
494 : "=&r" (tmp0),
495 "=&r" (tmp1),
496 "+Q" (*((char __iomem *)fun_base))
497 : "Q" (*((char *)src))
498 : "memory");
499 }
500
501 static int qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
502 bool op)
503 {
504 struct qm_mailbox mailbox;
505 int ret = 0;
506
507 dev_dbg(&qm->pdev->dev, "QM mailbox request to q%u: %u-%llx\n",
508 queue, cmd, (unsigned long long)dma_addr);
509
510 mailbox.w0 = cpu_to_le16(cmd |
511 (op ? 0x1 << QM_MB_OP_SHIFT : 0) |
512 (0x1 << QM_MB_BUSY_SHIFT));
513 mailbox.queue_num = cpu_to_le16(queue);
514 mailbox.base_l = cpu_to_le32(lower_32_bits(dma_addr));
515 mailbox.base_h = cpu_to_le32(upper_32_bits(dma_addr));
516 mailbox.rsvd = 0;
517
518 mutex_lock(&qm->mailbox_lock);
519
520 if (unlikely(qm_wait_mb_ready(qm))) {
521 ret = -EBUSY;
522 dev_err(&qm->pdev->dev, "QM mailbox is busy to start!\n");
523 goto busy_unlock;
524 }
525
526 qm_mb_write(qm, &mailbox);
527
528 if (unlikely(qm_wait_mb_ready(qm))) {
529 ret = -EBUSY;
530 dev_err(&qm->pdev->dev, "QM mailbox operation timeout!\n");
531 goto busy_unlock;
532 }
533
534 busy_unlock:
535 mutex_unlock(&qm->mailbox_lock);
536
537 if (ret)
538 atomic64_inc(&qm->debug.dfx.mb_err_cnt);
539 return ret;
540 }
541
542 static void qm_db_v1(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
543 {
544 u64 doorbell;
545
546 doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V1) |
547 ((u64)index << QM_DB_INDEX_SHIFT_V1) |
548 ((u64)priority << QM_DB_PRIORITY_SHIFT_V1);
549
550 writeq(doorbell, qm->io_base + QM_DOORBELL_BASE_V1);
551 }
552
553 static void qm_db_v2(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
554 {
555 u64 doorbell;
556 u64 dbase;
557 u16 randata = 0;
558
559 if (cmd == QM_DOORBELL_CMD_SQ || cmd == QM_DOORBELL_CMD_CQ)
560 dbase = QM_DOORBELL_SQ_CQ_BASE_V2;
561 else
562 dbase = QM_DOORBELL_EQ_AEQ_BASE_V2;
563
564 doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V2) |
565 ((u64)randata << QM_DB_RAND_SHIFT_V2) |
566 ((u64)index << QM_DB_INDEX_SHIFT_V2) |
567 ((u64)priority << QM_DB_PRIORITY_SHIFT_V2);
568
569 writeq(doorbell, qm->io_base + dbase);
570 }
571
572 static void qm_db(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
573 {
574 dev_dbg(&qm->pdev->dev, "QM doorbell request: qn=%u, cmd=%u, index=%u\n",
575 qn, cmd, index);
576
577 qm->ops->qm_db(qm, qn, cmd, index, priority);
578 }
579
580 static int qm_dev_mem_reset(struct hisi_qm *qm)
581 {
582 u32 val;
583
584 writel(0x1, qm->io_base + QM_MEM_START_INIT);
585 return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val,
586 val & BIT(0), POLL_PERIOD,
587 POLL_TIMEOUT);
588 }
589
590 static u32 qm_get_irq_num_v1(struct hisi_qm *qm)
591 {
592 return QM_IRQ_NUM_V1;
593 }
594
595 static u32 qm_get_irq_num_v2(struct hisi_qm *qm)
596 {
597 if (qm->fun_type == QM_HW_PF)
598 return QM_IRQ_NUM_PF_V2;
599 else
600 return QM_IRQ_NUM_VF_V2;
601 }
602
603 static struct hisi_qp *qm_to_hisi_qp(struct hisi_qm *qm, struct qm_eqe *eqe)
604 {
605 u16 cqn = le32_to_cpu(eqe->dw0) & QM_EQE_CQN_MASK;
606
607 return &qm->qp_array[cqn];
608 }
609
610 static void qm_cq_head_update(struct hisi_qp *qp)
611 {
612 if (qp->qp_status.cq_head == QM_Q_DEPTH - 1) {
613 qp->qp_status.cqc_phase = !qp->qp_status.cqc_phase;
614 qp->qp_status.cq_head = 0;
615 } else {
616 qp->qp_status.cq_head++;
617 }
618 }
619
620 static void qm_poll_qp(struct hisi_qp *qp, struct hisi_qm *qm)
621 {
622 if (qp->event_cb) {
623 qp->event_cb(qp);
624 return;
625 }
626
627 if (qp->req_cb) {
628 struct qm_cqe *cqe = qp->cqe + qp->qp_status.cq_head;
629
630 while (QM_CQE_PHASE(cqe) == qp->qp_status.cqc_phase) {
631 dma_rmb();
632 qp->req_cb(qp, qp->sqe + qm->sqe_size *
633 le16_to_cpu(cqe->sq_head));
634 qm_cq_head_update(qp);
635 cqe = qp->cqe + qp->qp_status.cq_head;
636 qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ,
637 qp->qp_status.cq_head, 0);
638 atomic_dec(&qp->qp_status.used);
639 }
640
641 /* set c_flag */
642 qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ,
643 qp->qp_status.cq_head, 1);
644 }
645 }
646
647 static void qm_work_process(struct work_struct *work)
648 {
649 struct hisi_qm *qm = container_of(work, struct hisi_qm, work);
650 struct qm_eqe *eqe = qm->eqe + qm->status.eq_head;
651 struct hisi_qp *qp;
652 int eqe_num = 0;
653
654 while (QM_EQE_PHASE(eqe) == qm->status.eqc_phase) {
655 eqe_num++;
656 qp = qm_to_hisi_qp(qm, eqe);
657 qm_poll_qp(qp, qm);
658
659 if (qm->status.eq_head == QM_EQ_DEPTH - 1) {
660 qm->status.eqc_phase = !qm->status.eqc_phase;
661 eqe = qm->eqe;
662 qm->status.eq_head = 0;
663 } else {
664 eqe++;
665 qm->status.eq_head++;
666 }
667
668 if (eqe_num == QM_EQ_DEPTH / 2 - 1) {
669 eqe_num = 0;
670 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
671 }
672 }
673
674 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
675 }
676
677 static irqreturn_t do_qm_irq(int irq, void *data)
678 {
679 struct hisi_qm *qm = (struct hisi_qm *)data;
680
681 /* the workqueue created by device driver of QM */
682 if (qm->wq)
683 queue_work(qm->wq, &qm->work);
684 else
685 schedule_work(&qm->work);
686
687 return IRQ_HANDLED;
688 }
689
690 static irqreturn_t qm_irq(int irq, void *data)
691 {
692 struct hisi_qm *qm = data;
693
694 if (readl(qm->io_base + QM_VF_EQ_INT_SOURCE))
695 return do_qm_irq(irq, data);
696
697 atomic64_inc(&qm->debug.dfx.err_irq_cnt);
698 dev_err(&qm->pdev->dev, "invalid int source\n");
699 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
700
701 return IRQ_NONE;
702 }
703
704 static irqreturn_t qm_aeq_irq(int irq, void *data)
705 {
706 struct hisi_qm *qm = data;
707 struct qm_aeqe *aeqe = qm->aeqe + qm->status.aeq_head;
708 u32 type;
709
710 atomic64_inc(&qm->debug.dfx.aeq_irq_cnt);
711 if (!readl(qm->io_base + QM_VF_AEQ_INT_SOURCE))
712 return IRQ_NONE;
713
714 while (QM_AEQE_PHASE(aeqe) == qm->status.aeqc_phase) {
715 type = le32_to_cpu(aeqe->dw0) >> QM_AEQE_TYPE_SHIFT;
716 if (type < ARRAY_SIZE(qm_fifo_overflow))
717 dev_err(&qm->pdev->dev, "%s overflow\n",
718 qm_fifo_overflow[type]);
719 else
720 dev_err(&qm->pdev->dev, "unknown error type %d\n",
721 type);
722
723 if (qm->status.aeq_head == QM_Q_DEPTH - 1) {
724 qm->status.aeqc_phase = !qm->status.aeqc_phase;
725 aeqe = qm->aeqe;
726 qm->status.aeq_head = 0;
727 } else {
728 aeqe++;
729 qm->status.aeq_head++;
730 }
731
732 qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0);
733 }
734
735 return IRQ_HANDLED;
736 }
737
738 static void qm_irq_unregister(struct hisi_qm *qm)
739 {
740 struct pci_dev *pdev = qm->pdev;
741
742 free_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), qm);
743
744 if (qm->ver == QM_HW_V1)
745 return;
746
747 free_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), qm);
748
749 if (qm->fun_type == QM_HW_PF)
750 free_irq(pci_irq_vector(pdev,
751 QM_ABNORMAL_EVENT_IRQ_VECTOR), qm);
752 }
753
754 static void qm_init_qp_status(struct hisi_qp *qp)
755 {
756 struct hisi_qp_status *qp_status = &qp->qp_status;
757
758 qp_status->sq_tail = 0;
759 qp_status->cq_head = 0;
760 qp_status->cqc_phase = true;
761 atomic_set(&qp_status->used, 0);
762 }
763
764 static void qm_vft_data_cfg(struct hisi_qm *qm, enum vft_type type, u32 base,
765 u32 number)
766 {
767 u64 tmp = 0;
768
769 if (number > 0) {
770 switch (type) {
771 case SQC_VFT:
772 if (qm->ver == QM_HW_V1) {
773 tmp = QM_SQC_VFT_BUF_SIZE |
774 QM_SQC_VFT_SQC_SIZE |
775 QM_SQC_VFT_INDEX_NUMBER |
776 QM_SQC_VFT_VALID |
777 (u64)base << QM_SQC_VFT_START_SQN_SHIFT;
778 } else {
779 tmp = (u64)base << QM_SQC_VFT_START_SQN_SHIFT |
780 QM_SQC_VFT_VALID |
781 (u64)(number - 1) << QM_SQC_VFT_SQN_SHIFT;
782 }
783 break;
784 case CQC_VFT:
785 if (qm->ver == QM_HW_V1) {
786 tmp = QM_CQC_VFT_BUF_SIZE |
787 QM_CQC_VFT_SQC_SIZE |
788 QM_CQC_VFT_INDEX_NUMBER |
789 QM_CQC_VFT_VALID;
790 } else {
791 tmp = QM_CQC_VFT_VALID;
792 }
793 break;
794 }
795 }
796
797 writel(lower_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_L);
798 writel(upper_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_H);
799 }
800
801 static int qm_set_vft_common(struct hisi_qm *qm, enum vft_type type,
802 u32 fun_num, u32 base, u32 number)
803 {
804 unsigned int val;
805 int ret;
806
807 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
808 val & BIT(0), POLL_PERIOD,
809 POLL_TIMEOUT);
810 if (ret)
811 return ret;
812
813 writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR);
814 writel(type, qm->io_base + QM_VFT_CFG_TYPE);
815 writel(fun_num, qm->io_base + QM_VFT_CFG);
816
817 qm_vft_data_cfg(qm, type, base, number);
818
819 writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
820 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
821
822 return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
823 val & BIT(0), POLL_PERIOD,
824 POLL_TIMEOUT);
825 }
826
827 /* The config should be conducted after qm_dev_mem_reset() */
828 static int qm_set_sqc_cqc_vft(struct hisi_qm *qm, u32 fun_num, u32 base,
829 u32 number)
830 {
831 int ret, i;
832
833 for (i = SQC_VFT; i <= CQC_VFT; i++) {
834 ret = qm_set_vft_common(qm, i, fun_num, base, number);
835 if (ret)
836 return ret;
837 }
838
839 return 0;
840 }
841
842 static int qm_get_vft_v2(struct hisi_qm *qm, u32 *base, u32 *number)
843 {
844 u64 sqc_vft;
845 int ret;
846
847 ret = qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1);
848 if (ret)
849 return ret;
850
851 sqc_vft = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
852 ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
853 *base = QM_SQC_VFT_BASE_MASK_V2 & (sqc_vft >> QM_SQC_VFT_BASE_SHIFT_V2);
854 *number = (QM_SQC_VFT_NUM_MASK_v2 &
855 (sqc_vft >> QM_SQC_VFT_NUM_SHIFT_V2)) + 1;
856
857 return 0;
858 }
859
860 static struct hisi_qm *file_to_qm(struct debugfs_file *file)
861 {
862 struct qm_debug *debug = file->debug;
863
864 return container_of(debug, struct hisi_qm, debug);
865 }
866
867 static u32 current_q_read(struct debugfs_file *file)
868 {
869 struct hisi_qm *qm = file_to_qm(file);
870
871 return readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) >> QM_DFX_QN_SHIFT;
872 }
873
874 static int current_q_write(struct debugfs_file *file, u32 val)
875 {
876 struct hisi_qm *qm = file_to_qm(file);
877 u32 tmp;
878
879 if (val >= qm->debug.curr_qm_qp_num)
880 return -EINVAL;
881
882 tmp = val << QM_DFX_QN_SHIFT |
883 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_FUN_MASK);
884 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
885
886 tmp = val << QM_DFX_QN_SHIFT |
887 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_FUN_MASK);
888 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
889
890 return 0;
891 }
892
893 static u32 clear_enable_read(struct debugfs_file *file)
894 {
895 struct hisi_qm *qm = file_to_qm(file);
896
897 return readl(qm->io_base + QM_DFX_CNT_CLR_CE);
898 }
899
900 /* rd_clr_ctrl 1 enable read clear, otherwise 0 disable it */
901 static int clear_enable_write(struct debugfs_file *file, u32 rd_clr_ctrl)
902 {
903 struct hisi_qm *qm = file_to_qm(file);
904
905 if (rd_clr_ctrl > 1)
906 return -EINVAL;
907
908 writel(rd_clr_ctrl, qm->io_base + QM_DFX_CNT_CLR_CE);
909
910 return 0;
911 }
912
913 static ssize_t qm_debug_read(struct file *filp, char __user *buf,
914 size_t count, loff_t *pos)
915 {
916 struct debugfs_file *file = filp->private_data;
917 enum qm_debug_file index = file->index;
918 char tbuf[QM_DBG_TMP_BUF_LEN];
919 u32 val;
920 int ret;
921
922 mutex_lock(&file->lock);
923 switch (index) {
924 case CURRENT_Q:
925 val = current_q_read(file);
926 break;
927 case CLEAR_ENABLE:
928 val = clear_enable_read(file);
929 break;
930 default:
931 mutex_unlock(&file->lock);
932 return -EINVAL;
933 }
934 mutex_unlock(&file->lock);
935
936 ret = scnprintf(tbuf, QM_DBG_TMP_BUF_LEN, "%u\n", val);
937 return simple_read_from_buffer(buf, count, pos, tbuf, ret);
938 }
939
940 static ssize_t qm_debug_write(struct file *filp, const char __user *buf,
941 size_t count, loff_t *pos)
942 {
943 struct debugfs_file *file = filp->private_data;
944 enum qm_debug_file index = file->index;
945 unsigned long val;
946 char tbuf[QM_DBG_TMP_BUF_LEN];
947 int len, ret;
948
949 if (*pos != 0)
950 return 0;
951
952 if (count >= QM_DBG_TMP_BUF_LEN)
953 return -ENOSPC;
954
955 len = simple_write_to_buffer(tbuf, QM_DBG_TMP_BUF_LEN - 1, pos, buf,
956 count);
957 if (len < 0)
958 return len;
959
960 tbuf[len] = '\0';
961 if (kstrtoul(tbuf, 0, &val))
962 return -EFAULT;
963
964 mutex_lock(&file->lock);
965 switch (index) {
966 case CURRENT_Q:
967 ret = current_q_write(file, val);
968 if (ret)
969 goto err_input;
970 break;
971 case CLEAR_ENABLE:
972 ret = clear_enable_write(file, val);
973 if (ret)
974 goto err_input;
975 break;
976 default:
977 ret = -EINVAL;
978 goto err_input;
979 }
980 mutex_unlock(&file->lock);
981
982 return count;
983
984 err_input:
985 mutex_unlock(&file->lock);
986 return ret;
987 }
988
989 static const struct file_operations qm_debug_fops = {
990 .owner = THIS_MODULE,
991 .open = simple_open,
992 .read = qm_debug_read,
993 .write = qm_debug_write,
994 };
995
996 struct qm_dfx_registers {
997 char *reg_name;
998 u64 reg_offset;
999 };
1000
1001 #define CNT_CYC_REGS_NUM 10
1002 static struct qm_dfx_registers qm_dfx_regs[] = {
1003 /* XXX_CNT are reading clear register */
1004 {"QM_ECC_1BIT_CNT ", 0x104000ull},
1005 {"QM_ECC_MBIT_CNT ", 0x104008ull},
1006 {"QM_DFX_MB_CNT ", 0x104018ull},
1007 {"QM_DFX_DB_CNT ", 0x104028ull},
1008 {"QM_DFX_SQE_CNT ", 0x104038ull},
1009 {"QM_DFX_CQE_CNT ", 0x104048ull},
1010 {"QM_DFX_SEND_SQE_TO_ACC_CNT ", 0x104050ull},
1011 {"QM_DFX_WB_SQE_FROM_ACC_CNT ", 0x104058ull},
1012 {"QM_DFX_ACC_FINISH_CNT ", 0x104060ull},
1013 {"QM_DFX_CQE_ERR_CNT ", 0x1040b4ull},
1014 {"QM_DFX_FUNS_ACTIVE_ST ", 0x200ull},
1015 {"QM_ECC_1BIT_INF ", 0x104004ull},
1016 {"QM_ECC_MBIT_INF ", 0x10400cull},
1017 {"QM_DFX_ACC_RDY_VLD0 ", 0x1040a0ull},
1018 {"QM_DFX_ACC_RDY_VLD1 ", 0x1040a4ull},
1019 {"QM_DFX_AXI_RDY_VLD ", 0x1040a8ull},
1020 {"QM_DFX_FF_ST0 ", 0x1040c8ull},
1021 {"QM_DFX_FF_ST1 ", 0x1040ccull},
1022 {"QM_DFX_FF_ST2 ", 0x1040d0ull},
1023 {"QM_DFX_FF_ST3 ", 0x1040d4ull},
1024 {"QM_DFX_FF_ST4 ", 0x1040d8ull},
1025 {"QM_DFX_FF_ST5 ", 0x1040dcull},
1026 {"QM_DFX_FF_ST6 ", 0x1040e0ull},
1027 {"QM_IN_IDLE_ST ", 0x1040e4ull},
1028 { NULL, 0}
1029 };
1030
1031 static struct qm_dfx_registers qm_vf_dfx_regs[] = {
1032 {"QM_DFX_FUNS_ACTIVE_ST ", 0x200ull},
1033 { NULL, 0}
1034 };
1035
1036 static int qm_regs_show(struct seq_file *s, void *unused)
1037 {
1038 struct hisi_qm *qm = s->private;
1039 struct qm_dfx_registers *regs;
1040 u32 val;
1041
1042 if (qm->fun_type == QM_HW_PF)
1043 regs = qm_dfx_regs;
1044 else
1045 regs = qm_vf_dfx_regs;
1046
1047 while (regs->reg_name) {
1048 val = readl(qm->io_base + regs->reg_offset);
1049 seq_printf(s, "%s= 0x%08x\n", regs->reg_name, val);
1050 regs++;
1051 }
1052
1053 return 0;
1054 }
1055
1056 DEFINE_SHOW_ATTRIBUTE(qm_regs);
1057
1058 static ssize_t qm_cmd_read(struct file *filp, char __user *buffer,
1059 size_t count, loff_t *pos)
1060 {
1061 char buf[QM_DBG_READ_LEN];
1062 int len;
1063
1064 len = scnprintf(buf, QM_DBG_READ_LEN, "%s\n",
1065 "Please echo help to cmd to get help information");
1066
1067 return simple_read_from_buffer(buffer, count, pos, buf, len);
1068 }
1069
1070 static void *qm_ctx_alloc(struct hisi_qm *qm, size_t ctx_size,
1071 dma_addr_t *dma_addr)
1072 {
1073 struct device *dev = &qm->pdev->dev;
1074 void *ctx_addr;
1075
1076 ctx_addr = kzalloc(ctx_size, GFP_KERNEL);
1077 if (!ctx_addr)
1078 return ERR_PTR(-ENOMEM);
1079
1080 *dma_addr = dma_map_single(dev, ctx_addr, ctx_size, DMA_FROM_DEVICE);
1081 if (dma_mapping_error(dev, *dma_addr)) {
1082 dev_err(dev, "DMA mapping error!\n");
1083 kfree(ctx_addr);
1084 return ERR_PTR(-ENOMEM);
1085 }
1086
1087 return ctx_addr;
1088 }
1089
1090 static void qm_ctx_free(struct hisi_qm *qm, size_t ctx_size,
1091 const void *ctx_addr, dma_addr_t *dma_addr)
1092 {
1093 struct device *dev = &qm->pdev->dev;
1094
1095 dma_unmap_single(dev, *dma_addr, ctx_size, DMA_FROM_DEVICE);
1096 kfree(ctx_addr);
1097 }
1098
1099 static int dump_show(struct hisi_qm *qm, void *info,
1100 unsigned int info_size, char *info_name)
1101 {
1102 struct device *dev = &qm->pdev->dev;
1103 u8 *info_buf, *info_curr = info;
1104 u32 i;
1105 #define BYTE_PER_DW 4
1106
1107 info_buf = kzalloc(info_size, GFP_KERNEL);
1108 if (!info_buf)
1109 return -ENOMEM;
1110
1111 for (i = 0; i < info_size; i++, info_curr++) {
1112 if (i % BYTE_PER_DW == 0)
1113 info_buf[i + 3UL] = *info_curr;
1114 else if (i % BYTE_PER_DW == 1)
1115 info_buf[i + 1UL] = *info_curr;
1116 else if (i % BYTE_PER_DW == 2)
1117 info_buf[i - 1] = *info_curr;
1118 else if (i % BYTE_PER_DW == 3)
1119 info_buf[i - 3] = *info_curr;
1120 }
1121
1122 dev_info(dev, "%s DUMP\n", info_name);
1123 for (i = 0; i < info_size; i += BYTE_PER_DW) {
1124 pr_info("DW%d: %02X%02X %02X%02X\n", i / BYTE_PER_DW,
1125 info_buf[i], info_buf[i + 1UL],
1126 info_buf[i + 2UL], info_buf[i + 3UL]);
1127 }
1128
1129 kfree(info_buf);
1130
1131 return 0;
1132 }
1133
1134 static int qm_dump_sqc_raw(struct hisi_qm *qm, dma_addr_t dma_addr, u16 qp_id)
1135 {
1136 return qm_mb(qm, QM_MB_CMD_SQC, dma_addr, qp_id, 1);
1137 }
1138
1139 static int qm_dump_cqc_raw(struct hisi_qm *qm, dma_addr_t dma_addr, u16 qp_id)
1140 {
1141 return qm_mb(qm, QM_MB_CMD_CQC, dma_addr, qp_id, 1);
1142 }
1143
1144 static int qm_sqc_dump(struct hisi_qm *qm, const char *s)
1145 {
1146 struct device *dev = &qm->pdev->dev;
1147 struct qm_sqc *sqc, *sqc_curr;
1148 dma_addr_t sqc_dma;
1149 u32 qp_id;
1150 int ret;
1151
1152 if (!s)
1153 return -EINVAL;
1154
1155 ret = kstrtou32(s, 0, &qp_id);
1156 if (ret || qp_id >= qm->qp_num) {
1157 dev_err(dev, "Please input qp num (0-%d)", qm->qp_num - 1);
1158 return -EINVAL;
1159 }
1160
1161 sqc = qm_ctx_alloc(qm, sizeof(*sqc), &sqc_dma);
1162 if (IS_ERR(sqc))
1163 return PTR_ERR(sqc);
1164
1165 ret = qm_dump_sqc_raw(qm, sqc_dma, qp_id);
1166 if (ret) {
1167 down_read(&qm->qps_lock);
1168 if (qm->sqc) {
1169 sqc_curr = qm->sqc + qp_id;
1170
1171 ret = dump_show(qm, sqc_curr, sizeof(*sqc),
1172 "SOFT SQC");
1173 if (ret)
1174 dev_info(dev, "Show soft sqc failed!\n");
1175 }
1176 up_read(&qm->qps_lock);
1177
1178 goto err_free_ctx;
1179 }
1180
1181 ret = dump_show(qm, sqc, sizeof(*sqc), "SQC");
1182 if (ret)
1183 dev_info(dev, "Show hw sqc failed!\n");
1184
1185 err_free_ctx:
1186 qm_ctx_free(qm, sizeof(*sqc), sqc, &sqc_dma);
1187 return ret;
1188 }
1189
1190 static int qm_cqc_dump(struct hisi_qm *qm, const char *s)
1191 {
1192 struct device *dev = &qm->pdev->dev;
1193 struct qm_cqc *cqc, *cqc_curr;
1194 dma_addr_t cqc_dma;
1195 u32 qp_id;
1196 int ret;
1197
1198 if (!s)
1199 return -EINVAL;
1200
1201 ret = kstrtou32(s, 0, &qp_id);
1202 if (ret || qp_id >= qm->qp_num) {
1203 dev_err(dev, "Please input qp num (0-%d)", qm->qp_num - 1);
1204 return -EINVAL;
1205 }
1206
1207 cqc = qm_ctx_alloc(qm, sizeof(*cqc), &cqc_dma);
1208 if (IS_ERR(cqc))
1209 return PTR_ERR(cqc);
1210
1211 ret = qm_dump_cqc_raw(qm, cqc_dma, qp_id);
1212 if (ret) {
1213 down_read(&qm->qps_lock);
1214 if (qm->cqc) {
1215 cqc_curr = qm->cqc + qp_id;
1216
1217 ret = dump_show(qm, cqc_curr, sizeof(*cqc),
1218 "SOFT CQC");
1219 if (ret)
1220 dev_info(dev, "Show soft cqc failed!\n");
1221 }
1222 up_read(&qm->qps_lock);
1223
1224 goto err_free_ctx;
1225 }
1226
1227 ret = dump_show(qm, cqc, sizeof(*cqc), "CQC");
1228 if (ret)
1229 dev_info(dev, "Show hw cqc failed!\n");
1230
1231 err_free_ctx:
1232 qm_ctx_free(qm, sizeof(*cqc), cqc, &cqc_dma);
1233 return ret;
1234 }
1235
1236 static int qm_eqc_aeqc_dump(struct hisi_qm *qm, char *s, size_t size,
1237 int cmd, char *name)
1238 {
1239 struct device *dev = &qm->pdev->dev;
1240 dma_addr_t xeqc_dma;
1241 void *xeqc;
1242 int ret;
1243
1244 if (strsep(&s, " ")) {
1245 dev_err(dev, "Please do not input extra characters!\n");
1246 return -EINVAL;
1247 }
1248
1249 xeqc = qm_ctx_alloc(qm, size, &xeqc_dma);
1250 if (IS_ERR(xeqc))
1251 return PTR_ERR(xeqc);
1252
1253 ret = qm_mb(qm, cmd, xeqc_dma, 0, 1);
1254 if (ret)
1255 goto err_free_ctx;
1256
1257 ret = dump_show(qm, xeqc, size, name);
1258 if (ret)
1259 dev_info(dev, "Show hw %s failed!\n", name);
1260
1261 err_free_ctx:
1262 qm_ctx_free(qm, size, xeqc, &xeqc_dma);
1263 return ret;
1264 }
1265
1266 static int q_dump_param_parse(struct hisi_qm *qm, char *s,
1267 u32 *e_id, u32 *q_id)
1268 {
1269 struct device *dev = &qm->pdev->dev;
1270 unsigned int qp_num = qm->qp_num;
1271 char *presult;
1272 int ret;
1273
1274 presult = strsep(&s, " ");
1275 if (!presult) {
1276 dev_err(dev, "Please input qp number!\n");
1277 return -EINVAL;
1278 }
1279
1280 ret = kstrtou32(presult, 0, q_id);
1281 if (ret || *q_id >= qp_num) {
1282 dev_err(dev, "Please input qp num (0-%d)", qp_num - 1);
1283 return -EINVAL;
1284 }
1285
1286 presult = strsep(&s, " ");
1287 if (!presult) {
1288 dev_err(dev, "Please input sqe number!\n");
1289 return -EINVAL;
1290 }
1291
1292 ret = kstrtou32(presult, 0, e_id);
1293 if (ret || *e_id >= QM_Q_DEPTH) {
1294 dev_err(dev, "Please input sqe num (0-%d)", QM_Q_DEPTH - 1);
1295 return -EINVAL;
1296 }
1297
1298 if (strsep(&s, " ")) {
1299 dev_err(dev, "Please do not input extra characters!\n");
1300 return -EINVAL;
1301 }
1302
1303 return 0;
1304 }
1305
1306 static int qm_sq_dump(struct hisi_qm *qm, char *s)
1307 {
1308 struct device *dev = &qm->pdev->dev;
1309 void *sqe, *sqe_curr;
1310 struct hisi_qp *qp;
1311 u32 qp_id, sqe_id;
1312 int ret;
1313
1314 ret = q_dump_param_parse(qm, s, &sqe_id, &qp_id);
1315 if (ret)
1316 return ret;
1317
1318 sqe = kzalloc(qm->sqe_size * QM_Q_DEPTH, GFP_KERNEL);
1319 if (!sqe)
1320 return -ENOMEM;
1321
1322 qp = &qm->qp_array[qp_id];
1323 memcpy(sqe, qp->sqe, qm->sqe_size * QM_Q_DEPTH);
1324 sqe_curr = sqe + (u32)(sqe_id * qm->sqe_size);
1325 memset(sqe_curr + qm->debug.sqe_mask_offset, QM_SQE_ADDR_MASK,
1326 qm->debug.sqe_mask_len);
1327
1328 ret = dump_show(qm, sqe_curr, qm->sqe_size, "SQE");
1329 if (ret)
1330 dev_info(dev, "Show sqe failed!\n");
1331
1332 kfree(sqe);
1333
1334 return ret;
1335 }
1336
1337 static int qm_cq_dump(struct hisi_qm *qm, char *s)
1338 {
1339 struct device *dev = &qm->pdev->dev;
1340 struct qm_cqe *cqe_curr;
1341 struct hisi_qp *qp;
1342 u32 qp_id, cqe_id;
1343 int ret;
1344
1345 ret = q_dump_param_parse(qm, s, &cqe_id, &qp_id);
1346 if (ret)
1347 return ret;
1348
1349 qp = &qm->qp_array[qp_id];
1350 cqe_curr = qp->cqe + cqe_id;
1351 ret = dump_show(qm, cqe_curr, sizeof(struct qm_cqe), "CQE");
1352 if (ret)
1353 dev_info(dev, "Show cqe failed!\n");
1354
1355 return ret;
1356 }
1357
1358 static int qm_eq_aeq_dump(struct hisi_qm *qm, const char *s,
1359 size_t size, char *name)
1360 {
1361 struct device *dev = &qm->pdev->dev;
1362 void *xeqe;
1363 u32 xeqe_id;
1364 int ret;
1365
1366 if (!s)
1367 return -EINVAL;
1368
1369 ret = kstrtou32(s, 0, &xeqe_id);
1370 if (ret)
1371 return -EINVAL;
1372
1373 if (!strcmp(name, "EQE") && xeqe_id >= QM_EQ_DEPTH) {
1374 dev_err(dev, "Please input eqe num (0-%d)", QM_EQ_DEPTH - 1);
1375 return -EINVAL;
1376 } else if (!strcmp(name, "AEQE") && xeqe_id >= QM_Q_DEPTH) {
1377 dev_err(dev, "Please input aeqe num (0-%d)", QM_Q_DEPTH - 1);
1378 return -EINVAL;
1379 }
1380
1381 down_read(&qm->qps_lock);
1382
1383 if (qm->eqe && !strcmp(name, "EQE")) {
1384 xeqe = qm->eqe + xeqe_id;
1385 } else if (qm->aeqe && !strcmp(name, "AEQE")) {
1386 xeqe = qm->aeqe + xeqe_id;
1387 } else {
1388 ret = -EINVAL;
1389 goto err_unlock;
1390 }
1391
1392 ret = dump_show(qm, xeqe, size, name);
1393 if (ret)
1394 dev_info(dev, "Show %s failed!\n", name);
1395
1396 err_unlock:
1397 up_read(&qm->qps_lock);
1398 return ret;
1399 }
1400
1401 static int qm_dbg_help(struct hisi_qm *qm, char *s)
1402 {
1403 struct device *dev = &qm->pdev->dev;
1404
1405 if (strsep(&s, " ")) {
1406 dev_err(dev, "Please do not input extra characters!\n");
1407 return -EINVAL;
1408 }
1409
1410 dev_info(dev, "available commands:\n");
1411 dev_info(dev, "sqc <num>\n");
1412 dev_info(dev, "cqc <num>\n");
1413 dev_info(dev, "eqc\n");
1414 dev_info(dev, "aeqc\n");
1415 dev_info(dev, "sq <num> <e>\n");
1416 dev_info(dev, "cq <num> <e>\n");
1417 dev_info(dev, "eq <e>\n");
1418 dev_info(dev, "aeq <e>\n");
1419
1420 return 0;
1421 }
1422
1423 static int qm_cmd_write_dump(struct hisi_qm *qm, const char *cmd_buf)
1424 {
1425 struct device *dev = &qm->pdev->dev;
1426 char *presult, *s, *s_tmp;
1427 int ret;
1428
1429 s = kstrdup(cmd_buf, GFP_KERNEL);
1430 if (!s)
1431 return -ENOMEM;
1432
1433 s_tmp = s;
1434 presult = strsep(&s, " ");
1435 if (!presult) {
1436 ret = -EINVAL;
1437 goto err_buffer_free;
1438 }
1439
1440 if (!strcmp(presult, "sqc"))
1441 ret = qm_sqc_dump(qm, s);
1442 else if (!strcmp(presult, "cqc"))
1443 ret = qm_cqc_dump(qm, s);
1444 else if (!strcmp(presult, "eqc"))
1445 ret = qm_eqc_aeqc_dump(qm, s, sizeof(struct qm_eqc),
1446 QM_MB_CMD_EQC, "EQC");
1447 else if (!strcmp(presult, "aeqc"))
1448 ret = qm_eqc_aeqc_dump(qm, s, sizeof(struct qm_aeqc),
1449 QM_MB_CMD_AEQC, "AEQC");
1450 else if (!strcmp(presult, "sq"))
1451 ret = qm_sq_dump(qm, s);
1452 else if (!strcmp(presult, "cq"))
1453 ret = qm_cq_dump(qm, s);
1454 else if (!strcmp(presult, "eq"))
1455 ret = qm_eq_aeq_dump(qm, s, sizeof(struct qm_eqe), "EQE");
1456 else if (!strcmp(presult, "aeq"))
1457 ret = qm_eq_aeq_dump(qm, s, sizeof(struct qm_aeqe), "AEQE");
1458 else if (!strcmp(presult, "help"))
1459 ret = qm_dbg_help(qm, s);
1460 else
1461 ret = -EINVAL;
1462
1463 if (ret)
1464 dev_info(dev, "Please echo help\n");
1465
1466 err_buffer_free:
1467 kfree(s_tmp);
1468
1469 return ret;
1470 }
1471
1472 static ssize_t qm_cmd_write(struct file *filp, const char __user *buffer,
1473 size_t count, loff_t *pos)
1474 {
1475 struct hisi_qm *qm = filp->private_data;
1476 char *cmd_buf, *cmd_buf_tmp;
1477 int ret;
1478
1479 if (*pos)
1480 return 0;
1481
1482 /* Judge if the instance is being reset. */
1483 if (unlikely(atomic_read(&qm->status.flags) == QM_STOP))
1484 return 0;
1485
1486 if (count > QM_DBG_WRITE_LEN)
1487 return -ENOSPC;
1488
1489 cmd_buf = kzalloc(count + 1, GFP_KERNEL);
1490 if (!cmd_buf)
1491 return -ENOMEM;
1492
1493 if (copy_from_user(cmd_buf, buffer, count)) {
1494 kfree(cmd_buf);
1495 return -EFAULT;
1496 }
1497
1498 cmd_buf[count] = '\0';
1499
1500 cmd_buf_tmp = strchr(cmd_buf, '\n');
1501 if (cmd_buf_tmp) {
1502 *cmd_buf_tmp = '\0';
1503 count = cmd_buf_tmp - cmd_buf + 1;
1504 }
1505
1506 ret = qm_cmd_write_dump(qm, cmd_buf);
1507 if (ret) {
1508 kfree(cmd_buf);
1509 return ret;
1510 }
1511
1512 kfree(cmd_buf);
1513
1514 return count;
1515 }
1516
1517 static const struct file_operations qm_cmd_fops = {
1518 .owner = THIS_MODULE,
1519 .open = simple_open,
1520 .read = qm_cmd_read,
1521 .write = qm_cmd_write,
1522 };
1523
1524 static void qm_create_debugfs_file(struct hisi_qm *qm, enum qm_debug_file index)
1525 {
1526 struct dentry *qm_d = qm->debug.qm_d;
1527 struct debugfs_file *file = qm->debug.files + index;
1528
1529 debugfs_create_file(qm_debug_file_name[index], 0600, qm_d, file,
1530 &qm_debug_fops);
1531
1532 file->index = index;
1533 mutex_init(&file->lock);
1534 file->debug = &qm->debug;
1535 }
1536
1537 static void qm_hw_error_init_v1(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe)
1538 {
1539 writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
1540 }
1541
1542 static void qm_hw_error_init_v2(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe)
1543 {
1544 u32 irq_enable = ce | nfe | fe;
1545 u32 irq_unmask = ~irq_enable;
1546
1547 qm->error_mask = ce | nfe | fe;
1548
1549 /* clear QM hw residual error source */
1550 writel(QM_ABNORMAL_INT_SOURCE_CLR,
1551 qm->io_base + QM_ABNORMAL_INT_SOURCE);
1552
1553 /* configure error type */
1554 writel(ce, qm->io_base + QM_RAS_CE_ENABLE);
1555 writel(QM_RAS_CE_TIMES_PER_IRQ, qm->io_base + QM_RAS_CE_THRESHOLD);
1556 writel(nfe, qm->io_base + QM_RAS_NFE_ENABLE);
1557 writel(fe, qm->io_base + QM_RAS_FE_ENABLE);
1558
1559 irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
1560 writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
1561 }
1562
1563 static void qm_hw_error_uninit_v2(struct hisi_qm *qm)
1564 {
1565 writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
1566 }
1567
1568 static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status)
1569 {
1570 const struct hisi_qm_hw_error *err;
1571 struct device *dev = &qm->pdev->dev;
1572 u32 reg_val, type, vf_num;
1573 int i;
1574
1575 for (i = 0; i < ARRAY_SIZE(qm_hw_error); i++) {
1576 err = &qm_hw_error[i];
1577 if (!(err->int_msk & error_status))
1578 continue;
1579
1580 dev_err(dev, "%s [error status=0x%x] found\n",
1581 err->msg, err->int_msk);
1582
1583 if (err->int_msk & QM_DB_TIMEOUT) {
1584 reg_val = readl(qm->io_base + QM_ABNORMAL_INF01);
1585 type = (reg_val & QM_DB_TIMEOUT_TYPE) >>
1586 QM_DB_TIMEOUT_TYPE_SHIFT;
1587 vf_num = reg_val & QM_DB_TIMEOUT_VF;
1588 dev_err(dev, "qm %s doorbell timeout in function %u\n",
1589 qm_db_timeout[type], vf_num);
1590 } else if (err->int_msk & QM_OF_FIFO_OF) {
1591 reg_val = readl(qm->io_base + QM_ABNORMAL_INF00);
1592 type = (reg_val & QM_FIFO_OVERFLOW_TYPE) >>
1593 QM_FIFO_OVERFLOW_TYPE_SHIFT;
1594 vf_num = reg_val & QM_FIFO_OVERFLOW_VF;
1595
1596 if (type < ARRAY_SIZE(qm_fifo_overflow))
1597 dev_err(dev, "qm %s fifo overflow in function %u\n",
1598 qm_fifo_overflow[type], vf_num);
1599 else
1600 dev_err(dev, "unknown error type\n");
1601 }
1602 }
1603 }
1604
1605 static enum acc_err_result qm_hw_error_handle_v2(struct hisi_qm *qm)
1606 {
1607 u32 error_status, tmp;
1608
1609 /* read err sts */
1610 tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
1611 error_status = qm->error_mask & tmp;
1612
1613 if (error_status) {
1614 if (error_status & QM_ECC_MBIT)
1615 qm->err_status.is_qm_ecc_mbit = true;
1616
1617 qm_log_hw_error(qm, error_status);
1618 if (error_status == QM_DB_RANDOM_INVALID) {
1619 writel(error_status, qm->io_base +
1620 QM_ABNORMAL_INT_SOURCE);
1621 return ACC_ERR_RECOVERED;
1622 }
1623
1624 return ACC_ERR_NEED_RESET;
1625 }
1626
1627 return ACC_ERR_RECOVERED;
1628 }
1629
1630 static const struct hisi_qm_hw_ops qm_hw_ops_v1 = {
1631 .qm_db = qm_db_v1,
1632 .get_irq_num = qm_get_irq_num_v1,
1633 .hw_error_init = qm_hw_error_init_v1,
1634 };
1635
1636 static const struct hisi_qm_hw_ops qm_hw_ops_v2 = {
1637 .get_vft = qm_get_vft_v2,
1638 .qm_db = qm_db_v2,
1639 .get_irq_num = qm_get_irq_num_v2,
1640 .hw_error_init = qm_hw_error_init_v2,
1641 .hw_error_uninit = qm_hw_error_uninit_v2,
1642 .hw_error_handle = qm_hw_error_handle_v2,
1643 };
1644
1645 static void *qm_get_avail_sqe(struct hisi_qp *qp)
1646 {
1647 struct hisi_qp_status *qp_status = &qp->qp_status;
1648 u16 sq_tail = qp_status->sq_tail;
1649
1650 if (unlikely(atomic_read(&qp->qp_status.used) == QM_Q_DEPTH - 1))
1651 return NULL;
1652
1653 return qp->sqe + sq_tail * qp->qm->sqe_size;
1654 }
1655
1656 static struct hisi_qp *qm_create_qp_nolock(struct hisi_qm *qm, u8 alg_type)
1657 {
1658 struct device *dev = &qm->pdev->dev;
1659 struct hisi_qp *qp;
1660 int qp_id;
1661
1662 if (!qm_qp_avail_state(qm, NULL, QP_INIT))
1663 return ERR_PTR(-EPERM);
1664
1665 if (qm->qp_in_used == qm->qp_num) {
1666 dev_info_ratelimited(dev, "All %u queues of QM are busy!\n",
1667 qm->qp_num);
1668 atomic64_inc(&qm->debug.dfx.create_qp_err_cnt);
1669 return ERR_PTR(-EBUSY);
1670 }
1671
1672 qp_id = idr_alloc_cyclic(&qm->qp_idr, NULL, 0, qm->qp_num, GFP_ATOMIC);
1673 if (qp_id < 0) {
1674 dev_info_ratelimited(dev, "All %u queues of QM are busy!\n",
1675 qm->qp_num);
1676 atomic64_inc(&qm->debug.dfx.create_qp_err_cnt);
1677 return ERR_PTR(-EBUSY);
1678 }
1679
1680 qp = &qm->qp_array[qp_id];
1681
1682 memset(qp->cqe, 0, sizeof(struct qm_cqe) * QM_Q_DEPTH);
1683
1684 qp->event_cb = NULL;
1685 qp->req_cb = NULL;
1686 qp->qp_id = qp_id;
1687 qp->alg_type = alg_type;
1688 qm->qp_in_used++;
1689 atomic_set(&qp->qp_status.flags, QP_INIT);
1690
1691 return qp;
1692 }
1693
1694 /**
1695 * hisi_qm_create_qp() - Create a queue pair from qm.
1696 * @qm: The qm we create a qp from.
1697 * @alg_type: Accelerator specific algorithm type in sqc.
1698 *
1699 * return created qp, -EBUSY if all qps in qm allocated, -ENOMEM if allocating
1700 * qp memory fails.
1701 */
1702 struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type)
1703 {
1704 struct hisi_qp *qp;
1705
1706 down_write(&qm->qps_lock);
1707 qp = qm_create_qp_nolock(qm, alg_type);
1708 up_write(&qm->qps_lock);
1709
1710 return qp;
1711 }
1712 EXPORT_SYMBOL_GPL(hisi_qm_create_qp);
1713
1714 /**
1715 * hisi_qm_release_qp() - Release a qp back to its qm.
1716 * @qp: The qp we want to release.
1717 *
1718 * This function releases the resource of a qp.
1719 */
1720 void hisi_qm_release_qp(struct hisi_qp *qp)
1721 {
1722 struct hisi_qm *qm = qp->qm;
1723
1724 down_write(&qm->qps_lock);
1725
1726 if (!qm_qp_avail_state(qm, qp, QP_CLOSE)) {
1727 up_write(&qm->qps_lock);
1728 return;
1729 }
1730
1731 qm->qp_in_used--;
1732 idr_remove(&qm->qp_idr, qp->qp_id);
1733
1734 up_write(&qm->qps_lock);
1735 }
1736 EXPORT_SYMBOL_GPL(hisi_qm_release_qp);
1737
1738 static int qm_sq_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
1739 {
1740 struct hisi_qm *qm = qp->qm;
1741 struct device *dev = &qm->pdev->dev;
1742 enum qm_hw_ver ver = qm->ver;
1743 struct qm_sqc *sqc;
1744 dma_addr_t sqc_dma;
1745 int ret;
1746
1747 sqc = kzalloc(sizeof(struct qm_sqc), GFP_KERNEL);
1748 if (!sqc)
1749 return -ENOMEM;
1750 sqc_dma = dma_map_single(dev, sqc, sizeof(struct qm_sqc),
1751 DMA_TO_DEVICE);
1752 if (dma_mapping_error(dev, sqc_dma)) {
1753 kfree(sqc);
1754 return -ENOMEM;
1755 }
1756
1757 INIT_QC_COMMON(sqc, qp->sqe_dma, pasid);
1758 if (ver == QM_HW_V1) {
1759 sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V1(0, 0, 0, qm->sqe_size));
1760 sqc->w8 = cpu_to_le16(QM_Q_DEPTH - 1);
1761 } else {
1762 sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V2(qm->sqe_size));
1763 sqc->w8 = 0; /* rand_qc */
1764 }
1765 sqc->cq_num = cpu_to_le16(qp_id);
1766 sqc->w13 = cpu_to_le16(QM_MK_SQC_W13(0, 1, qp->alg_type));
1767
1768 ret = qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 0);
1769 dma_unmap_single(dev, sqc_dma, sizeof(struct qm_sqc), DMA_TO_DEVICE);
1770 kfree(sqc);
1771
1772 return ret;
1773 }
1774
1775 static int qm_cq_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
1776 {
1777 struct hisi_qm *qm = qp->qm;
1778 struct device *dev = &qm->pdev->dev;
1779 enum qm_hw_ver ver = qm->ver;
1780 struct qm_cqc *cqc;
1781 dma_addr_t cqc_dma;
1782 int ret;
1783
1784 cqc = kzalloc(sizeof(struct qm_cqc), GFP_KERNEL);
1785 if (!cqc)
1786 return -ENOMEM;
1787 cqc_dma = dma_map_single(dev, cqc, sizeof(struct qm_cqc),
1788 DMA_TO_DEVICE);
1789 if (dma_mapping_error(dev, cqc_dma)) {
1790 kfree(cqc);
1791 return -ENOMEM;
1792 }
1793
1794 INIT_QC_COMMON(cqc, qp->cqe_dma, pasid);
1795 if (ver == QM_HW_V1) {
1796 cqc->dw3 = cpu_to_le32(QM_MK_CQC_DW3_V1(0, 0, 0,
1797 QM_QC_CQE_SIZE));
1798 cqc->w8 = cpu_to_le16(QM_Q_DEPTH - 1);
1799 } else {
1800 cqc->dw3 = cpu_to_le32(QM_MK_CQC_DW3_V2(QM_QC_CQE_SIZE));
1801 cqc->w8 = 0; /* rand_qc */
1802 }
1803 cqc->dw6 = cpu_to_le32(1 << QM_CQ_PHASE_SHIFT | 1 << QM_CQ_FLAG_SHIFT);
1804
1805 ret = qm_mb(qm, QM_MB_CMD_CQC, cqc_dma, qp_id, 0);
1806 dma_unmap_single(dev, cqc_dma, sizeof(struct qm_cqc), DMA_TO_DEVICE);
1807 kfree(cqc);
1808
1809 return ret;
1810 }
1811
1812 static int qm_qp_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
1813 {
1814 int ret;
1815
1816 qm_init_qp_status(qp);
1817
1818 ret = qm_sq_ctx_cfg(qp, qp_id, pasid);
1819 if (ret)
1820 return ret;
1821
1822 return qm_cq_ctx_cfg(qp, qp_id, pasid);
1823 }
1824
1825 static int qm_start_qp_nolock(struct hisi_qp *qp, unsigned long arg)
1826 {
1827 struct hisi_qm *qm = qp->qm;
1828 struct device *dev = &qm->pdev->dev;
1829 int qp_id = qp->qp_id;
1830 u32 pasid = arg;
1831 int ret;
1832
1833 if (!qm_qp_avail_state(qm, qp, QP_START))
1834 return -EPERM;
1835
1836 ret = qm_qp_ctx_cfg(qp, qp_id, pasid);
1837 if (ret)
1838 return ret;
1839
1840 atomic_set(&qp->qp_status.flags, QP_START);
1841 dev_dbg(dev, "queue %d started\n", qp_id);
1842
1843 return 0;
1844 }
1845
1846 /**
1847 * hisi_qm_start_qp() - Start a qp into running.
1848 * @qp: The qp we want to start to run.
1849 * @arg: Accelerator specific argument.
1850 *
1851 * After this function, qp can receive request from user. Return 0 if
1852 * successful, Return -EBUSY if failed.
1853 */
1854 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg)
1855 {
1856 struct hisi_qm *qm = qp->qm;
1857 int ret;
1858
1859 down_write(&qm->qps_lock);
1860 ret = qm_start_qp_nolock(qp, arg);
1861 up_write(&qm->qps_lock);
1862
1863 return ret;
1864 }
1865 EXPORT_SYMBOL_GPL(hisi_qm_start_qp);
1866
1867 /**
1868 * qm_drain_qp() - Drain a qp.
1869 * @qp: The qp we want to drain.
1870 *
1871 * Determine whether the queue is cleared by judging the tail pointers of
1872 * sq and cq.
1873 */
1874 static int qm_drain_qp(struct hisi_qp *qp)
1875 {
1876 size_t size = sizeof(struct qm_sqc) + sizeof(struct qm_cqc);
1877 struct hisi_qm *qm = qp->qm;
1878 struct device *dev = &qm->pdev->dev;
1879 struct qm_sqc *sqc;
1880 struct qm_cqc *cqc;
1881 dma_addr_t dma_addr;
1882 int ret = 0, i = 0;
1883 void *addr;
1884
1885 /*
1886 * No need to judge if ECC multi-bit error occurs because the
1887 * master OOO will be blocked.
1888 */
1889 if (qm->err_status.is_qm_ecc_mbit || qm->err_status.is_dev_ecc_mbit)
1890 return 0;
1891
1892 addr = qm_ctx_alloc(qm, size, &dma_addr);
1893 if (IS_ERR(addr)) {
1894 dev_err(dev, "Failed to alloc ctx for sqc and cqc!\n");
1895 return -ENOMEM;
1896 }
1897
1898 while (++i) {
1899 ret = qm_dump_sqc_raw(qm, dma_addr, qp->qp_id);
1900 if (ret) {
1901 dev_err_ratelimited(dev, "Failed to dump sqc!\n");
1902 break;
1903 }
1904 sqc = addr;
1905
1906 ret = qm_dump_cqc_raw(qm, (dma_addr + sizeof(struct qm_sqc)),
1907 qp->qp_id);
1908 if (ret) {
1909 dev_err_ratelimited(dev, "Failed to dump cqc!\n");
1910 break;
1911 }
1912 cqc = addr + sizeof(struct qm_sqc);
1913
1914 if ((sqc->tail == cqc->tail) &&
1915 (QM_SQ_TAIL_IDX(sqc) == QM_CQ_TAIL_IDX(cqc)))
1916 break;
1917
1918 if (i == MAX_WAIT_COUNTS) {
1919 dev_err(dev, "Fail to empty queue %u!\n", qp->qp_id);
1920 ret = -EBUSY;
1921 break;
1922 }
1923
1924 usleep_range(WAIT_PERIOD_US_MIN, WAIT_PERIOD_US_MAX);
1925 }
1926
1927 qm_ctx_free(qm, size, addr, &dma_addr);
1928
1929 return ret;
1930 }
1931
1932 static int qm_stop_qp_nolock(struct hisi_qp *qp)
1933 {
1934 struct device *dev = &qp->qm->pdev->dev;
1935 int ret;
1936
1937 /*
1938 * It is allowed to stop and release qp when reset, If the qp is
1939 * stopped when reset but still want to be released then, the
1940 * is_resetting flag should be set negative so that this qp will not
1941 * be restarted after reset.
1942 */
1943 if (atomic_read(&qp->qp_status.flags) == QP_STOP) {
1944 qp->is_resetting = false;
1945 return 0;
1946 }
1947
1948 if (!qm_qp_avail_state(qp->qm, qp, QP_STOP))
1949 return -EPERM;
1950
1951 atomic_set(&qp->qp_status.flags, QP_STOP);
1952
1953 ret = qm_drain_qp(qp);
1954 if (ret)
1955 dev_err(dev, "Failed to drain out data for stopping!\n");
1956
1957 if (qp->qm->wq)
1958 flush_workqueue(qp->qm->wq);
1959 else
1960 flush_work(&qp->qm->work);
1961
1962 dev_dbg(dev, "stop queue %u!", qp->qp_id);
1963
1964 return 0;
1965 }
1966
1967 /**
1968 * hisi_qm_stop_qp() - Stop a qp in qm.
1969 * @qp: The qp we want to stop.
1970 *
1971 * This function is reverse of hisi_qm_start_qp. Return 0 if successful.
1972 */
1973 int hisi_qm_stop_qp(struct hisi_qp *qp)
1974 {
1975 int ret;
1976
1977 down_write(&qp->qm->qps_lock);
1978 ret = qm_stop_qp_nolock(qp);
1979 up_write(&qp->qm->qps_lock);
1980
1981 return ret;
1982 }
1983 EXPORT_SYMBOL_GPL(hisi_qm_stop_qp);
1984
1985 /**
1986 * hisi_qp_send() - Queue up a task in the hardware queue.
1987 * @qp: The qp in which to put the message.
1988 * @msg: The message.
1989 *
1990 * This function will return -EBUSY if qp is currently full, and -EAGAIN
1991 * if qp related qm is resetting.
1992 *
1993 * Note: This function may run with qm_irq_thread and ACC reset at same time.
1994 * It has no race with qm_irq_thread. However, during hisi_qp_send, ACC
1995 * reset may happen, we have no lock here considering performance. This
1996 * causes current qm_db sending fail or can not receive sended sqe. QM
1997 * sync/async receive function should handle the error sqe. ACC reset
1998 * done function should clear used sqe to 0.
1999 */
2000 int hisi_qp_send(struct hisi_qp *qp, const void *msg)
2001 {
2002 struct hisi_qp_status *qp_status = &qp->qp_status;
2003 u16 sq_tail = qp_status->sq_tail;
2004 u16 sq_tail_next = (sq_tail + 1) % QM_Q_DEPTH;
2005 void *sqe = qm_get_avail_sqe(qp);
2006
2007 if (unlikely(atomic_read(&qp->qp_status.flags) == QP_STOP ||
2008 atomic_read(&qp->qm->status.flags) == QM_STOP ||
2009 qp->is_resetting)) {
2010 dev_info_ratelimited(&qp->qm->pdev->dev, "QP is stopped or resetting\n");
2011 return -EAGAIN;
2012 }
2013
2014 if (!sqe)
2015 return -EBUSY;
2016
2017 memcpy(sqe, msg, qp->qm->sqe_size);
2018
2019 qm_db(qp->qm, qp->qp_id, QM_DOORBELL_CMD_SQ, sq_tail_next, 0);
2020 atomic_inc(&qp->qp_status.used);
2021 qp_status->sq_tail = sq_tail_next;
2022
2023 return 0;
2024 }
2025 EXPORT_SYMBOL_GPL(hisi_qp_send);
2026
2027 static void hisi_qm_cache_wb(struct hisi_qm *qm)
2028 {
2029 unsigned int val;
2030
2031 if (qm->ver == QM_HW_V1)
2032 return;
2033
2034 writel(0x1, qm->io_base + QM_CACHE_WB_START);
2035 if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,
2036 val, val & BIT(0), POLL_PERIOD,
2037 POLL_TIMEOUT))
2038 dev_err(&qm->pdev->dev, "QM writeback sqc cache fail!\n");
2039 }
2040
2041 static void qm_qp_event_notifier(struct hisi_qp *qp)
2042 {
2043 wake_up_interruptible(&qp->uacce_q->wait);
2044 }
2045
2046 static int hisi_qm_get_available_instances(struct uacce_device *uacce)
2047 {
2048 return hisi_qm_get_free_qp_num(uacce->priv);
2049 }
2050
2051 static int hisi_qm_uacce_get_queue(struct uacce_device *uacce,
2052 unsigned long arg,
2053 struct uacce_queue *q)
2054 {
2055 struct hisi_qm *qm = uacce->priv;
2056 struct hisi_qp *qp;
2057 u8 alg_type = 0;
2058
2059 qp = hisi_qm_create_qp(qm, alg_type);
2060 if (IS_ERR(qp))
2061 return PTR_ERR(qp);
2062
2063 q->priv = qp;
2064 q->uacce = uacce;
2065 qp->uacce_q = q;
2066 qp->event_cb = qm_qp_event_notifier;
2067 qp->pasid = arg;
2068
2069 return 0;
2070 }
2071
2072 static void hisi_qm_uacce_put_queue(struct uacce_queue *q)
2073 {
2074 struct hisi_qp *qp = q->priv;
2075
2076 hisi_qm_cache_wb(qp->qm);
2077 hisi_qm_release_qp(qp);
2078 }
2079
2080 /* map sq/cq/doorbell to user space */
2081 static int hisi_qm_uacce_mmap(struct uacce_queue *q,
2082 struct vm_area_struct *vma,
2083 struct uacce_qfile_region *qfr)
2084 {
2085 struct hisi_qp *qp = q->priv;
2086 struct hisi_qm *qm = qp->qm;
2087 size_t sz = vma->vm_end - vma->vm_start;
2088 struct pci_dev *pdev = qm->pdev;
2089 struct device *dev = &pdev->dev;
2090 unsigned long vm_pgoff;
2091 int ret;
2092
2093 switch (qfr->type) {
2094 case UACCE_QFRT_MMIO:
2095 if (qm->ver == QM_HW_V1) {
2096 if (sz > PAGE_SIZE * QM_DOORBELL_PAGE_NR)
2097 return -EINVAL;
2098 } else {
2099 if (sz > PAGE_SIZE * (QM_DOORBELL_PAGE_NR +
2100 QM_DOORBELL_SQ_CQ_BASE_V2 / PAGE_SIZE))
2101 return -EINVAL;
2102 }
2103
2104 vma->vm_flags |= VM_IO;
2105
2106 return remap_pfn_range(vma, vma->vm_start,
2107 qm->phys_base >> PAGE_SHIFT,
2108 sz, pgprot_noncached(vma->vm_page_prot));
2109 case UACCE_QFRT_DUS:
2110 if (sz != qp->qdma.size)
2111 return -EINVAL;
2112
2113 /*
2114 * dma_mmap_coherent() requires vm_pgoff as 0
2115 * restore vm_pfoff to initial value for mmap()
2116 */
2117 vm_pgoff = vma->vm_pgoff;
2118 vma->vm_pgoff = 0;
2119 ret = dma_mmap_coherent(dev, vma, qp->qdma.va,
2120 qp->qdma.dma, sz);
2121 vma->vm_pgoff = vm_pgoff;
2122 return ret;
2123
2124 default:
2125 return -EINVAL;
2126 }
2127 }
2128
2129 static int hisi_qm_uacce_start_queue(struct uacce_queue *q)
2130 {
2131 struct hisi_qp *qp = q->priv;
2132
2133 return hisi_qm_start_qp(qp, qp->pasid);
2134 }
2135
2136 static void hisi_qm_uacce_stop_queue(struct uacce_queue *q)
2137 {
2138 hisi_qm_stop_qp(q->priv);
2139 }
2140
2141 static void qm_set_sqctype(struct uacce_queue *q, u16 type)
2142 {
2143 struct hisi_qm *qm = q->uacce->priv;
2144 struct hisi_qp *qp = q->priv;
2145
2146 down_write(&qm->qps_lock);
2147 qp->alg_type = type;
2148 up_write(&qm->qps_lock);
2149 }
2150
2151 static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd,
2152 unsigned long arg)
2153 {
2154 struct hisi_qp *qp = q->priv;
2155 struct hisi_qp_ctx qp_ctx;
2156
2157 if (cmd == UACCE_CMD_QM_SET_QP_CTX) {
2158 if (copy_from_user(&qp_ctx, (void __user *)arg,
2159 sizeof(struct hisi_qp_ctx)))
2160 return -EFAULT;
2161
2162 if (qp_ctx.qc_type != 0 && qp_ctx.qc_type != 1)
2163 return -EINVAL;
2164
2165 qm_set_sqctype(q, qp_ctx.qc_type);
2166 qp_ctx.id = qp->qp_id;
2167
2168 if (copy_to_user((void __user *)arg, &qp_ctx,
2169 sizeof(struct hisi_qp_ctx)))
2170 return -EFAULT;
2171 } else {
2172 return -EINVAL;
2173 }
2174
2175 return 0;
2176 }
2177
2178 static const struct uacce_ops uacce_qm_ops = {
2179 .get_available_instances = hisi_qm_get_available_instances,
2180 .get_queue = hisi_qm_uacce_get_queue,
2181 .put_queue = hisi_qm_uacce_put_queue,
2182 .start_queue = hisi_qm_uacce_start_queue,
2183 .stop_queue = hisi_qm_uacce_stop_queue,
2184 .mmap = hisi_qm_uacce_mmap,
2185 .ioctl = hisi_qm_uacce_ioctl,
2186 };
2187
2188 static int qm_alloc_uacce(struct hisi_qm *qm)
2189 {
2190 struct pci_dev *pdev = qm->pdev;
2191 struct uacce_device *uacce;
2192 unsigned long mmio_page_nr;
2193 unsigned long dus_page_nr;
2194 struct uacce_interface interface = {
2195 .flags = UACCE_DEV_SVA,
2196 .ops = &uacce_qm_ops,
2197 };
2198 int ret;
2199
2200 ret = strscpy(interface.name, pdev->driver->name,
2201 sizeof(interface.name));
2202 if (ret < 0)
2203 return -ENAMETOOLONG;
2204
2205 uacce = uacce_alloc(&pdev->dev, &interface);
2206 if (IS_ERR(uacce))
2207 return PTR_ERR(uacce);
2208
2209 if (uacce->flags & UACCE_DEV_SVA) {
2210 qm->use_sva = true;
2211 } else {
2212 /* only consider sva case */
2213 uacce_remove(uacce);
2214 qm->uacce = NULL;
2215 return -EINVAL;
2216 }
2217
2218 uacce->is_vf = pdev->is_virtfn;
2219 uacce->priv = qm;
2220 uacce->algs = qm->algs;
2221
2222 if (qm->ver == QM_HW_V1) {
2223 mmio_page_nr = QM_DOORBELL_PAGE_NR;
2224 uacce->api_ver = HISI_QM_API_VER_BASE;
2225 } else {
2226 mmio_page_nr = QM_DOORBELL_PAGE_NR +
2227 QM_DOORBELL_SQ_CQ_BASE_V2 / PAGE_SIZE;
2228 uacce->api_ver = HISI_QM_API_VER2_BASE;
2229 }
2230
2231 dus_page_nr = (PAGE_SIZE - 1 + qm->sqe_size * QM_Q_DEPTH +
2232 sizeof(struct qm_cqe) * QM_Q_DEPTH) >> PAGE_SHIFT;
2233
2234 uacce->qf_pg_num[UACCE_QFRT_MMIO] = mmio_page_nr;
2235 uacce->qf_pg_num[UACCE_QFRT_DUS] = dus_page_nr;
2236
2237 qm->uacce = uacce;
2238
2239 return 0;
2240 }
2241
2242 /**
2243 * qm_frozen() - Try to froze QM to cut continuous queue request. If
2244 * there is user on the QM, return failure without doing anything.
2245 * @qm: The qm needed to be fronzen.
2246 *
2247 * This function frozes QM, then we can do SRIOV disabling.
2248 */
2249 static int qm_frozen(struct hisi_qm *qm)
2250 {
2251 down_write(&qm->qps_lock);
2252
2253 if (qm->is_frozen) {
2254 up_write(&qm->qps_lock);
2255 return 0;
2256 }
2257
2258 if (!qm->qp_in_used) {
2259 qm->qp_in_used = qm->qp_num;
2260 qm->is_frozen = true;
2261 up_write(&qm->qps_lock);
2262 return 0;
2263 }
2264
2265 up_write(&qm->qps_lock);
2266
2267 return -EBUSY;
2268 }
2269
2270 static int qm_try_frozen_vfs(struct pci_dev *pdev,
2271 struct hisi_qm_list *qm_list)
2272 {
2273 struct hisi_qm *qm, *vf_qm;
2274 struct pci_dev *dev;
2275 int ret = 0;
2276
2277 if (!qm_list || !pdev)
2278 return -EINVAL;
2279
2280 /* Try to frozen all the VFs as disable SRIOV */
2281 mutex_lock(&qm_list->lock);
2282 list_for_each_entry(qm, &qm_list->list, list) {
2283 dev = qm->pdev;
2284 if (dev == pdev)
2285 continue;
2286 if (pci_physfn(dev) == pdev) {
2287 vf_qm = pci_get_drvdata(dev);
2288 ret = qm_frozen(vf_qm);
2289 if (ret)
2290 goto frozen_fail;
2291 }
2292 }
2293
2294 frozen_fail:
2295 mutex_unlock(&qm_list->lock);
2296
2297 return ret;
2298 }
2299
2300 /**
2301 * hisi_qm_wait_task_finish() - Wait until the task is finished
2302 * when removing the driver.
2303 * @qm: The qm needed to wait for the task to finish.
2304 * @qm_list: The list of all available devices.
2305 */
2306 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
2307 {
2308 while (qm_frozen(qm) ||
2309 ((qm->fun_type == QM_HW_PF) &&
2310 qm_try_frozen_vfs(qm->pdev, qm_list))) {
2311 msleep(WAIT_PERIOD);
2312 }
2313
2314 udelay(REMOVE_WAIT_DELAY);
2315 }
2316 EXPORT_SYMBOL_GPL(hisi_qm_wait_task_finish);
2317
2318 /**
2319 * hisi_qm_get_free_qp_num() - Get free number of qp in qm.
2320 * @qm: The qm which want to get free qp.
2321 *
2322 * This function return free number of qp in qm.
2323 */
2324 int hisi_qm_get_free_qp_num(struct hisi_qm *qm)
2325 {
2326 int ret;
2327
2328 down_read(&qm->qps_lock);
2329 ret = qm->qp_num - qm->qp_in_used;
2330 up_read(&qm->qps_lock);
2331
2332 return ret;
2333 }
2334 EXPORT_SYMBOL_GPL(hisi_qm_get_free_qp_num);
2335
2336 static void hisi_qp_memory_uninit(struct hisi_qm *qm, int num)
2337 {
2338 struct device *dev = &qm->pdev->dev;
2339 struct qm_dma *qdma;
2340 int i;
2341
2342 for (i = num - 1; i >= 0; i--) {
2343 qdma = &qm->qp_array[i].qdma;
2344 dma_free_coherent(dev, qdma->size, qdma->va, qdma->dma);
2345 }
2346
2347 kfree(qm->qp_array);
2348 }
2349
2350 static int hisi_qp_memory_init(struct hisi_qm *qm, size_t dma_size, int id)
2351 {
2352 struct device *dev = &qm->pdev->dev;
2353 size_t off = qm->sqe_size * QM_Q_DEPTH;
2354 struct hisi_qp *qp;
2355
2356 qp = &qm->qp_array[id];
2357 qp->qdma.va = dma_alloc_coherent(dev, dma_size, &qp->qdma.dma,
2358 GFP_KERNEL);
2359 if (!qp->qdma.va)
2360 return -ENOMEM;
2361
2362 qp->sqe = qp->qdma.va;
2363 qp->sqe_dma = qp->qdma.dma;
2364 qp->cqe = qp->qdma.va + off;
2365 qp->cqe_dma = qp->qdma.dma + off;
2366 qp->qdma.size = dma_size;
2367 qp->qm = qm;
2368 qp->qp_id = id;
2369
2370 return 0;
2371 }
2372
2373 static int hisi_qm_memory_init(struct hisi_qm *qm)
2374 {
2375 struct device *dev = &qm->pdev->dev;
2376 size_t qp_dma_size, off = 0;
2377 int i, ret = 0;
2378
2379 #define QM_INIT_BUF(qm, type, num) do { \
2380 (qm)->type = ((qm)->qdma.va + (off)); \
2381 (qm)->type##_dma = (qm)->qdma.dma + (off); \
2382 off += QMC_ALIGN(sizeof(struct qm_##type) * (num)); \
2383 } while (0)
2384
2385 idr_init(&qm->qp_idr);
2386 qm->qdma.size = QMC_ALIGN(sizeof(struct qm_eqe) * QM_EQ_DEPTH) +
2387 QMC_ALIGN(sizeof(struct qm_aeqe) * QM_Q_DEPTH) +
2388 QMC_ALIGN(sizeof(struct qm_sqc) * qm->qp_num) +
2389 QMC_ALIGN(sizeof(struct qm_cqc) * qm->qp_num);
2390 qm->qdma.va = dma_alloc_coherent(dev, qm->qdma.size, &qm->qdma.dma,
2391 GFP_ATOMIC);
2392 dev_dbg(dev, "allocate qm dma buf size=%zx)\n", qm->qdma.size);
2393 if (!qm->qdma.va)
2394 return -ENOMEM;
2395
2396 QM_INIT_BUF(qm, eqe, QM_EQ_DEPTH);
2397 QM_INIT_BUF(qm, aeqe, QM_Q_DEPTH);
2398 QM_INIT_BUF(qm, sqc, qm->qp_num);
2399 QM_INIT_BUF(qm, cqc, qm->qp_num);
2400
2401 qm->qp_array = kcalloc(qm->qp_num, sizeof(struct hisi_qp), GFP_KERNEL);
2402 if (!qm->qp_array) {
2403 ret = -ENOMEM;
2404 goto err_alloc_qp_array;
2405 }
2406
2407 /* one more page for device or qp statuses */
2408 qp_dma_size = qm->sqe_size * QM_Q_DEPTH +
2409 sizeof(struct qm_cqe) * QM_Q_DEPTH;
2410 qp_dma_size = PAGE_ALIGN(qp_dma_size);
2411 for (i = 0; i < qm->qp_num; i++) {
2412 ret = hisi_qp_memory_init(qm, qp_dma_size, i);
2413 if (ret)
2414 goto err_init_qp_mem;
2415
2416 dev_dbg(dev, "allocate qp dma buf size=%zx)\n", qp_dma_size);
2417 }
2418
2419 return ret;
2420
2421 err_init_qp_mem:
2422 hisi_qp_memory_uninit(qm, i);
2423 err_alloc_qp_array:
2424 dma_free_coherent(dev, qm->qdma.size, qm->qdma.va, qm->qdma.dma);
2425
2426 return ret;
2427 }
2428
2429 static void hisi_qm_pre_init(struct hisi_qm *qm)
2430 {
2431 struct pci_dev *pdev = qm->pdev;
2432
2433 if (qm->ver == QM_HW_V1)
2434 qm->ops = &qm_hw_ops_v1;
2435 else
2436 qm->ops = &qm_hw_ops_v2;
2437
2438 pci_set_drvdata(pdev, qm);
2439 mutex_init(&qm->mailbox_lock);
2440 init_rwsem(&qm->qps_lock);
2441 qm->qp_in_used = 0;
2442 qm->is_frozen = false;
2443 }
2444
2445 static void hisi_qm_pci_uninit(struct hisi_qm *qm)
2446 {
2447 struct pci_dev *pdev = qm->pdev;
2448
2449 pci_free_irq_vectors(pdev);
2450 iounmap(qm->io_base);
2451 pci_release_mem_regions(pdev);
2452 pci_disable_device(pdev);
2453 }
2454
2455 /**
2456 * hisi_qm_uninit() - Uninitialize qm.
2457 * @qm: The qm needed uninit.
2458 *
2459 * This function uninits qm related device resources.
2460 */
2461 void hisi_qm_uninit(struct hisi_qm *qm)
2462 {
2463 struct pci_dev *pdev = qm->pdev;
2464 struct device *dev = &pdev->dev;
2465
2466 down_write(&qm->qps_lock);
2467
2468 if (!qm_avail_state(qm, QM_CLOSE)) {
2469 up_write(&qm->qps_lock);
2470 return;
2471 }
2472
2473 hisi_qp_memory_uninit(qm, qm->qp_num);
2474 idr_destroy(&qm->qp_idr);
2475
2476 if (qm->qdma.va) {
2477 hisi_qm_cache_wb(qm);
2478 dma_free_coherent(dev, qm->qdma.size,
2479 qm->qdma.va, qm->qdma.dma);
2480 memset(&qm->qdma, 0, sizeof(qm->qdma));
2481 }
2482
2483 qm_irq_unregister(qm);
2484 hisi_qm_pci_uninit(qm);
2485 uacce_remove(qm->uacce);
2486 qm->uacce = NULL;
2487
2488 up_write(&qm->qps_lock);
2489 }
2490 EXPORT_SYMBOL_GPL(hisi_qm_uninit);
2491
2492 /**
2493 * hisi_qm_get_vft() - Get vft from a qm.
2494 * @qm: The qm we want to get its vft.
2495 * @base: The base number of queue in vft.
2496 * @number: The number of queues in vft.
2497 *
2498 * We can allocate multiple queues to a qm by configuring virtual function
2499 * table. We get related configures by this function. Normally, we call this
2500 * function in VF driver to get the queue information.
2501 *
2502 * qm hw v1 does not support this interface.
2503 */
2504 int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number)
2505 {
2506 if (!base || !number)
2507 return -EINVAL;
2508
2509 if (!qm->ops->get_vft) {
2510 dev_err(&qm->pdev->dev, "Don't support vft read!\n");
2511 return -EINVAL;
2512 }
2513
2514 return qm->ops->get_vft(qm, base, number);
2515 }
2516 EXPORT_SYMBOL_GPL(hisi_qm_get_vft);
2517
2518 /**
2519 * hisi_qm_set_vft() - Set vft to a qm.
2520 * @qm: The qm we want to set its vft.
2521 * @fun_num: The function number.
2522 * @base: The base number of queue in vft.
2523 * @number: The number of queues in vft.
2524 *
2525 * This function is alway called in PF driver, it is used to assign queues
2526 * among PF and VFs.
2527 *
2528 * Assign queues A~B to PF: hisi_qm_set_vft(qm, 0, A, B - A + 1)
2529 * Assign queues A~B to VF: hisi_qm_set_vft(qm, 2, A, B - A + 1)
2530 * (VF function number 0x2)
2531 */
2532 static int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base,
2533 u32 number)
2534 {
2535 u32 max_q_num = qm->ctrl_qp_num;
2536
2537 if (base >= max_q_num || number > max_q_num ||
2538 (base + number) > max_q_num)
2539 return -EINVAL;
2540
2541 return qm_set_sqc_cqc_vft(qm, fun_num, base, number);
2542 }
2543
2544 static void qm_init_eq_aeq_status(struct hisi_qm *qm)
2545 {
2546 struct hisi_qm_status *status = &qm->status;
2547
2548 status->eq_head = 0;
2549 status->aeq_head = 0;
2550 status->eqc_phase = true;
2551 status->aeqc_phase = true;
2552 }
2553
2554 static int qm_eq_ctx_cfg(struct hisi_qm *qm)
2555 {
2556 struct device *dev = &qm->pdev->dev;
2557 struct qm_eqc *eqc;
2558 dma_addr_t eqc_dma;
2559 int ret;
2560
2561 eqc = kzalloc(sizeof(struct qm_eqc), GFP_KERNEL); //todo
2562 if (!eqc)
2563 return -ENOMEM;
2564 eqc_dma = dma_map_single(dev, eqc, sizeof(struct qm_eqc),
2565 DMA_TO_DEVICE);
2566 if (dma_mapping_error(dev, eqc_dma)) {
2567 kfree(eqc);
2568 return -ENOMEM;
2569 }
2570
2571 eqc->base_l = cpu_to_le32(lower_32_bits(qm->eqe_dma));
2572 eqc->base_h = cpu_to_le32(upper_32_bits(qm->eqe_dma));
2573 if (qm->ver == QM_HW_V1)
2574 eqc->dw3 = cpu_to_le32(QM_EQE_AEQE_SIZE);
2575 eqc->dw6 = cpu_to_le32((QM_EQ_DEPTH - 1) | (1 << QM_EQC_PHASE_SHIFT));
2576
2577 ret = qm_mb(qm, QM_MB_CMD_EQC, eqc_dma, 0, 0);
2578 dma_unmap_single(dev, eqc_dma, sizeof(struct qm_eqc), DMA_TO_DEVICE);
2579 kfree(eqc);
2580
2581 return ret;
2582 }
2583
2584 static int qm_aeq_ctx_cfg(struct hisi_qm *qm)
2585 {
2586 struct device *dev = &qm->pdev->dev;
2587 struct qm_aeqc *aeqc;
2588 dma_addr_t aeqc_dma;
2589 int ret;
2590
2591 aeqc = kzalloc(sizeof(struct qm_aeqc), GFP_KERNEL);
2592 if (!aeqc)
2593 return -ENOMEM;
2594 aeqc_dma = dma_map_single(dev, aeqc, sizeof(struct qm_aeqc),
2595 DMA_TO_DEVICE);
2596 if (dma_mapping_error(dev, aeqc_dma)) {
2597 kfree(aeqc);
2598 return -ENOMEM;
2599 }
2600
2601 aeqc->base_l = cpu_to_le32(lower_32_bits(qm->aeqe_dma));
2602 aeqc->base_h = cpu_to_le32(upper_32_bits(qm->aeqe_dma));
2603 aeqc->dw6 = cpu_to_le32((QM_Q_DEPTH - 1) | (1 << QM_EQC_PHASE_SHIFT));
2604
2605 ret = qm_mb(qm, QM_MB_CMD_AEQC, aeqc_dma, 0, 0);
2606 dma_unmap_single(dev, aeqc_dma, sizeof(struct qm_aeqc), DMA_TO_DEVICE);
2607 kfree(aeqc);
2608
2609 return ret;
2610 }
2611
2612 static int qm_eq_aeq_ctx_cfg(struct hisi_qm *qm)
2613 {
2614 struct device *dev = &qm->pdev->dev;
2615 int ret;
2616
2617 qm_init_eq_aeq_status(qm);
2618
2619 ret = qm_eq_ctx_cfg(qm);
2620 if (ret) {
2621 dev_err(dev, "Set eqc failed!\n");
2622 return ret;
2623 }
2624
2625 return qm_aeq_ctx_cfg(qm);
2626 }
2627
2628 static int __hisi_qm_start(struct hisi_qm *qm)
2629 {
2630 int ret;
2631
2632 WARN_ON(!qm->qdma.dma);
2633
2634 if (qm->fun_type == QM_HW_PF) {
2635 ret = qm_dev_mem_reset(qm);
2636 if (ret)
2637 return ret;
2638
2639 ret = hisi_qm_set_vft(qm, 0, qm->qp_base, qm->qp_num);
2640 if (ret)
2641 return ret;
2642 }
2643
2644 ret = qm_eq_aeq_ctx_cfg(qm);
2645 if (ret)
2646 return ret;
2647
2648 ret = qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);
2649 if (ret)
2650 return ret;
2651
2652 ret = qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);
2653 if (ret)
2654 return ret;
2655
2656 writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK);
2657 writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK);
2658
2659 return 0;
2660 }
2661
2662 /**
2663 * hisi_qm_start() - start qm
2664 * @qm: The qm to be started.
2665 *
2666 * This function starts a qm, then we can allocate qp from this qm.
2667 */
2668 int hisi_qm_start(struct hisi_qm *qm)
2669 {
2670 struct device *dev = &qm->pdev->dev;
2671 int ret = 0;
2672
2673 down_write(&qm->qps_lock);
2674
2675 if (!qm_avail_state(qm, QM_START)) {
2676 up_write(&qm->qps_lock);
2677 return -EPERM;
2678 }
2679
2680 dev_dbg(dev, "qm start with %d queue pairs\n", qm->qp_num);
2681
2682 if (!qm->qp_num) {
2683 dev_err(dev, "qp_num should not be 0\n");
2684 ret = -EINVAL;
2685 goto err_unlock;
2686 }
2687
2688 ret = __hisi_qm_start(qm);
2689 if (!ret)
2690 atomic_set(&qm->status.flags, QM_START);
2691
2692 err_unlock:
2693 up_write(&qm->qps_lock);
2694 return ret;
2695 }
2696 EXPORT_SYMBOL_GPL(hisi_qm_start);
2697
2698 static int qm_restart(struct hisi_qm *qm)
2699 {
2700 struct device *dev = &qm->pdev->dev;
2701 struct hisi_qp *qp;
2702 int ret, i;
2703
2704 ret = hisi_qm_start(qm);
2705 if (ret < 0)
2706 return ret;
2707
2708 down_write(&qm->qps_lock);
2709 for (i = 0; i < qm->qp_num; i++) {
2710 qp = &qm->qp_array[i];
2711 if (atomic_read(&qp->qp_status.flags) == QP_STOP &&
2712 qp->is_resetting == true) {
2713 ret = qm_start_qp_nolock(qp, 0);
2714 if (ret < 0) {
2715 dev_err(dev, "Failed to start qp%d!\n", i);
2716
2717 up_write(&qm->qps_lock);
2718 return ret;
2719 }
2720 qp->is_resetting = false;
2721 }
2722 }
2723 up_write(&qm->qps_lock);
2724
2725 return 0;
2726 }
2727
2728 /* Stop started qps in reset flow */
2729 static int qm_stop_started_qp(struct hisi_qm *qm)
2730 {
2731 struct device *dev = &qm->pdev->dev;
2732 struct hisi_qp *qp;
2733 int i, ret;
2734
2735 for (i = 0; i < qm->qp_num; i++) {
2736 qp = &qm->qp_array[i];
2737 if (qp && atomic_read(&qp->qp_status.flags) == QP_START) {
2738 qp->is_resetting = true;
2739 ret = qm_stop_qp_nolock(qp);
2740 if (ret < 0) {
2741 dev_err(dev, "Failed to stop qp%d!\n", i);
2742 return ret;
2743 }
2744 }
2745 }
2746
2747 return 0;
2748 }
2749
2750
2751 /**
2752 * qm_clear_queues() - Clear all queues memory in a qm.
2753 * @qm: The qm in which the queues will be cleared.
2754 *
2755 * This function clears all queues memory in a qm. Reset of accelerator can
2756 * use this to clear queues.
2757 */
2758 static void qm_clear_queues(struct hisi_qm *qm)
2759 {
2760 struct hisi_qp *qp;
2761 int i;
2762
2763 for (i = 0; i < qm->qp_num; i++) {
2764 qp = &qm->qp_array[i];
2765 if (qp->is_resetting)
2766 memset(qp->qdma.va, 0, qp->qdma.size);
2767 }
2768
2769 memset(qm->qdma.va, 0, qm->qdma.size);
2770 }
2771
2772 /**
2773 * hisi_qm_stop() - Stop a qm.
2774 * @qm: The qm which will be stopped.
2775 * @r: The reason to stop qm.
2776 *
2777 * This function stops qm and its qps, then qm can not accept request.
2778 * Related resources are not released at this state, we can use hisi_qm_start
2779 * to let qm start again.
2780 */
2781 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r)
2782 {
2783 struct device *dev = &qm->pdev->dev;
2784 int ret = 0;
2785
2786 down_write(&qm->qps_lock);
2787
2788 qm->status.stop_reason = r;
2789 if (!qm_avail_state(qm, QM_STOP)) {
2790 ret = -EPERM;
2791 goto err_unlock;
2792 }
2793
2794 if (qm->status.stop_reason == QM_SOFT_RESET ||
2795 qm->status.stop_reason == QM_FLR) {
2796 ret = qm_stop_started_qp(qm);
2797 if (ret < 0) {
2798 dev_err(dev, "Failed to stop started qp!\n");
2799 goto err_unlock;
2800 }
2801 }
2802
2803 /* Mask eq and aeq irq */
2804 writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK);
2805 writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK);
2806
2807 if (qm->fun_type == QM_HW_PF) {
2808 ret = hisi_qm_set_vft(qm, 0, 0, 0);
2809 if (ret < 0) {
2810 dev_err(dev, "Failed to set vft!\n");
2811 ret = -EBUSY;
2812 goto err_unlock;
2813 }
2814 }
2815
2816 qm_clear_queues(qm);
2817 atomic_set(&qm->status.flags, QM_STOP);
2818
2819 err_unlock:
2820 up_write(&qm->qps_lock);
2821 return ret;
2822 }
2823 EXPORT_SYMBOL_GPL(hisi_qm_stop);
2824
2825 static ssize_t qm_status_read(struct file *filp, char __user *buffer,
2826 size_t count, loff_t *pos)
2827 {
2828 struct hisi_qm *qm = filp->private_data;
2829 char buf[QM_DBG_READ_LEN];
2830 int val, len;
2831
2832 val = atomic_read(&qm->status.flags);
2833 len = scnprintf(buf, QM_DBG_READ_LEN, "%s\n", qm_s[val]);
2834
2835 return simple_read_from_buffer(buffer, count, pos, buf, len);
2836 }
2837
2838 static const struct file_operations qm_status_fops = {
2839 .owner = THIS_MODULE,
2840 .open = simple_open,
2841 .read = qm_status_read,
2842 };
2843
2844 static int qm_debugfs_atomic64_set(void *data, u64 val)
2845 {
2846 if (val)
2847 return -EINVAL;
2848
2849 atomic64_set((atomic64_t *)data, 0);
2850
2851 return 0;
2852 }
2853
2854 static int qm_debugfs_atomic64_get(void *data, u64 *val)
2855 {
2856 *val = atomic64_read((atomic64_t *)data);
2857
2858 return 0;
2859 }
2860
2861 DEFINE_DEBUGFS_ATTRIBUTE(qm_atomic64_ops, qm_debugfs_atomic64_get,
2862 qm_debugfs_atomic64_set, "%llu\n");
2863
2864 /**
2865 * hisi_qm_debug_init() - Initialize qm related debugfs files.
2866 * @qm: The qm for which we want to add debugfs files.
2867 *
2868 * Create qm related debugfs files.
2869 */
2870 void hisi_qm_debug_init(struct hisi_qm *qm)
2871 {
2872 struct qm_dfx *dfx = &qm->debug.dfx;
2873 struct dentry *qm_d;
2874 void *data;
2875 int i;
2876
2877 qm_d = debugfs_create_dir("qm", qm->debug.debug_root);
2878 qm->debug.qm_d = qm_d;
2879
2880 /* only show this in PF */
2881 if (qm->fun_type == QM_HW_PF)
2882 for (i = CURRENT_Q; i < DEBUG_FILE_NUM; i++)
2883 qm_create_debugfs_file(qm, i);
2884
2885 debugfs_create_file("regs", 0444, qm->debug.qm_d, qm, &qm_regs_fops);
2886
2887 debugfs_create_file("cmd", 0444, qm->debug.qm_d, qm, &qm_cmd_fops);
2888
2889 debugfs_create_file("status", 0444, qm->debug.qm_d, qm,
2890 &qm_status_fops);
2891 for (i = 0; i < ARRAY_SIZE(qm_dfx_files); i++) {
2892 data = (atomic64_t *)((uintptr_t)dfx + qm_dfx_files[i].offset);
2893 debugfs_create_file(qm_dfx_files[i].name,
2894 0644,
2895 qm_d,
2896 data,
2897 &qm_atomic64_ops);
2898 }
2899 }
2900 EXPORT_SYMBOL_GPL(hisi_qm_debug_init);
2901
2902 /**
2903 * hisi_qm_debug_regs_clear() - clear qm debug related registers.
2904 * @qm: The qm for which we want to clear its debug registers.
2905 */
2906 void hisi_qm_debug_regs_clear(struct hisi_qm *qm)
2907 {
2908 struct qm_dfx_registers *regs;
2909 int i;
2910
2911 /* clear current_q */
2912 writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
2913 writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
2914
2915 /*
2916 * these registers are reading and clearing, so clear them after
2917 * reading them.
2918 */
2919 writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE);
2920
2921 regs = qm_dfx_regs;
2922 for (i = 0; i < CNT_CYC_REGS_NUM; i++) {
2923 readl(qm->io_base + regs->reg_offset);
2924 regs++;
2925 }
2926
2927 writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE);
2928 }
2929 EXPORT_SYMBOL_GPL(hisi_qm_debug_regs_clear);
2930
2931 static void qm_hw_error_init(struct hisi_qm *qm)
2932 {
2933 const struct hisi_qm_err_info *err_info = &qm->err_ini->err_info;
2934
2935 if (!qm->ops->hw_error_init) {
2936 dev_err(&qm->pdev->dev, "QM doesn't support hw error handling!\n");
2937 return;
2938 }
2939
2940 qm->ops->hw_error_init(qm, err_info->ce, err_info->nfe, err_info->fe);
2941 }
2942
2943 static void qm_hw_error_uninit(struct hisi_qm *qm)
2944 {
2945 if (!qm->ops->hw_error_uninit) {
2946 dev_err(&qm->pdev->dev, "Unexpected QM hw error uninit!\n");
2947 return;
2948 }
2949
2950 qm->ops->hw_error_uninit(qm);
2951 }
2952
2953 static enum acc_err_result qm_hw_error_handle(struct hisi_qm *qm)
2954 {
2955 if (!qm->ops->hw_error_handle) {
2956 dev_err(&qm->pdev->dev, "QM doesn't support hw error report!\n");
2957 return ACC_ERR_NONE;
2958 }
2959
2960 return qm->ops->hw_error_handle(qm);
2961 }
2962
2963 /**
2964 * hisi_qm_dev_err_init() - Initialize device error configuration.
2965 * @qm: The qm for which we want to do error initialization.
2966 *
2967 * Initialize QM and device error related configuration.
2968 */
2969 void hisi_qm_dev_err_init(struct hisi_qm *qm)
2970 {
2971 if (qm->fun_type == QM_HW_VF)
2972 return;
2973
2974 qm_hw_error_init(qm);
2975
2976 if (!qm->err_ini->hw_err_enable) {
2977 dev_err(&qm->pdev->dev, "Device doesn't support hw error init!\n");
2978 return;
2979 }
2980 qm->err_ini->hw_err_enable(qm);
2981 }
2982 EXPORT_SYMBOL_GPL(hisi_qm_dev_err_init);
2983
2984 /**
2985 * hisi_qm_dev_err_uninit() - Uninitialize device error configuration.
2986 * @qm: The qm for which we want to do error uninitialization.
2987 *
2988 * Uninitialize QM and device error related configuration.
2989 */
2990 void hisi_qm_dev_err_uninit(struct hisi_qm *qm)
2991 {
2992 if (qm->fun_type == QM_HW_VF)
2993 return;
2994
2995 qm_hw_error_uninit(qm);
2996
2997 if (!qm->err_ini->hw_err_disable) {
2998 dev_err(&qm->pdev->dev, "Unexpected device hw error uninit!\n");
2999 return;
3000 }
3001 qm->err_ini->hw_err_disable(qm);
3002 }
3003 EXPORT_SYMBOL_GPL(hisi_qm_dev_err_uninit);
3004
3005 /**
3006 * hisi_qm_free_qps() - free multiple queue pairs.
3007 * @qps: The queue pairs need to be freed.
3008 * @qp_num: The num of queue pairs.
3009 */
3010 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num)
3011 {
3012 int i;
3013
3014 if (!qps || qp_num <= 0)
3015 return;
3016
3017 for (i = qp_num - 1; i >= 0; i--)
3018 hisi_qm_release_qp(qps[i]);
3019 }
3020 EXPORT_SYMBOL_GPL(hisi_qm_free_qps);
3021
3022 static void free_list(struct list_head *head)
3023 {
3024 struct hisi_qm_resource *res, *tmp;
3025
3026 list_for_each_entry_safe(res, tmp, head, list) {
3027 list_del(&res->list);
3028 kfree(res);
3029 }
3030 }
3031
3032 static int hisi_qm_sort_devices(int node, struct list_head *head,
3033 struct hisi_qm_list *qm_list)
3034 {
3035 struct hisi_qm_resource *res, *tmp;
3036 struct hisi_qm *qm;
3037 struct list_head *n;
3038 struct device *dev;
3039 int dev_node = 0;
3040
3041 list_for_each_entry(qm, &qm_list->list, list) {
3042 dev = &qm->pdev->dev;
3043
3044 if (IS_ENABLED(CONFIG_NUMA)) {
3045 dev_node = dev_to_node(dev);
3046 if (dev_node < 0)
3047 dev_node = 0;
3048 }
3049
3050 res = kzalloc(sizeof(*res), GFP_KERNEL);
3051 if (!res)
3052 return -ENOMEM;
3053
3054 res->qm = qm;
3055 res->distance = node_distance(dev_node, node);
3056 n = head;
3057 list_for_each_entry(tmp, head, list) {
3058 if (res->distance < tmp->distance) {
3059 n = &tmp->list;
3060 break;
3061 }
3062 }
3063 list_add_tail(&res->list, n);
3064 }
3065
3066 return 0;
3067 }
3068
3069 /**
3070 * hisi_qm_alloc_qps_node() - Create multiple queue pairs.
3071 * @qm_list: The list of all available devices.
3072 * @qp_num: The number of queue pairs need created.
3073 * @alg_type: The algorithm type.
3074 * @node: The numa node.
3075 * @qps: The queue pairs need created.
3076 *
3077 * This function will sort all available device according to numa distance.
3078 * Then try to create all queue pairs from one device, if all devices do
3079 * not meet the requirements will return error.
3080 */
3081 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
3082 u8 alg_type, int node, struct hisi_qp **qps)
3083 {
3084 struct hisi_qm_resource *tmp;
3085 int ret = -ENODEV;
3086 LIST_HEAD(head);
3087 int i;
3088
3089 if (!qps || !qm_list || qp_num <= 0)
3090 return -EINVAL;
3091
3092 mutex_lock(&qm_list->lock);
3093 if (hisi_qm_sort_devices(node, &head, qm_list)) {
3094 mutex_unlock(&qm_list->lock);
3095 goto err;
3096 }
3097
3098 list_for_each_entry(tmp, &head, list) {
3099 for (i = 0; i < qp_num; i++) {
3100 qps[i] = hisi_qm_create_qp(tmp->qm, alg_type);
3101 if (IS_ERR(qps[i])) {
3102 hisi_qm_free_qps(qps, i);
3103 break;
3104 }
3105 }
3106
3107 if (i == qp_num) {
3108 ret = 0;
3109 break;
3110 }
3111 }
3112
3113 mutex_unlock(&qm_list->lock);
3114 if (ret)
3115 pr_info("Failed to create qps, node[%d], alg[%d], qp[%d]!\n",
3116 node, alg_type, qp_num);
3117
3118 err:
3119 free_list(&head);
3120 return ret;
3121 }
3122 EXPORT_SYMBOL_GPL(hisi_qm_alloc_qps_node);
3123
3124 static int qm_vf_q_assign(struct hisi_qm *qm, u32 num_vfs)
3125 {
3126 u32 remain_q_num, q_num, i, j;
3127 u32 q_base = qm->qp_num;
3128 int ret;
3129
3130 if (!num_vfs)
3131 return -EINVAL;
3132
3133 remain_q_num = qm->ctrl_qp_num - qm->qp_num;
3134
3135 /* If remain queues not enough, return error. */
3136 if (qm->ctrl_qp_num < qm->qp_num || remain_q_num < num_vfs)
3137 return -EINVAL;
3138
3139 q_num = remain_q_num / num_vfs;
3140 for (i = 1; i <= num_vfs; i++) {
3141 if (i == num_vfs)
3142 q_num += remain_q_num % num_vfs;
3143 ret = hisi_qm_set_vft(qm, i, q_base, q_num);
3144 if (ret) {
3145 for (j = i; j > 0; j--)
3146 hisi_qm_set_vft(qm, j, 0, 0);
3147 return ret;
3148 }
3149 q_base += q_num;
3150 }
3151
3152 return 0;
3153 }
3154
3155 static int qm_clear_vft_config(struct hisi_qm *qm)
3156 {
3157 int ret;
3158 u32 i;
3159
3160 for (i = 1; i <= qm->vfs_num; i++) {
3161 ret = hisi_qm_set_vft(qm, i, 0, 0);
3162 if (ret)
3163 return ret;
3164 }
3165 qm->vfs_num = 0;
3166
3167 return 0;
3168 }
3169
3170 /**
3171 * hisi_qm_sriov_enable() - enable virtual functions
3172 * @pdev: the PCIe device
3173 * @max_vfs: the number of virtual functions to enable
3174 *
3175 * Returns the number of enabled VFs. If there are VFs enabled already or
3176 * max_vfs is more than the total number of device can be enabled, returns
3177 * failure.
3178 */
3179 int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs)
3180 {
3181 struct hisi_qm *qm = pci_get_drvdata(pdev);
3182 int pre_existing_vfs, num_vfs, total_vfs, ret;
3183
3184 total_vfs = pci_sriov_get_totalvfs(pdev);
3185 pre_existing_vfs = pci_num_vf(pdev);
3186 if (pre_existing_vfs) {
3187 pci_err(pdev, "%d VFs already enabled. Please disable pre-enabled VFs!\n",
3188 pre_existing_vfs);
3189 return 0;
3190 }
3191
3192 num_vfs = min_t(int, max_vfs, total_vfs);
3193 ret = qm_vf_q_assign(qm, num_vfs);
3194 if (ret) {
3195 pci_err(pdev, "Can't assign queues for VF!\n");
3196 return ret;
3197 }
3198
3199 qm->vfs_num = num_vfs;
3200
3201 ret = pci_enable_sriov(pdev, num_vfs);
3202 if (ret) {
3203 pci_err(pdev, "Can't enable VF!\n");
3204 qm_clear_vft_config(qm);
3205 return ret;
3206 }
3207
3208 pci_info(pdev, "VF enabled, vfs_num(=%d)!\n", num_vfs);
3209
3210 return num_vfs;
3211 }
3212 EXPORT_SYMBOL_GPL(hisi_qm_sriov_enable);
3213
3214 /**
3215 * hisi_qm_sriov_disable - disable virtual functions
3216 * @pdev: the PCI device.
3217 * @is_frozen: true when all the VFs are frozen.
3218 *
3219 * Return failure if there are VFs assigned already or VF is in used.
3220 */
3221 int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen)
3222 {
3223 struct hisi_qm *qm = pci_get_drvdata(pdev);
3224
3225 if (pci_vfs_assigned(pdev)) {
3226 pci_err(pdev, "Failed to disable VFs as VFs are assigned!\n");
3227 return -EPERM;
3228 }
3229
3230 /* While VF is in used, SRIOV cannot be disabled. */
3231 if (!is_frozen && qm_try_frozen_vfs(pdev, qm->qm_list)) {
3232 pci_err(pdev, "Task is using its VF!\n");
3233 return -EBUSY;
3234 }
3235
3236 pci_disable_sriov(pdev);
3237 return qm_clear_vft_config(qm);
3238 }
3239 EXPORT_SYMBOL_GPL(hisi_qm_sriov_disable);
3240
3241 /**
3242 * hisi_qm_sriov_configure - configure the number of VFs
3243 * @pdev: The PCI device
3244 * @num_vfs: The number of VFs need enabled
3245 *
3246 * Enable SR-IOV according to num_vfs, 0 means disable.
3247 */
3248 int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs)
3249 {
3250 if (num_vfs == 0)
3251 return hisi_qm_sriov_disable(pdev, 0);
3252 else
3253 return hisi_qm_sriov_enable(pdev, num_vfs);
3254 }
3255 EXPORT_SYMBOL_GPL(hisi_qm_sriov_configure);
3256
3257 static enum acc_err_result qm_dev_err_handle(struct hisi_qm *qm)
3258 {
3259 u32 err_sts;
3260
3261 if (!qm->err_ini->get_dev_hw_err_status) {
3262 dev_err(&qm->pdev->dev, "Device doesn't support get hw error status!\n");
3263 return ACC_ERR_NONE;
3264 }
3265
3266 /* get device hardware error status */
3267 err_sts = qm->err_ini->get_dev_hw_err_status(qm);
3268 if (err_sts) {
3269 if (err_sts & qm->err_ini->err_info.ecc_2bits_mask)
3270 qm->err_status.is_dev_ecc_mbit = true;
3271
3272 if (!qm->err_ini->log_dev_hw_err) {
3273 dev_err(&qm->pdev->dev, "Device doesn't support log hw error!\n");
3274 return ACC_ERR_NEED_RESET;
3275 }
3276
3277 qm->err_ini->log_dev_hw_err(qm, err_sts);
3278 return ACC_ERR_NEED_RESET;
3279 }
3280
3281 return ACC_ERR_RECOVERED;
3282 }
3283
3284 static enum acc_err_result qm_process_dev_error(struct hisi_qm *qm)
3285 {
3286 enum acc_err_result qm_ret, dev_ret;
3287
3288 /* log qm error */
3289 qm_ret = qm_hw_error_handle(qm);
3290
3291 /* log device error */
3292 dev_ret = qm_dev_err_handle(qm);
3293
3294 return (qm_ret == ACC_ERR_NEED_RESET ||
3295 dev_ret == ACC_ERR_NEED_RESET) ?
3296 ACC_ERR_NEED_RESET : ACC_ERR_RECOVERED;
3297 }
3298
3299 /**
3300 * hisi_qm_dev_err_detected() - Get device and qm error status then log it.
3301 * @pdev: The PCI device which need report error.
3302 * @state: The connectivity between CPU and device.
3303 *
3304 * We register this function into PCIe AER handlers, It will report device or
3305 * qm hardware error status when error occur.
3306 */
3307 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
3308 pci_channel_state_t state)
3309 {
3310 struct hisi_qm *qm = pci_get_drvdata(pdev);
3311 enum acc_err_result ret;
3312
3313 if (pdev->is_virtfn)
3314 return PCI_ERS_RESULT_NONE;
3315
3316 pci_info(pdev, "PCI error detected, state(=%d)!!\n", state);
3317 if (state == pci_channel_io_perm_failure)
3318 return PCI_ERS_RESULT_DISCONNECT;
3319
3320 ret = qm_process_dev_error(qm);
3321 if (ret == ACC_ERR_NEED_RESET)
3322 return PCI_ERS_RESULT_NEED_RESET;
3323
3324 return PCI_ERS_RESULT_RECOVERED;
3325 }
3326 EXPORT_SYMBOL_GPL(hisi_qm_dev_err_detected);
3327
3328 static u32 qm_get_hw_error_status(struct hisi_qm *qm)
3329 {
3330 return readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
3331 }
3332
3333 static int qm_check_req_recv(struct hisi_qm *qm)
3334 {
3335 struct pci_dev *pdev = qm->pdev;
3336 int ret;
3337 u32 val;
3338
3339 writel(ACC_VENDOR_ID_VALUE, qm->io_base + QM_PEH_VENDOR_ID);
3340 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
3341 (val == ACC_VENDOR_ID_VALUE),
3342 POLL_PERIOD, POLL_TIMEOUT);
3343 if (ret) {
3344 dev_err(&pdev->dev, "Fails to read QM reg!\n");
3345 return ret;
3346 }
3347
3348 writel(PCI_VENDOR_ID_HUAWEI, qm->io_base + QM_PEH_VENDOR_ID);
3349 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
3350 (val == PCI_VENDOR_ID_HUAWEI),
3351 POLL_PERIOD, POLL_TIMEOUT);
3352 if (ret)
3353 dev_err(&pdev->dev, "Fails to read QM reg in the second time!\n");
3354
3355 return ret;
3356 }
3357
3358 static int qm_set_pf_mse(struct hisi_qm *qm, bool set)
3359 {
3360 struct pci_dev *pdev = qm->pdev;
3361 u16 cmd;
3362 int i;
3363
3364 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
3365 if (set)
3366 cmd |= PCI_COMMAND_MEMORY;
3367 else
3368 cmd &= ~PCI_COMMAND_MEMORY;
3369
3370 pci_write_config_word(pdev, PCI_COMMAND, cmd);
3371 for (i = 0; i < MAX_WAIT_COUNTS; i++) {
3372 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
3373 if (set == ((cmd & PCI_COMMAND_MEMORY) >> 1))
3374 return 0;
3375
3376 udelay(1);
3377 }
3378
3379 return -ETIMEDOUT;
3380 }
3381
3382 static int qm_set_vf_mse(struct hisi_qm *qm, bool set)
3383 {
3384 struct pci_dev *pdev = qm->pdev;
3385 u16 sriov_ctrl;
3386 int pos;
3387 int i;
3388
3389 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
3390 pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &sriov_ctrl);
3391 if (set)
3392 sriov_ctrl |= PCI_SRIOV_CTRL_MSE;
3393 else
3394 sriov_ctrl &= ~PCI_SRIOV_CTRL_MSE;
3395 pci_write_config_word(pdev, pos + PCI_SRIOV_CTRL, sriov_ctrl);
3396
3397 for (i = 0; i < MAX_WAIT_COUNTS; i++) {
3398 pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &sriov_ctrl);
3399 if (set == (sriov_ctrl & PCI_SRIOV_CTRL_MSE) >>
3400 ACC_PEH_SRIOV_CTRL_VF_MSE_SHIFT)
3401 return 0;
3402
3403 udelay(1);
3404 }
3405
3406 return -ETIMEDOUT;
3407 }
3408
3409 static int qm_set_msi(struct hisi_qm *qm, bool set)
3410 {
3411 struct pci_dev *pdev = qm->pdev;
3412
3413 if (set) {
3414 pci_write_config_dword(pdev, pdev->msi_cap + PCI_MSI_MASK_64,
3415 0);
3416 } else {
3417 pci_write_config_dword(pdev, pdev->msi_cap + PCI_MSI_MASK_64,
3418 ACC_PEH_MSI_DISABLE);
3419 if (qm->err_status.is_qm_ecc_mbit ||
3420 qm->err_status.is_dev_ecc_mbit)
3421 return 0;
3422
3423 mdelay(1);
3424 if (readl(qm->io_base + QM_PEH_DFX_INFO0))
3425 return -EFAULT;
3426 }
3427
3428 return 0;
3429 }
3430
3431 static int qm_vf_reset_prepare(struct hisi_qm *qm,
3432 enum qm_stop_reason stop_reason)
3433 {
3434 struct hisi_qm_list *qm_list = qm->qm_list;
3435 struct pci_dev *pdev = qm->pdev;
3436 struct pci_dev *virtfn;
3437 struct hisi_qm *vf_qm;
3438 int ret = 0;
3439
3440 mutex_lock(&qm_list->lock);
3441 list_for_each_entry(vf_qm, &qm_list->list, list) {
3442 virtfn = vf_qm->pdev;
3443 if (virtfn == pdev)
3444 continue;
3445
3446 if (pci_physfn(virtfn) == pdev) {
3447 /* save VFs PCIE BAR configuration */
3448 pci_save_state(virtfn);
3449
3450 ret = hisi_qm_stop(vf_qm, stop_reason);
3451 if (ret)
3452 goto stop_fail;
3453 }
3454 }
3455
3456 stop_fail:
3457 mutex_unlock(&qm_list->lock);
3458 return ret;
3459 }
3460
3461 static int qm_reset_prepare_ready(struct hisi_qm *qm)
3462 {
3463 struct pci_dev *pdev = qm->pdev;
3464 struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
3465 int delay = 0;
3466
3467 /* All reset requests need to be queued for processing */
3468 while (test_and_set_bit(QM_DEV_RESET_FLAG, &pf_qm->reset_flag)) {
3469 msleep(++delay);
3470 if (delay > QM_RESET_WAIT_TIMEOUT)
3471 return -EBUSY;
3472 }
3473
3474 return 0;
3475 }
3476
3477 static int qm_controller_reset_prepare(struct hisi_qm *qm)
3478 {
3479 struct pci_dev *pdev = qm->pdev;
3480 int ret;
3481
3482 ret = qm_reset_prepare_ready(qm);
3483 if (ret) {
3484 pci_err(pdev, "Controller reset not ready!\n");
3485 return ret;
3486 }
3487
3488 if (qm->vfs_num) {
3489 ret = qm_vf_reset_prepare(qm, QM_SOFT_RESET);
3490 if (ret) {
3491 pci_err(pdev, "Fails to stop VFs!\n");
3492 return ret;
3493 }
3494 }
3495
3496 ret = hisi_qm_stop(qm, QM_SOFT_RESET);
3497 if (ret) {
3498 pci_err(pdev, "Fails to stop QM!\n");
3499 return ret;
3500 }
3501
3502 return 0;
3503 }
3504
3505 static void qm_dev_ecc_mbit_handle(struct hisi_qm *qm)
3506 {
3507 u32 nfe_enb = 0;
3508
3509 if (!qm->err_status.is_dev_ecc_mbit &&
3510 qm->err_status.is_qm_ecc_mbit &&
3511 qm->err_ini->close_axi_master_ooo) {
3512
3513 qm->err_ini->close_axi_master_ooo(qm);
3514
3515 } else if (qm->err_status.is_dev_ecc_mbit &&
3516 !qm->err_status.is_qm_ecc_mbit &&
3517 !qm->err_ini->close_axi_master_ooo) {
3518
3519 nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);
3520 writel(nfe_enb & QM_RAS_NFE_MBIT_DISABLE,
3521 qm->io_base + QM_RAS_NFE_ENABLE);
3522 writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET);
3523 }
3524 }
3525
3526 static int qm_soft_reset(struct hisi_qm *qm)
3527 {
3528 struct pci_dev *pdev = qm->pdev;
3529 int ret;
3530 u32 val;
3531
3532 /* Ensure all doorbells and mailboxes received by QM */
3533 ret = qm_check_req_recv(qm);
3534 if (ret)
3535 return ret;
3536
3537 if (qm->vfs_num) {
3538 ret = qm_set_vf_mse(qm, false);
3539 if (ret) {
3540 pci_err(pdev, "Fails to disable vf MSE bit.\n");
3541 return ret;
3542 }
3543 }
3544
3545 ret = qm_set_msi(qm, false);
3546 if (ret) {
3547 pci_err(pdev, "Fails to disable PEH MSI bit.\n");
3548 return ret;
3549 }
3550
3551 qm_dev_ecc_mbit_handle(qm);
3552
3553 /* OOO register set and check */
3554 writel(ACC_MASTER_GLOBAL_CTRL_SHUTDOWN,
3555 qm->io_base + ACC_MASTER_GLOBAL_CTRL);
3556
3557 /* If bus lock, reset chip */
3558 ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,
3559 val,
3560 (val == ACC_MASTER_TRANS_RETURN_RW),
3561 POLL_PERIOD, POLL_TIMEOUT);
3562 if (ret) {
3563 pci_emerg(pdev, "Bus lock! Please reset system.\n");
3564 return ret;
3565 }
3566
3567 ret = qm_set_pf_mse(qm, false);
3568 if (ret) {
3569 pci_err(pdev, "Fails to disable pf MSE bit.\n");
3570 return ret;
3571 }
3572
3573 /* The reset related sub-control registers are not in PCI BAR */
3574 if (ACPI_HANDLE(&pdev->dev)) {
3575 unsigned long long value = 0;
3576 acpi_status s;
3577
3578 s = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
3579 qm->err_ini->err_info.acpi_rst,
3580 NULL, &value);
3581 if (ACPI_FAILURE(s)) {
3582 pci_err(pdev, "NO controller reset method!\n");
3583 return -EIO;
3584 }
3585
3586 if (value) {
3587 pci_err(pdev, "Reset step %llu failed!\n", value);
3588 return -EIO;
3589 }
3590 } else {
3591 pci_err(pdev, "No reset method!\n");
3592 return -EINVAL;
3593 }
3594
3595 return 0;
3596 }
3597
3598 static int qm_vf_reset_done(struct hisi_qm *qm)
3599 {
3600 struct hisi_qm_list *qm_list = qm->qm_list;
3601 struct pci_dev *pdev = qm->pdev;
3602 struct pci_dev *virtfn;
3603 struct hisi_qm *vf_qm;
3604 int ret = 0;
3605
3606 mutex_lock(&qm_list->lock);
3607 list_for_each_entry(vf_qm, &qm_list->list, list) {
3608 virtfn = vf_qm->pdev;
3609 if (virtfn == pdev)
3610 continue;
3611
3612 if (pci_physfn(virtfn) == pdev) {
3613 /* enable VFs PCIE BAR configuration */
3614 pci_restore_state(virtfn);
3615
3616 ret = qm_restart(vf_qm);
3617 if (ret)
3618 goto restart_fail;
3619 }
3620 }
3621
3622 restart_fail:
3623 mutex_unlock(&qm_list->lock);
3624 return ret;
3625 }
3626
3627 static u32 qm_get_dev_err_status(struct hisi_qm *qm)
3628 {
3629 return qm->err_ini->get_dev_hw_err_status(qm);
3630 }
3631
3632 static int qm_dev_hw_init(struct hisi_qm *qm)
3633 {
3634 return qm->err_ini->hw_init(qm);
3635 }
3636
3637 static void qm_restart_prepare(struct hisi_qm *qm)
3638 {
3639 u32 value;
3640
3641 if (!qm->err_status.is_qm_ecc_mbit &&
3642 !qm->err_status.is_dev_ecc_mbit)
3643 return;
3644
3645 /* temporarily close the OOO port used for PEH to write out MSI */
3646 value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
3647 writel(value & ~qm->err_ini->err_info.msi_wr_port,
3648 qm->io_base + ACC_AM_CFG_PORT_WR_EN);
3649
3650 /* clear dev ecc 2bit error source if having */
3651 value = qm_get_dev_err_status(qm) &
3652 qm->err_ini->err_info.ecc_2bits_mask;
3653 if (value && qm->err_ini->clear_dev_hw_err_status)
3654 qm->err_ini->clear_dev_hw_err_status(qm, value);
3655
3656 /* clear QM ecc mbit error source */
3657 writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SOURCE);
3658
3659 /* clear AM Reorder Buffer ecc mbit source */
3660 writel(ACC_ROB_ECC_ERR_MULTPL, qm->io_base + ACC_AM_ROB_ECC_INT_STS);
3661
3662 if (qm->err_ini->open_axi_master_ooo)
3663 qm->err_ini->open_axi_master_ooo(qm);
3664 }
3665
3666 static void qm_restart_done(struct hisi_qm *qm)
3667 {
3668 u32 value;
3669
3670 if (!qm->err_status.is_qm_ecc_mbit &&
3671 !qm->err_status.is_dev_ecc_mbit)
3672 return;
3673
3674 /* open the OOO port for PEH to write out MSI */
3675 value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
3676 value |= qm->err_ini->err_info.msi_wr_port;
3677 writel(value, qm->io_base + ACC_AM_CFG_PORT_WR_EN);
3678
3679 qm->err_status.is_qm_ecc_mbit = false;
3680 qm->err_status.is_dev_ecc_mbit = false;
3681 }
3682
3683 static int qm_controller_reset_done(struct hisi_qm *qm)
3684 {
3685 struct pci_dev *pdev = qm->pdev;
3686 int ret;
3687
3688 ret = qm_set_msi(qm, true);
3689 if (ret) {
3690 pci_err(pdev, "Fails to enable PEH MSI bit!\n");
3691 return ret;
3692 }
3693
3694 ret = qm_set_pf_mse(qm, true);
3695 if (ret) {
3696 pci_err(pdev, "Fails to enable pf MSE bit!\n");
3697 return ret;
3698 }
3699
3700 if (qm->vfs_num) {
3701 ret = qm_set_vf_mse(qm, true);
3702 if (ret) {
3703 pci_err(pdev, "Fails to enable vf MSE bit!\n");
3704 return ret;
3705 }
3706 }
3707
3708 ret = qm_dev_hw_init(qm);
3709 if (ret) {
3710 pci_err(pdev, "Failed to init device\n");
3711 return ret;
3712 }
3713
3714 qm_restart_prepare(qm);
3715
3716 ret = qm_restart(qm);
3717 if (ret) {
3718 pci_err(pdev, "Failed to start QM!\n");
3719 return ret;
3720 }
3721
3722 if (qm->vfs_num) {
3723 ret = qm_vf_q_assign(qm, qm->vfs_num);
3724 if (ret) {
3725 pci_err(pdev, "Failed to assign queue!\n");
3726 return ret;
3727 }
3728 }
3729
3730 ret = qm_vf_reset_done(qm);
3731 if (ret) {
3732 pci_err(pdev, "Failed to start VFs!\n");
3733 return -EPERM;
3734 }
3735
3736 hisi_qm_dev_err_init(qm);
3737 qm_restart_done(qm);
3738
3739 clear_bit(QM_DEV_RESET_FLAG, &qm->reset_flag);
3740
3741 return 0;
3742 }
3743
3744 static int qm_controller_reset(struct hisi_qm *qm)
3745 {
3746 struct pci_dev *pdev = qm->pdev;
3747 int ret;
3748
3749 pci_info(pdev, "Controller resetting...\n");
3750
3751 ret = qm_controller_reset_prepare(qm);
3752 if (ret)
3753 return ret;
3754
3755 ret = qm_soft_reset(qm);
3756 if (ret) {
3757 pci_err(pdev, "Controller reset failed (%d)\n", ret);
3758 return ret;
3759 }
3760
3761 ret = qm_controller_reset_done(qm);
3762 if (ret)
3763 return ret;
3764
3765 pci_info(pdev, "Controller reset complete\n");
3766
3767 return 0;
3768 }
3769
3770 /**
3771 * hisi_qm_dev_slot_reset() - slot reset
3772 * @pdev: the PCIe device
3773 *
3774 * This function offers QM relate PCIe device reset interface. Drivers which
3775 * use QM can use this function as slot_reset in its struct pci_error_handlers.
3776 */
3777 pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev)
3778 {
3779 struct hisi_qm *qm = pci_get_drvdata(pdev);
3780 int ret;
3781
3782 if (pdev->is_virtfn)
3783 return PCI_ERS_RESULT_RECOVERED;
3784
3785 pci_aer_clear_nonfatal_status(pdev);
3786
3787 /* reset pcie device controller */
3788 ret = qm_controller_reset(qm);
3789 if (ret) {
3790 pci_err(pdev, "Controller reset failed (%d)\n", ret);
3791 return PCI_ERS_RESULT_DISCONNECT;
3792 }
3793
3794 return PCI_ERS_RESULT_RECOVERED;
3795 }
3796 EXPORT_SYMBOL_GPL(hisi_qm_dev_slot_reset);
3797
3798 /* check the interrupt is ecc-mbit error or not */
3799 static int qm_check_dev_error(struct hisi_qm *qm)
3800 {
3801 int ret;
3802
3803 if (qm->fun_type == QM_HW_VF)
3804 return 0;
3805
3806 ret = qm_get_hw_error_status(qm) & QM_ECC_MBIT;
3807 if (ret)
3808 return ret;
3809
3810 return (qm_get_dev_err_status(qm) &
3811 qm->err_ini->err_info.ecc_2bits_mask);
3812 }
3813
3814 void hisi_qm_reset_prepare(struct pci_dev *pdev)
3815 {
3816 struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
3817 struct hisi_qm *qm = pci_get_drvdata(pdev);
3818 u32 delay = 0;
3819 int ret;
3820
3821 hisi_qm_dev_err_uninit(pf_qm);
3822
3823 /*
3824 * Check whether there is an ECC mbit error, If it occurs, need to
3825 * wait for soft reset to fix it.
3826 */
3827 while (qm_check_dev_error(pf_qm)) {
3828 msleep(++delay);
3829 if (delay > QM_RESET_WAIT_TIMEOUT)
3830 return;
3831 }
3832
3833 ret = qm_reset_prepare_ready(qm);
3834 if (ret) {
3835 pci_err(pdev, "FLR not ready!\n");
3836 return;
3837 }
3838
3839 if (qm->vfs_num) {
3840 ret = qm_vf_reset_prepare(qm, QM_FLR);
3841 if (ret) {
3842 pci_err(pdev, "Failed to prepare reset, ret = %d.\n",
3843 ret);
3844 return;
3845 }
3846 }
3847
3848 ret = hisi_qm_stop(qm, QM_FLR);
3849 if (ret) {
3850 pci_err(pdev, "Failed to stop QM, ret = %d.\n", ret);
3851 return;
3852 }
3853
3854 pci_info(pdev, "FLR resetting...\n");
3855 }
3856 EXPORT_SYMBOL_GPL(hisi_qm_reset_prepare);
3857
3858 static bool qm_flr_reset_complete(struct pci_dev *pdev)
3859 {
3860 struct pci_dev *pf_pdev = pci_physfn(pdev);
3861 struct hisi_qm *qm = pci_get_drvdata(pf_pdev);
3862 u32 id;
3863
3864 pci_read_config_dword(qm->pdev, PCI_COMMAND, &id);
3865 if (id == QM_PCI_COMMAND_INVALID) {
3866 pci_err(pdev, "Device can not be used!\n");
3867 return false;
3868 }
3869
3870 clear_bit(QM_DEV_RESET_FLAG, &qm->reset_flag);
3871
3872 return true;
3873 }
3874
3875 void hisi_qm_reset_done(struct pci_dev *pdev)
3876 {
3877 struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
3878 struct hisi_qm *qm = pci_get_drvdata(pdev);
3879 int ret;
3880
3881 hisi_qm_dev_err_init(pf_qm);
3882
3883 ret = qm_restart(qm);
3884 if (ret) {
3885 pci_err(pdev, "Failed to start QM, ret = %d.\n", ret);
3886 goto flr_done;
3887 }
3888
3889 if (qm->fun_type == QM_HW_PF) {
3890 ret = qm_dev_hw_init(qm);
3891 if (ret) {
3892 pci_err(pdev, "Failed to init PF, ret = %d.\n", ret);
3893 goto flr_done;
3894 }
3895
3896 if (!qm->vfs_num)
3897 goto flr_done;
3898
3899 ret = qm_vf_q_assign(qm, qm->vfs_num);
3900 if (ret) {
3901 pci_err(pdev, "Failed to assign VFs, ret = %d.\n", ret);
3902 goto flr_done;
3903 }
3904
3905 ret = qm_vf_reset_done(qm);
3906 if (ret) {
3907 pci_err(pdev, "Failed to start VFs, ret = %d.\n", ret);
3908 goto flr_done;
3909 }
3910 }
3911
3912 flr_done:
3913 if (qm_flr_reset_complete(pdev))
3914 pci_info(pdev, "FLR reset complete\n");
3915 }
3916 EXPORT_SYMBOL_GPL(hisi_qm_reset_done);
3917
3918 static irqreturn_t qm_abnormal_irq(int irq, void *data)
3919 {
3920 struct hisi_qm *qm = data;
3921 enum acc_err_result ret;
3922
3923 atomic64_inc(&qm->debug.dfx.abnormal_irq_cnt);
3924 ret = qm_process_dev_error(qm);
3925 if (ret == ACC_ERR_NEED_RESET)
3926 schedule_work(&qm->rst_work);
3927
3928 return IRQ_HANDLED;
3929 }
3930
3931 static int qm_irq_register(struct hisi_qm *qm)
3932 {
3933 struct pci_dev *pdev = qm->pdev;
3934 int ret;
3935
3936 ret = request_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR),
3937 qm_irq, IRQF_SHARED, qm->dev_name, qm);
3938 if (ret)
3939 return ret;
3940
3941 if (qm->ver != QM_HW_V1) {
3942 ret = request_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR),
3943 qm_aeq_irq, IRQF_SHARED, qm->dev_name, qm);
3944 if (ret)
3945 goto err_aeq_irq;
3946
3947 if (qm->fun_type == QM_HW_PF) {
3948 ret = request_irq(pci_irq_vector(pdev,
3949 QM_ABNORMAL_EVENT_IRQ_VECTOR),
3950 qm_abnormal_irq, IRQF_SHARED,
3951 qm->dev_name, qm);
3952 if (ret)
3953 goto err_abonormal_irq;
3954 }
3955 }
3956
3957 return 0;
3958
3959 err_abonormal_irq:
3960 free_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), qm);
3961 err_aeq_irq:
3962 free_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), qm);
3963 return ret;
3964 }
3965
3966 /**
3967 * hisi_qm_dev_shutdown() - Shutdown device.
3968 * @pdev: The device will be shutdown.
3969 *
3970 * This function will stop qm when OS shutdown or rebooting.
3971 */
3972 void hisi_qm_dev_shutdown(struct pci_dev *pdev)
3973 {
3974 struct hisi_qm *qm = pci_get_drvdata(pdev);
3975 int ret;
3976
3977 ret = hisi_qm_stop(qm, QM_NORMAL);
3978 if (ret)
3979 dev_err(&pdev->dev, "Fail to stop qm in shutdown!\n");
3980 }
3981 EXPORT_SYMBOL_GPL(hisi_qm_dev_shutdown);
3982
3983 static void hisi_qm_controller_reset(struct work_struct *rst_work)
3984 {
3985 struct hisi_qm *qm = container_of(rst_work, struct hisi_qm, rst_work);
3986 int ret;
3987
3988 /* reset pcie device controller */
3989 ret = qm_controller_reset(qm);
3990 if (ret)
3991 dev_err(&qm->pdev->dev, "controller reset failed (%d)\n", ret);
3992
3993 }
3994
3995 /**
3996 * hisi_qm_alg_register() - Register alg to crypto and add qm to qm_list.
3997 * @qm: The qm needs add.
3998 * @qm_list: The qm list.
3999 *
4000 * This function adds qm to qm list, and will register algorithm to
4001 * crypto when the qm list is empty.
4002 */
4003 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
4004 {
4005 int flag = 0;
4006 int ret = 0;
4007
4008 mutex_lock(&qm_list->lock);
4009 if (list_empty(&qm_list->list))
4010 flag = 1;
4011 list_add_tail(&qm->list, &qm_list->list);
4012 mutex_unlock(&qm_list->lock);
4013
4014 if (flag) {
4015 ret = qm_list->register_to_crypto();
4016 if (ret) {
4017 mutex_lock(&qm_list->lock);
4018 list_del(&qm->list);
4019 mutex_unlock(&qm_list->lock);
4020 }
4021 }
4022
4023 return ret;
4024 }
4025 EXPORT_SYMBOL_GPL(hisi_qm_alg_register);
4026
4027 /**
4028 * hisi_qm_alg_unregister() - Unregister alg from crypto and delete qm from
4029 * qm list.
4030 * @qm: The qm needs delete.
4031 * @qm_list: The qm list.
4032 *
4033 * This function deletes qm from qm list, and will unregister algorithm
4034 * from crypto when the qm list is empty.
4035 */
4036 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
4037 {
4038 mutex_lock(&qm_list->lock);
4039 list_del(&qm->list);
4040 mutex_unlock(&qm_list->lock);
4041
4042 if (list_empty(&qm_list->list))
4043 qm_list->unregister_from_crypto();
4044 }
4045 EXPORT_SYMBOL_GPL(hisi_qm_alg_unregister);
4046
4047 static int hisi_qm_pci_init(struct hisi_qm *qm)
4048 {
4049 struct pci_dev *pdev = qm->pdev;
4050 struct device *dev = &pdev->dev;
4051 unsigned int num_vec;
4052 int ret;
4053
4054 ret = pci_enable_device_mem(pdev);
4055 if (ret < 0) {
4056 dev_err(dev, "Failed to enable device mem!\n");
4057 return ret;
4058 }
4059
4060 ret = pci_request_mem_regions(pdev, qm->dev_name);
4061 if (ret < 0) {
4062 dev_err(dev, "Failed to request mem regions!\n");
4063 goto err_disable_pcidev;
4064 }
4065
4066 qm->phys_base = pci_resource_start(pdev, PCI_BAR_2);
4067 qm->phys_size = pci_resource_len(qm->pdev, PCI_BAR_2);
4068 qm->io_base = ioremap(qm->phys_base, qm->phys_size);
4069 if (!qm->io_base) {
4070 ret = -EIO;
4071 goto err_release_mem_regions;
4072 }
4073
4074 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
4075 if (ret < 0)
4076 goto err_iounmap;
4077 pci_set_master(pdev);
4078
4079 if (!qm->ops->get_irq_num) {
4080 ret = -EOPNOTSUPP;
4081 goto err_iounmap;
4082 }
4083 num_vec = qm->ops->get_irq_num(qm);
4084 ret = pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSI);
4085 if (ret < 0) {
4086 dev_err(dev, "Failed to enable MSI vectors!\n");
4087 goto err_iounmap;
4088 }
4089
4090 return 0;
4091
4092 err_iounmap:
4093 iounmap(qm->io_base);
4094 err_release_mem_regions:
4095 pci_release_mem_regions(pdev);
4096 err_disable_pcidev:
4097 pci_disable_device(pdev);
4098 return ret;
4099 }
4100
4101 /**
4102 * hisi_qm_init() - Initialize configures about qm.
4103 * @qm: The qm needing init.
4104 *
4105 * This function init qm, then we can call hisi_qm_start to put qm into work.
4106 */
4107 int hisi_qm_init(struct hisi_qm *qm)
4108 {
4109 struct pci_dev *pdev = qm->pdev;
4110 struct device *dev = &pdev->dev;
4111 int ret;
4112
4113 hisi_qm_pre_init(qm);
4114
4115 ret = qm_alloc_uacce(qm);
4116 if (ret < 0)
4117 dev_warn(dev, "fail to alloc uacce (%d)\n", ret);
4118
4119 ret = hisi_qm_pci_init(qm);
4120 if (ret)
4121 goto err_remove_uacce;
4122
4123 ret = qm_irq_register(qm);
4124 if (ret)
4125 goto err_pci_uninit;
4126
4127 if (qm->fun_type == QM_HW_VF && qm->ver != QM_HW_V1) {
4128 /* v2 starts to support get vft by mailbox */
4129 ret = hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
4130 if (ret)
4131 goto err_irq_unregister;
4132 }
4133
4134 ret = hisi_qm_memory_init(qm);
4135 if (ret)
4136 goto err_irq_unregister;
4137
4138 INIT_WORK(&qm->work, qm_work_process);
4139 if (qm->fun_type == QM_HW_PF)
4140 INIT_WORK(&qm->rst_work, hisi_qm_controller_reset);
4141
4142 atomic_set(&qm->status.flags, QM_INIT);
4143
4144 return 0;
4145
4146 err_irq_unregister:
4147 qm_irq_unregister(qm);
4148 err_pci_uninit:
4149 hisi_qm_pci_uninit(qm);
4150 err_remove_uacce:
4151 uacce_remove(qm->uacce);
4152 qm->uacce = NULL;
4153 return ret;
4154 }
4155 EXPORT_SYMBOL_GPL(hisi_qm_init);
4156
4157 MODULE_LICENSE("GPL v2");
4158 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
4159 MODULE_DESCRIPTION("HiSilicon Accelerator queue manager driver");
Linux with added FPC-III support