drivers/edac/amd64_edac.h

   1 /*
   2  * AMD64 class Memory Controller kernel module
   3  *
   4  * Copyright (c) 2009 SoftwareBitMaker.
   5  * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
   6  *
   7  * This file may be distributed under the terms of the
   8  * GNU General Public License.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/ctype.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/pci_ids.h>
  16 #include <linux/slab.h>
  17 #include <linux/mmzone.h>
  18 #include <linux/edac.h>
  19 #include <asm/cpu_device_id.h>
  20 #include <asm/msr.h>
  21 #include "edac_module.h"
  22 #include "mce_amd.h"
  23
  24 #define amd64_info(fmt, arg...) \
  25         edac_printk(KERN_INFO, "amd64", fmt, ##arg)
  26
  27 #define amd64_warn(fmt, arg...) \
  28         edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)
  29
  30 #define amd64_err(fmt, arg...) \
  31         edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)
  32
  33 #define amd64_mc_warn(mci, fmt, arg...) \
  34         edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
  35
  36 #define amd64_mc_err(mci, fmt, arg...) \
  37         edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
  38
  39 /*
  40  * Throughout the comments in this code, the following terms are used:
  41  *
  42  *      SysAddr, DramAddr, and InputAddr
  43  *
  44  *  These terms come directly from the amd64 documentation
  45  * (AMD publication #26094).  They are defined as follows:
  46  *
  47  *     SysAddr:
  48  *         This is a physical address generated by a CPU core or a device
  49  *         doing DMA.  If generated by a CPU core, a SysAddr is the result of
  50  *         a virtual to physical address translation by the CPU core's address
  51  *         translation mechanism (MMU).
  52  *
  53  *     DramAddr:
  54  *         A DramAddr is derived from a SysAddr by subtracting an offset that
  55  *         depends on which node the SysAddr maps to and whether the SysAddr
  56  *         is within a range affected by memory hoisting.  The DRAM Base
  57  *         (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
  58  *         determine which node a SysAddr maps to.
  59  *
  60  *         If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
  61  *         is within the range of addresses specified by this register, then
  62  *         a value x from the DHAR is subtracted from the SysAddr to produce a
  63  *         DramAddr.  Here, x represents the base address for the node that
  64  *         the SysAddr maps to plus an offset due to memory hoisting.  See
  65  *         section 3.4.8 and the comments in amd64_get_dram_hole_info() and
  66  *         sys_addr_to_dram_addr() below for more information.
  67  *
  68  *         If the SysAddr is not affected by the DHAR then a value y is
  69  *         subtracted from the SysAddr to produce a DramAddr.  Here, y is the
  70  *         base address for the node that the SysAddr maps to.  See section
  71  *         3.4.4 and the comments in sys_addr_to_dram_addr() below for more
  72  *         information.
  73  *
  74  *     InputAddr:
  75  *         A DramAddr is translated to an InputAddr before being passed to the
  76  *         memory controller for the node that the DramAddr is associated
  77  *         with.  The memory controller then maps the InputAddr to a csrow.
  78  *         If node interleaving is not in use, then the InputAddr has the same
  79  *         value as the DramAddr.  Otherwise, the InputAddr is produced by
  80  *         discarding the bits used for node interleaving from the DramAddr.
  81  *         See section 3.4.4 for more information.
  82  *
  83  *         The memory controller for a given node uses its DRAM CS Base and
  84  *         DRAM CS Mask registers to map an InputAddr to a csrow.  See
  85  *         sections 3.5.4 and 3.5.5 for more information.
  86  */
  87
  88 #define EDAC_AMD64_VERSION              "3.5.0"
  89 #define EDAC_MOD_STR                    "amd64_edac"
  90
  91 /* Extended Model from CPUID, for CPU Revision numbers */
  92 #define K8_REV_D                        1
  93 #define K8_REV_E                        2
  94 #define K8_REV_F                        4
  95
  96 /* Hardware limit on ChipSelect rows per MC and processors per system */
  97 #define NUM_CHIPSELECTS                 8
  98 #define DRAM_RANGES                     8
  99 #define NUM_CONTROLLERS                 8
 100
 101 #define ON true
 102 #define OFF false
 103
 104 /*
 105  * PCI-defined configuration space registers
 106  */
 107 #define PCI_DEVICE_ID_AMD_15H_NB_F1     0x1601
 108 #define PCI_DEVICE_ID_AMD_15H_NB_F2     0x1602
 109 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
 110 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
 111 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
 112 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
 113 #define PCI_DEVICE_ID_AMD_16H_NB_F1     0x1531
 114 #define PCI_DEVICE_ID_AMD_16H_NB_F2     0x1532
 115 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
 116 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
 117 #define PCI_DEVICE_ID_AMD_17H_DF_F0     0x1460
 118 #define PCI_DEVICE_ID_AMD_17H_DF_F6     0x1466
 119 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
 120 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
 121 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
 122 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496
 123 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F0 0x1448
 124 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F6 0x144e
 125 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440
 126 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446
 127 #define PCI_DEVICE_ID_AMD_19H_DF_F0     0x1650
 128 #define PCI_DEVICE_ID_AMD_19H_DF_F6     0x1656
 129
 130 /*
 131  * Function 1 - Address Map
 132  */
 133 #define DRAM_BASE_LO                    0x40
 134 #define DRAM_LIMIT_LO                   0x44
 135
 136 /*
 137  * F15 M30h D18F1x2[1C:00]
 138  */
 139 #define DRAM_CONT_BASE                  0x200
 140 #define DRAM_CONT_LIMIT                 0x204
 141
 142 /*
 143  * F15 M30h D18F1x2[4C:40]
 144  */
 145 #define DRAM_CONT_HIGH_OFF              0x240
 146
 147 #define dram_rw(pvt, i)                 ((u8)(pvt->ranges[i].base.lo & 0x3))
 148 #define dram_intlv_sel(pvt, i)          ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
 149 #define dram_dst_node(pvt, i)           ((u8)(pvt->ranges[i].lim.lo & 0x7))
 150
 151 #define DHAR                            0xf0
 152 #define dhar_mem_hoist_valid(pvt)       ((pvt)->dhar & BIT(1))
 153 #define dhar_base(pvt)                  ((pvt)->dhar & 0xff000000)
 154 #define k8_dhar_offset(pvt)             (((pvt)->dhar & 0x0000ff00) << 16)
 155
 156                                         /* NOTE: Extra mask bit vs K8 */
 157 #define f10_dhar_offset(pvt)            (((pvt)->dhar & 0x0000ff80) << 16)
 158
 159 #define DCT_CFG_SEL                     0x10C
 160
 161 #define DRAM_LOCAL_NODE_BASE            0x120
 162 #define DRAM_LOCAL_NODE_LIM             0x124
 163
 164 #define DRAM_BASE_HI                    0x140
 165 #define DRAM_LIMIT_HI                   0x144
 166
 167
 168 /*
 169  * Function 2 - DRAM controller
 170  */
 171 #define DCSB0                           0x40
 172 #define DCSB1                           0x140
 173 #define DCSB_CS_ENABLE                  BIT(0)
 174
 175 #define DCSM0                           0x60
 176 #define DCSM1                           0x160
 177
 178 #define csrow_enabled(i, dct, pvt)      ((pvt)->csels[(dct)].csbases[(i)]     & DCSB_CS_ENABLE)
 179 #define csrow_sec_enabled(i, dct, pvt)  ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
 180
 181 #define DRAM_CONTROL                    0x78
 182
 183 #define DBAM0                           0x80
 184 #define DBAM1                           0x180
 185
 186 /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
 187 #define DBAM_DIMM(i, reg)               ((((reg) >> (4*(i)))) & 0xF)
 188
 189 #define DBAM_MAX_VALUE                  11
 190
 191 #define DCLR0                           0x90
 192 #define DCLR1                           0x190
 193 #define REVE_WIDTH_128                  BIT(16)
 194 #define WIDTH_128                       BIT(11)
 195
 196 #define DCHR0                           0x94
 197 #define DCHR1                           0x194
 198 #define DDR3_MODE                       BIT(8)
 199
 200 #define DCT_SEL_LO                      0x110
 201 #define dct_high_range_enabled(pvt)     ((pvt)->dct_sel_lo & BIT(0))
 202 #define dct_interleave_enabled(pvt)     ((pvt)->dct_sel_lo & BIT(2))
 203
 204 #define dct_ganging_enabled(pvt)        ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
 205
 206 #define dct_data_intlv_enabled(pvt)     ((pvt)->dct_sel_lo & BIT(5))
 207 #define dct_memory_cleared(pvt)         ((pvt)->dct_sel_lo & BIT(10))
 208
 209 #define SWAP_INTLV_REG                  0x10c
 210
 211 #define DCT_SEL_HI                      0x114
 212
 213 #define F15H_M60H_SCRCTRL               0x1C8
 214 #define F17H_SCR_BASE_ADDR              0x48
 215 #define F17H_SCR_LIMIT_ADDR             0x4C
 216
 217 /*
 218  * Function 3 - Misc Control
 219  */
 220 #define NBCTL                           0x40
 221
 222 #define NBCFG                           0x44
 223 #define NBCFG_CHIPKILL                  BIT(23)
 224 #define NBCFG_ECC_ENABLE                BIT(22)
 225
 226 /* F3x48: NBSL */
 227 #define F10_NBSL_EXT_ERR_ECC            0x8
 228 #define NBSL_PP_OBS                     0x2
 229
 230 #define SCRCTRL                         0x58
 231
 232 #define F10_ONLINE_SPARE                0xB0
 233 #define online_spare_swap_done(pvt, c)  (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
 234 #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
 235
 236 #define F10_NB_ARRAY_ADDR               0xB8
 237 #define F10_NB_ARRAY_DRAM               BIT(31)
 238
 239 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline  */
 240 #define SET_NB_ARRAY_ADDR(section)      (((section) & 0x3) << 1)
 241
 242 #define F10_NB_ARRAY_DATA               0xBC
 243 #define F10_NB_ARR_ECC_WR_REQ           BIT(17)
 244 #define SET_NB_DRAM_INJECTION_WRITE(inj)  \
 245                                         (BIT(((inj.word) & 0xF) + 20) | \
 246                                         F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
 247 #define SET_NB_DRAM_INJECTION_READ(inj)  \
 248                                         (BIT(((inj.word) & 0xF) + 20) | \
 249                                         BIT(16) |  inj.bit_map)
 250
 251
 252 #define NBCAP                           0xE8
 253 #define NBCAP_CHIPKILL                  BIT(4)
 254 #define NBCAP_SECDED                    BIT(3)
 255 #define NBCAP_DCT_DUAL                  BIT(0)
 256
 257 #define EXT_NB_MCA_CFG                  0x180
 258
 259 /* MSRs */
 260 #define MSR_MCGCTL_NBE                  BIT(4)
 261
 262 /* F17h */
 263
 264 /* F0: */
 265 #define DF_DHAR                         0x104
 266
 267 /* UMC CH register offsets */
 268 #define UMCCH_BASE_ADDR                 0x0
 269 #define UMCCH_BASE_ADDR_SEC             0x10
 270 #define UMCCH_ADDR_MASK                 0x20
 271 #define UMCCH_ADDR_MASK_SEC             0x28
 272 #define UMCCH_ADDR_CFG                  0x30
 273 #define UMCCH_DIMM_CFG                  0x80
 274 #define UMCCH_UMC_CFG                   0x100
 275 #define UMCCH_SDP_CTRL                  0x104
 276 #define UMCCH_ECC_CTRL                  0x14C
 277 #define UMCCH_ECC_BAD_SYMBOL            0xD90
 278 #define UMCCH_UMC_CAP                   0xDF0
 279 #define UMCCH_UMC_CAP_HI                0xDF4
 280
 281 /* UMC CH bitfields */
 282 #define UMC_ECC_CHIPKILL_CAP            BIT(31)
 283 #define UMC_ECC_ENABLED                 BIT(30)
 284
 285 #define UMC_SDP_INIT                    BIT(31)
 286
 287 enum amd_families {
 288         K8_CPUS = 0,
 289         F10_CPUS,
 290         F15_CPUS,
 291         F15_M30H_CPUS,
 292         F15_M60H_CPUS,
 293         F16_CPUS,
 294         F16_M30H_CPUS,
 295         F17_CPUS,
 296         F17_M10H_CPUS,
 297         F17_M30H_CPUS,
 298         F17_M60H_CPUS,
 299         F17_M70H_CPUS,
 300         F19_CPUS,
 301         NUM_FAMILIES,
 302 };
 303
 304 /* Error injection control structure */
 305 struct error_injection {
 306         u32      section;
 307         u32      word;
 308         u32      bit_map;
 309 };
 310
 311 /* low and high part of PCI config space regs */
 312 struct reg_pair {
 313         u32 lo, hi;
 314 };
 315
 316 /*
 317  * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
 318  */
 319 struct dram_range {
 320         struct reg_pair base;
 321         struct reg_pair lim;
 322 };
 323
 324 /* A DCT chip selects collection */
 325 struct chip_select {
 326         u32 csbases[NUM_CHIPSELECTS];
 327         u32 csbases_sec[NUM_CHIPSELECTS];
 328         u8 b_cnt;
 329
 330         u32 csmasks[NUM_CHIPSELECTS];
 331         u32 csmasks_sec[NUM_CHIPSELECTS];
 332         u8 m_cnt;
 333 };
 334
 335 struct amd64_umc {
 336         u32 dimm_cfg;           /* DIMM Configuration reg */
 337         u32 umc_cfg;            /* Configuration reg */
 338         u32 sdp_ctrl;           /* SDP Control reg */
 339         u32 ecc_ctrl;           /* DRAM ECC Control reg */
 340         u32 umc_cap_hi;         /* Capabilities High reg */
 341 };
 342
 343 struct amd64_pvt {
 344         struct low_ops *ops;
 345
 346         /* pci_device handles which we utilize */
 347         struct pci_dev *F0, *F1, *F2, *F3, *F6;
 348
 349         u16 mc_node_id;         /* MC index of this MC node */
 350         u8 fam;                 /* CPU family */
 351         u8 model;               /* ... model */
 352         u8 stepping;            /* ... stepping */
 353
 354         int ext_model;          /* extended model value of this node */
 355         int channel_count;
 356
 357         /* Raw registers */
 358         u32 dclr0;              /* DRAM Configuration Low DCT0 reg */
 359         u32 dclr1;              /* DRAM Configuration Low DCT1 reg */
 360         u32 dchr0;              /* DRAM Configuration High DCT0 reg */
 361         u32 dchr1;              /* DRAM Configuration High DCT1 reg */
 362         u32 nbcap;              /* North Bridge Capabilities */
 363         u32 nbcfg;              /* F10 North Bridge Configuration */
 364         u32 ext_nbcfg;          /* Extended F10 North Bridge Configuration */
 365         u32 dhar;               /* DRAM Hoist reg */
 366         u32 dbam0;              /* DRAM Base Address Mapping reg for DCT0 */
 367         u32 dbam1;              /* DRAM Base Address Mapping reg for DCT1 */
 368
 369         /* one for each DCT/UMC */
 370         struct chip_select csels[NUM_CONTROLLERS];
 371
 372         /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
 373         struct dram_range ranges[DRAM_RANGES];
 374
 375         u64 top_mem;            /* top of memory below 4GB */
 376         u64 top_mem2;           /* top of memory above 4GB */
 377
 378         u32 dct_sel_lo;         /* DRAM Controller Select Low */
 379         u32 dct_sel_hi;         /* DRAM Controller Select High */
 380         u32 online_spare;       /* On-Line spare Reg */
 381
 382         /* x4, x8, or x16 syndromes in use */
 383         u8 ecc_sym_sz;
 384
 385         /* place to store error injection parameters prior to issue */
 386         struct error_injection injection;
 387
 388         /* cache the dram_type */
 389         enum mem_type dram_type;
 390
 391         struct amd64_umc *umc;  /* UMC registers */
 392 };
 393
 394 enum err_codes {
 395         DECODE_OK       =  0,
 396         ERR_NODE        = -1,
 397         ERR_CSROW       = -2,
 398         ERR_CHANNEL     = -3,
 399         ERR_SYND        = -4,
 400         ERR_NORM_ADDR   = -5,
 401 };
 402
 403 struct err_info {
 404         int err_code;
 405         struct mem_ctl_info *src_mci;
 406         int csrow;
 407         int channel;
 408         u16 syndrome;
 409         u32 page;
 410         u32 offset;
 411 };
 412
 413 static inline u32 get_umc_base(u8 channel)
 414 {
 415         /* chY: 0xY50000 */
 416         return 0x50000 + (channel << 20);
 417 }
 418
 419 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
 420 {
 421         u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
 422
 423         if (boot_cpu_data.x86 == 0xf)
 424                 return addr;
 425
 426         return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
 427 }
 428
 429 static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
 430 {
 431         u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
 432
 433         if (boot_cpu_data.x86 == 0xf)
 434                 return lim;
 435
 436         return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
 437 }
 438
 439 static inline u16 extract_syndrome(u64 status)
 440 {
 441         return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
 442 }
 443
 444 static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
 445 {
 446         if (pvt->fam == 0x15 && pvt->model >= 0x30)
 447                 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
 448                         ((pvt->dct_sel_lo >> 6) & 0x3);
 449
 450         return  ((pvt)->dct_sel_lo >> 6) & 0x3;
 451 }
 452 /*
 453  * per-node ECC settings descriptor
 454  */
 455 struct ecc_settings {
 456         u32 old_nbctl;
 457         bool nbctl_valid;
 458
 459         struct flags {
 460                 unsigned long nb_mce_enable:1;
 461                 unsigned long nb_ecc_prev:1;
 462         } flags;
 463 };
 464
 465 #ifdef CONFIG_EDAC_DEBUG
 466 extern const struct attribute_group amd64_edac_dbg_group;
 467 #endif
 468
 469 #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
 470 extern const struct attribute_group amd64_edac_inj_group;
 471 #endif
 472
 473 /*
 474  * Each of the PCI Device IDs types have their own set of hardware accessor
 475  * functions and per device encoding/decoding logic.
 476  */
 477 struct low_ops {
 478         int (*early_channel_count)      (struct amd64_pvt *pvt);
 479         void (*map_sysaddr_to_csrow)    (struct mem_ctl_info *mci, u64 sys_addr,
 480                                          struct err_info *);
 481         int (*dbam_to_cs)               (struct amd64_pvt *pvt, u8 dct,
 482                                          unsigned cs_mode, int cs_mask_nr);
 483 };
 484
 485 struct amd64_family_type {
 486         const char *ctl_name;
 487         u16 f0_id, f1_id, f2_id, f6_id;
 488         /* Maximum number of memory controllers per die/node. */
 489         u8 max_mcs;
 490         struct low_ops ops;
 491 };
 492
 493 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
 494                                u32 *val, const char *func);
 495 int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
 496                                 u32 val, const char *func);
 497
 498 #define amd64_read_pci_cfg(pdev, offset, val)   \
 499         __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
 500
 501 #define amd64_write_pci_cfg(pdev, offset, val)  \
 502         __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
 503
 504 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
 505                              u64 *hole_offset, u64 *hole_size);
 506
 507 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
 508
 509 /* Injection helpers */
 510 static inline void disable_caches(void *dummy)
 511 {
 512         write_cr0(read_cr0() | X86_CR0_CD);
 513         wbinvd();
 514 }
 515
 516 static inline void enable_caches(void *dummy)
 517 {
 518         write_cr0(read_cr0() & ~X86_CR0_CD);
 519 }
 520
 521 static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
 522 {
 523         if (pvt->fam == 0x15 && pvt->model >= 0x30) {
 524                 u32 tmp;
 525                 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
 526                 return (u8) tmp & 0xF;
 527         }
 528         return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
 529 }
 530
 531 static inline u8 dhar_valid(struct amd64_pvt *pvt)
 532 {
 533         if (pvt->fam == 0x15 && pvt->model >= 0x30) {
 534                 u32 tmp;
 535                 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
 536                 return (tmp >> 1) & BIT(0);
 537         }
 538         return (pvt)->dhar & BIT(0);
 539 }
 540
 541 static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
 542 {
 543         if (pvt->fam == 0x15 && pvt->model >= 0x30) {
 544                 u32 tmp;
 545                 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
 546                 return (tmp >> 11) & 0x1FFF;
 547         }
 548         return (pvt)->dct_sel_lo & 0xFFFFF800;
 549 }