drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef F32_MES_PM4_PACKETS_H
  25 #define F32_MES_PM4_PACKETS_H
  26
  27 #ifndef PM4_MES_HEADER_DEFINED
  28 #define PM4_MES_HEADER_DEFINED
  29 union PM4_MES_TYPE_3_HEADER {
  30         struct {
  31                 uint32_t reserved1 : 8; /* < reserved */
  32                 uint32_t opcode    : 8; /* < IT opcode */
  33                 uint32_t count     : 14;/* < Number of DWORDS - 1 in the
  34                                          *   information body
  35                                          */
  36                 uint32_t type      : 2; /* < packet identifier
  37                                          *   It should be 3 for type 3 packets
  38                                          */
  39         };
  40         uint32_t u32All;
  41 };
  42 #endif /* PM4_MES_HEADER_DEFINED */
  43
  44 /*--------------------MES_SET_RESOURCES--------------------*/
  45
  46 #ifndef PM4_MES_SET_RESOURCES_DEFINED
  47 #define PM4_MES_SET_RESOURCES_DEFINED
  48 enum mes_set_resources_queue_type_enum {
  49         queue_type__mes_set_resources__kernel_interface_queue_kiq = 0,
  50         queue_type__mes_set_resources__hsa_interface_queue_hiq = 1,
  51         queue_type__mes_set_resources__hsa_debug_interface_queue = 4
  52 };
  53
  54
  55 struct pm4_mes_set_resources {
  56         union {
  57                 union PM4_MES_TYPE_3_HEADER     header;         /* header */
  58                 uint32_t                        ordinal1;
  59         };
  60
  61         union {
  62                 struct {
  63                         uint32_t vmid_mask:16;
  64                         uint32_t unmap_latency:8;
  65                         uint32_t reserved1:5;
  66                         enum mes_set_resources_queue_type_enum queue_type:3;
  67                 } bitfields2;
  68                 uint32_t ordinal2;
  69         };
  70
  71         uint32_t queue_mask_lo;
  72         uint32_t queue_mask_hi;
  73         uint32_t gws_mask_lo;
  74         uint32_t gws_mask_hi;
  75
  76         union {
  77                 struct {
  78                         uint32_t oac_mask:16;
  79                         uint32_t reserved2:16;
  80                 } bitfields7;
  81                 uint32_t ordinal7;
  82         };
  83
  84         union {
  85                 struct {
  86                 uint32_t gds_heap_base:6;
  87                 uint32_t reserved3:5;
  88                 uint32_t gds_heap_size:6;
  89                 uint32_t reserved4:15;
  90                 } bitfields8;
  91                 uint32_t ordinal8;
  92         };
  93
  94 };
  95 #endif
  96
  97 /*--------------------MES_RUN_LIST--------------------*/
  98
  99 #ifndef PM4_MES_RUN_LIST_DEFINED
 100 #define PM4_MES_RUN_LIST_DEFINED
 101
 102 struct pm4_mes_runlist {
 103         union {
 104             union PM4_MES_TYPE_3_HEADER   header;            /* header */
 105             uint32_t            ordinal1;
 106         };
 107
 108         union {
 109                 struct {
 110                         uint32_t reserved1:2;
 111                         uint32_t ib_base_lo:30;
 112                 } bitfields2;
 113                 uint32_t ordinal2;
 114         };
 115
 116         union {
 117                 struct {
 118                         uint32_t ib_base_hi:16;
 119                         uint32_t reserved2:16;
 120                 } bitfields3;
 121                 uint32_t ordinal3;
 122         };
 123
 124         union {
 125                 struct {
 126                         uint32_t ib_size:20;
 127                         uint32_t chain:1;
 128                         uint32_t offload_polling:1;
 129                         uint32_t reserved2:1;
 130                         uint32_t valid:1;
 131                         uint32_t process_cnt:4;
 132                         uint32_t reserved3:4;
 133                 } bitfields4;
 134                 uint32_t ordinal4;
 135         };
 136
 137 };
 138 #endif
 139
 140 /*--------------------MES_MAP_PROCESS--------------------*/
 141
 142 #ifndef PM4_MES_MAP_PROCESS_DEFINED
 143 #define PM4_MES_MAP_PROCESS_DEFINED
 144
 145 struct pm4_mes_map_process {
 146         union {
 147                 union PM4_MES_TYPE_3_HEADER header;     /* header */
 148                 uint32_t ordinal1;
 149         };
 150
 151         union {
 152                 struct {
 153                         uint32_t pasid:16;
 154                         uint32_t reserved1:8;
 155                         uint32_t diq_enable:1;
 156                         uint32_t process_quantum:7;
 157                 } bitfields2;
 158                 uint32_t ordinal2;
 159         };
 160
 161         union {
 162                 struct {
 163                         uint32_t page_table_base:28;
 164                         uint32_t reserved3:4;
 165                 } bitfields3;
 166                 uint32_t ordinal3;
 167         };
 168
 169         uint32_t reserved;
 170
 171         uint32_t sh_mem_bases;
 172         uint32_t sh_mem_config;
 173         uint32_t sh_mem_ape1_base;
 174         uint32_t sh_mem_ape1_limit;
 175
 176         uint32_t sh_hidden_private_base_vmid;
 177
 178         uint32_t reserved2;
 179         uint32_t reserved3;
 180
 181         uint32_t gds_addr_lo;
 182         uint32_t gds_addr_hi;
 183
 184         union {
 185                 struct {
 186                         uint32_t num_gws:6;
 187                         uint32_t reserved4:2;
 188                         uint32_t num_oac:4;
 189                         uint32_t reserved5:4;
 190                         uint32_t gds_size:6;
 191                         uint32_t num_queues:10;
 192                 } bitfields10;
 193                 uint32_t ordinal10;
 194         };
 195
 196         uint32_t completion_signal_lo;
 197         uint32_t completion_signal_hi;
 198
 199 };
 200
 201 #endif
 202
 203 /*--------------------MES_MAP_QUEUES--------------------*/
 204
 205 #ifndef PM4_MES_MAP_QUEUES_VI_DEFINED
 206 #define PM4_MES_MAP_QUEUES_VI_DEFINED
 207 enum mes_map_queues_queue_sel_vi_enum {
 208         queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0,
 209 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1
 210 };
 211
 212 enum mes_map_queues_queue_type_vi_enum {
 213         queue_type__mes_map_queues__normal_compute_vi = 0,
 214         queue_type__mes_map_queues__debug_interface_queue_vi = 1,
 215         queue_type__mes_map_queues__normal_latency_static_queue_vi = 2,
 216 queue_type__mes_map_queues__low_latency_static_queue_vi = 3
 217 };
 218
 219 enum mes_map_queues_engine_sel_vi_enum {
 220         engine_sel__mes_map_queues__compute_vi = 0,
 221         engine_sel__mes_map_queues__sdma0_vi = 2,
 222         engine_sel__mes_map_queues__sdma1_vi = 3
 223 };
 224
 225
 226 struct pm4_mes_map_queues {
 227         union {
 228                 union PM4_MES_TYPE_3_HEADER   header;            /* header */
 229                 uint32_t            ordinal1;
 230         };
 231
 232         union {
 233                 struct {
 234                         uint32_t reserved1:4;
 235                         enum mes_map_queues_queue_sel_vi_enum queue_sel:2;
 236                         uint32_t reserved2:15;
 237                         enum mes_map_queues_queue_type_vi_enum queue_type:3;
 238                         uint32_t reserved3:2;
 239                         enum mes_map_queues_engine_sel_vi_enum engine_sel:3;
 240                         uint32_t num_queues:3;
 241                 } bitfields2;
 242                 uint32_t ordinal2;
 243         };
 244
 245         union {
 246                 struct {
 247                         uint32_t reserved3:1;
 248                         uint32_t check_disable:1;
 249                         uint32_t doorbell_offset:21;
 250                         uint32_t reserved4:3;
 251                         uint32_t queue:6;
 252                 } bitfields3;
 253                 uint32_t ordinal3;
 254         };
 255
 256         uint32_t mqd_addr_lo;
 257         uint32_t mqd_addr_hi;
 258         uint32_t wptr_addr_lo;
 259         uint32_t wptr_addr_hi;
 260 };
 261 #endif
 262
 263 /*--------------------MES_QUERY_STATUS--------------------*/
 264
 265 #ifndef PM4_MES_QUERY_STATUS_DEFINED
 266 #define PM4_MES_QUERY_STATUS_DEFINED
 267 enum mes_query_status_interrupt_sel_enum {
 268         interrupt_sel__mes_query_status__completion_status = 0,
 269         interrupt_sel__mes_query_status__process_status = 1,
 270         interrupt_sel__mes_query_status__queue_status = 2
 271 };
 272
 273 enum mes_query_status_command_enum {
 274         command__mes_query_status__interrupt_only = 0,
 275         command__mes_query_status__fence_only_immediate = 1,
 276         command__mes_query_status__fence_only_after_write_ack = 2,
 277         command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3
 278 };
 279
 280 enum mes_query_status_engine_sel_enum {
 281         engine_sel__mes_query_status__compute = 0,
 282         engine_sel__mes_query_status__sdma0_queue = 2,
 283         engine_sel__mes_query_status__sdma1_queue = 3
 284 };
 285
 286 struct pm4_mes_query_status {
 287         union {
 288                 union PM4_MES_TYPE_3_HEADER   header;            /* header */
 289                 uint32_t            ordinal1;
 290         };
 291
 292         union {
 293                 struct {
 294                         uint32_t context_id:28;
 295                         enum mes_query_status_interrupt_sel_enum
 296                                 interrupt_sel:2;
 297                         enum mes_query_status_command_enum command:2;
 298                 } bitfields2;
 299                 uint32_t ordinal2;
 300         };
 301
 302         union {
 303                 struct {
 304                         uint32_t pasid:16;
 305                         uint32_t reserved1:16;
 306                 } bitfields3a;
 307                 struct {
 308                         uint32_t reserved2:2;
 309                         uint32_t doorbell_offset:21;
 310                         uint32_t reserved3:2;
 311                         enum mes_query_status_engine_sel_enum engine_sel:3;
 312                         uint32_t reserved4:4;
 313                 } bitfields3b;
 314                 uint32_t ordinal3;
 315         };
 316
 317         uint32_t addr_lo;
 318         uint32_t addr_hi;
 319         uint32_t data_lo;
 320         uint32_t data_hi;
 321 };
 322 #endif
 323
 324 /*--------------------MES_UNMAP_QUEUES--------------------*/
 325
 326 #ifndef PM4_MES_UNMAP_QUEUES_DEFINED
 327 #define PM4_MES_UNMAP_QUEUES_DEFINED
 328 enum mes_unmap_queues_action_enum {
 329         action__mes_unmap_queues__preempt_queues = 0,
 330         action__mes_unmap_queues__reset_queues = 1,
 331         action__mes_unmap_queues__disable_process_queues = 2,
 332         action__mes_unmap_queues__reserved = 3
 333 };
 334
 335 enum mes_unmap_queues_queue_sel_enum {
 336         queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0,
 337         queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1,
 338         queue_sel__mes_unmap_queues__unmap_all_queues = 2,
 339         queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3
 340 };
 341
 342 enum mes_unmap_queues_engine_sel_enum {
 343         engine_sel__mes_unmap_queues__compute = 0,
 344         engine_sel__mes_unmap_queues__sdma0 = 2,
 345         engine_sel__mes_unmap_queues__sdmal = 3
 346 };
 347
 348 struct pm4_mes_unmap_queues {
 349         union {
 350                 union PM4_MES_TYPE_3_HEADER   header;            /* header */
 351                 uint32_t            ordinal1;
 352         };
 353
 354         union {
 355                 struct {
 356                         enum mes_unmap_queues_action_enum action:2;
 357                         uint32_t reserved1:2;
 358                         enum mes_unmap_queues_queue_sel_enum queue_sel:2;
 359                         uint32_t reserved2:20;
 360                         enum mes_unmap_queues_engine_sel_enum engine_sel:3;
 361                         uint32_t num_queues:3;
 362                 } bitfields2;
 363                 uint32_t ordinal2;
 364         };
 365
 366         union {
 367                 struct {
 368                         uint32_t pasid:16;
 369                         uint32_t reserved3:16;
 370                 } bitfields3a;
 371                 struct {
 372                         uint32_t reserved4:2;
 373                         uint32_t doorbell_offset0:21;
 374                         uint32_t reserved5:9;
 375                 } bitfields3b;
 376                 uint32_t ordinal3;
 377         };
 378
 379         union {
 380         struct {
 381                         uint32_t reserved6:2;
 382                         uint32_t doorbell_offset1:21;
 383                         uint32_t reserved7:9;
 384                 } bitfields4;
 385                 uint32_t ordinal4;
 386         };
 387
 388         union {
 389                 struct {
 390                         uint32_t reserved8:2;
 391                         uint32_t doorbell_offset2:21;
 392                         uint32_t reserved9:9;
 393                 } bitfields5;
 394                 uint32_t ordinal5;
 395         };
 396
 397         union {
 398                 struct {
 399                         uint32_t reserved10:2;
 400                         uint32_t doorbell_offset3:21;
 401                         uint32_t reserved11:9;
 402                 } bitfields6;
 403                 uint32_t ordinal6;
 404         };
 405 };
 406 #endif
 407
 408 #ifndef PM4_MEC_RELEASE_MEM_DEFINED
 409 #define PM4_MEC_RELEASE_MEM_DEFINED
 410 enum RELEASE_MEM_event_index_enum {
 411         event_index___release_mem__end_of_pipe = 5,
 412         event_index___release_mem__shader_done = 6
 413 };
 414
 415 enum RELEASE_MEM_cache_policy_enum {
 416         cache_policy___release_mem__lru = 0,
 417         cache_policy___release_mem__stream = 1,
 418         cache_policy___release_mem__bypass = 2
 419 };
 420
 421 enum RELEASE_MEM_dst_sel_enum {
 422         dst_sel___release_mem__memory_controller = 0,
 423         dst_sel___release_mem__tc_l2 = 1,
 424         dst_sel___release_mem__queue_write_pointer_register = 2,
 425         dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3
 426 };
 427
 428 enum RELEASE_MEM_int_sel_enum {
 429         int_sel___release_mem__none = 0,
 430         int_sel___release_mem__send_interrupt_only = 1,
 431         int_sel___release_mem__send_interrupt_after_write_confirm = 2,
 432         int_sel___release_mem__send_data_after_write_confirm = 3
 433 };
 434
 435 enum RELEASE_MEM_data_sel_enum {
 436         data_sel___release_mem__none = 0,
 437         data_sel___release_mem__send_32_bit_low = 1,
 438         data_sel___release_mem__send_64_bit_data = 2,
 439         data_sel___release_mem__send_gpu_clock_counter = 3,
 440         data_sel___release_mem__send_cp_perfcounter_hi_lo = 4,
 441         data_sel___release_mem__store_gds_data_to_memory = 5
 442 };
 443
 444 struct pm4_mec_release_mem {
 445         union {
 446                 union PM4_MES_TYPE_3_HEADER header;     /*header */
 447                 unsigned int ordinal1;
 448         };
 449
 450         union {
 451                 struct {
 452                         unsigned int event_type:6;
 453                         unsigned int reserved1:2;
 454                         enum RELEASE_MEM_event_index_enum event_index:4;
 455                         unsigned int tcl1_vol_action_ena:1;
 456                         unsigned int tc_vol_action_ena:1;
 457                         unsigned int reserved2:1;
 458                         unsigned int tc_wb_action_ena:1;
 459                         unsigned int tcl1_action_ena:1;
 460                         unsigned int tc_action_ena:1;
 461                         unsigned int reserved3:6;
 462                         unsigned int atc:1;
 463                         enum RELEASE_MEM_cache_policy_enum cache_policy:2;
 464                         unsigned int reserved4:5;
 465                 } bitfields2;
 466                 unsigned int ordinal2;
 467         };
 468
 469         union {
 470                 struct {
 471                         unsigned int reserved5:16;
 472                         enum RELEASE_MEM_dst_sel_enum dst_sel:2;
 473                         unsigned int reserved6:6;
 474                         enum RELEASE_MEM_int_sel_enum int_sel:3;
 475                         unsigned int reserved7:2;
 476                         enum RELEASE_MEM_data_sel_enum data_sel:3;
 477                 } bitfields3;
 478                 unsigned int ordinal3;
 479         };
 480
 481         union {
 482                 struct {
 483                         unsigned int reserved8:2;
 484                         unsigned int address_lo_32b:30;
 485                 } bitfields4;
 486                 struct {
 487                         unsigned int reserved9:3;
 488                         unsigned int address_lo_64b:29;
 489                 } bitfields5;
 490                 unsigned int ordinal4;
 491         };
 492
 493         unsigned int address_hi;
 494
 495         unsigned int data_lo;
 496
 497         unsigned int data_hi;
 498 };
 499 #endif
 500
 501 enum {
 502         CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
 503 };
 504
 505 #endif