drivers/gpu/drm/gma500/psb_irq.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /**************************************************************************
   3  * Copyright (c) 2007, Intel Corporation.
   4  * All Rights Reserved.
   5  *
   6  * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   7  * develop this driver.
   8  *
   9  **************************************************************************/
  10
  11 #include <drm/drm_vblank.h>
  12
  13 #include "mdfld_output.h"
  14 #include "power.h"
  15 #include "psb_drv.h"
  16 #include "psb_intel_reg.h"
  17 #include "psb_irq.h"
  18 #include "psb_reg.h"
  19
  20 /*
  21  * inline functions
  22  */
  23
  24 static inline u32
  25 psb_pipestat(int pipe)
  26 {
  27         if (pipe == 0)
  28                 return PIPEASTAT;
  29         if (pipe == 1)
  30                 return PIPEBSTAT;
  31         if (pipe == 2)
  32                 return PIPECSTAT;
  33         BUG();
  34 }
  35
  36 static inline u32
  37 mid_pipe_event(int pipe)
  38 {
  39         if (pipe == 0)
  40                 return _PSB_PIPEA_EVENT_FLAG;
  41         if (pipe == 1)
  42                 return _MDFLD_PIPEB_EVENT_FLAG;
  43         if (pipe == 2)
  44                 return _MDFLD_PIPEC_EVENT_FLAG;
  45         BUG();
  46 }
  47
  48 static inline u32
  49 mid_pipe_vsync(int pipe)
  50 {
  51         if (pipe == 0)
  52                 return _PSB_VSYNC_PIPEA_FLAG;
  53         if (pipe == 1)
  54                 return _PSB_VSYNC_PIPEB_FLAG;
  55         if (pipe == 2)
  56                 return _MDFLD_PIPEC_VBLANK_FLAG;
  57         BUG();
  58 }
  59
  60 static inline u32
  61 mid_pipeconf(int pipe)
  62 {
  63         if (pipe == 0)
  64                 return PIPEACONF;
  65         if (pipe == 1)
  66                 return PIPEBCONF;
  67         if (pipe == 2)
  68                 return PIPECCONF;
  69         BUG();
  70 }
  71
  72 void
  73 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
  74 {
  75         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  76                 u32 reg = psb_pipestat(pipe);
  77                 dev_priv->pipestat[pipe] |= mask;
  78                 /* Enable the interrupt, clear any pending status */
  79                 if (gma_power_begin(dev_priv->dev, false)) {
  80                         u32 writeVal = PSB_RVDC32(reg);
  81                         writeVal |= (mask | (mask >> 16));
  82                         PSB_WVDC32(writeVal, reg);
  83                         (void) PSB_RVDC32(reg);
  84                         gma_power_end(dev_priv->dev);
  85                 }
  86         }
  87 }
  88
  89 void
  90 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
  91 {
  92         if ((dev_priv->pipestat[pipe] & mask) != 0) {
  93                 u32 reg = psb_pipestat(pipe);
  94                 dev_priv->pipestat[pipe] &= ~mask;
  95                 if (gma_power_begin(dev_priv->dev, false)) {
  96                         u32 writeVal = PSB_RVDC32(reg);
  97                         writeVal &= ~mask;
  98                         PSB_WVDC32(writeVal, reg);
  99                         (void) PSB_RVDC32(reg);
 100                         gma_power_end(dev_priv->dev);
 101                 }
 102         }
 103 }
 104
 105 static void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 106 {
 107         if (gma_power_begin(dev_priv->dev, false)) {
 108                 u32 pipe_event = mid_pipe_event(pipe);
 109                 dev_priv->vdc_irq_mask |= pipe_event;
 110                 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 111                 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 112                 gma_power_end(dev_priv->dev);
 113         }
 114 }
 115
 116 static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 117 {
 118         if (dev_priv->pipestat[pipe] == 0) {
 119                 if (gma_power_begin(dev_priv->dev, false)) {
 120                         u32 pipe_event = mid_pipe_event(pipe);
 121                         dev_priv->vdc_irq_mask &= ~pipe_event;
 122                         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 123                         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 124                         gma_power_end(dev_priv->dev);
 125                 }
 126         }
 127 }
 128
 129 /**
 130  * Display controller interrupt handler for pipe event.
 131  *
 132  */
 133 static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
 134 {
 135         struct drm_psb_private *dev_priv =
 136             (struct drm_psb_private *) dev->dev_private;
 137
 138         uint32_t pipe_stat_val = 0;
 139         uint32_t pipe_stat_reg = psb_pipestat(pipe);
 140         uint32_t pipe_enable = dev_priv->pipestat[pipe];
 141         uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
 142         uint32_t pipe_clear;
 143         uint32_t i = 0;
 144
 145         spin_lock(&dev_priv->irqmask_lock);
 146
 147         pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
 148         pipe_stat_val &= pipe_enable | pipe_status;
 149         pipe_stat_val &= pipe_stat_val >> 16;
 150
 151         spin_unlock(&dev_priv->irqmask_lock);
 152
 153         /* Clear the 2nd level interrupt status bits
 154          * Sometimes the bits are very sticky so we repeat until they unstick */
 155         for (i = 0; i < 0xffff; i++) {
 156                 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
 157                 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
 158
 159                 if (pipe_clear == 0)
 160                         break;
 161         }
 162
 163         if (pipe_clear)
 164                 dev_err(dev->dev,
 165                 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
 166                 __func__, pipe, PSB_RVDC32(pipe_stat_reg));
 167
 168         if (pipe_stat_val & PIPE_VBLANK_STATUS ||
 169             (IS_MFLD(dev) && pipe_stat_val & PIPE_TE_STATUS)) {
 170                 struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);
 171                 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
 172                 unsigned long flags;
 173
 174                 drm_handle_vblank(dev, pipe);
 175
 176                 spin_lock_irqsave(&dev->event_lock, flags);
 177                 if (gma_crtc->page_flip_event) {
 178                         drm_crtc_send_vblank_event(crtc,
 179                                                    gma_crtc->page_flip_event);
 180                         gma_crtc->page_flip_event = NULL;
 181                         drm_crtc_vblank_put(crtc);
 182                 }
 183                 spin_unlock_irqrestore(&dev->event_lock, flags);
 184         }
 185 }
 186
 187 /*
 188  * Display controller interrupt handler.
 189  */
 190 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
 191 {
 192         if (vdc_stat & _PSB_IRQ_ASLE)
 193                 psb_intel_opregion_asle_intr(dev);
 194
 195         if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
 196                 mid_pipe_event_handler(dev, 0);
 197
 198         if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
 199                 mid_pipe_event_handler(dev, 1);
 200 }
 201
 202 /*
 203  * SGX interrupt handler
 204  */
 205 static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2)
 206 {
 207         struct drm_psb_private *dev_priv = dev->dev_private;
 208         u32 val, addr;
 209
 210         if (stat_1 & _PSB_CE_TWOD_COMPLETE)
 211                 val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
 212
 213         if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) {
 214                 val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
 215                 addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
 216                 if (val) {
 217                         if (val & _PSB_CBI_STAT_PF_N_RW)
 218                                 DRM_ERROR("SGX MMU page fault:");
 219                         else
 220                                 DRM_ERROR("SGX MMU read / write protection fault:");
 221
 222                         if (val & _PSB_CBI_STAT_FAULT_CACHE)
 223                                 DRM_ERROR("\tCache requestor");
 224                         if (val & _PSB_CBI_STAT_FAULT_TA)
 225                                 DRM_ERROR("\tTA requestor");
 226                         if (val & _PSB_CBI_STAT_FAULT_VDM)
 227                                 DRM_ERROR("\tVDM requestor");
 228                         if (val & _PSB_CBI_STAT_FAULT_2D)
 229                                 DRM_ERROR("\t2D requestor");
 230                         if (val & _PSB_CBI_STAT_FAULT_PBE)
 231                                 DRM_ERROR("\tPBE requestor");
 232                         if (val & _PSB_CBI_STAT_FAULT_TSP)
 233                                 DRM_ERROR("\tTSP requestor");
 234                         if (val & _PSB_CBI_STAT_FAULT_ISP)
 235                                 DRM_ERROR("\tISP requestor");
 236                         if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
 237                                 DRM_ERROR("\tUSSEPDS requestor");
 238                         if (val & _PSB_CBI_STAT_FAULT_HOST)
 239                                 DRM_ERROR("\tHost requestor");
 240
 241                         DRM_ERROR("\tMMU failing address is 0x%08x.\n",
 242                                   (unsigned int)addr);
 243                 }
 244         }
 245
 246         /* Clear bits */
 247         PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR);
 248         PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2);
 249         PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
 250 }
 251
 252 irqreturn_t psb_irq_handler(int irq, void *arg)
 253 {
 254         struct drm_device *dev = arg;
 255         struct drm_psb_private *dev_priv = dev->dev_private;
 256         uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
 257         u32 sgx_stat_1, sgx_stat_2;
 258         int handled = 0;
 259
 260         spin_lock(&dev_priv->irqmask_lock);
 261
 262         vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
 263
 264         if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE))
 265                 dsp_int = 1;
 266
 267         /* FIXME: Handle Medfield
 268         if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
 269                 dsp_int = 1;
 270         */
 271
 272         if (vdc_stat & _PSB_IRQ_SGX_FLAG)
 273                 sgx_int = 1;
 274         if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC)
 275                 hotplug_int = 1;
 276
 277         vdc_stat &= dev_priv->vdc_irq_mask;
 278         spin_unlock(&dev_priv->irqmask_lock);
 279
 280         if (dsp_int && gma_power_is_on(dev)) {
 281                 psb_vdc_interrupt(dev, vdc_stat);
 282                 handled = 1;
 283         }
 284
 285         if (sgx_int) {
 286                 sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
 287                 sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
 288                 psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2);
 289                 handled = 1;
 290         }
 291
 292         /* Note: this bit has other meanings on some devices, so we will
 293            need to address that later if it ever matters */
 294         if (hotplug_int && dev_priv->ops->hotplug) {
 295                 handled = dev_priv->ops->hotplug(dev);
 296                 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
 297         }
 298
 299         PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
 300         (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
 301         rmb();
 302
 303         if (!handled)
 304                 return IRQ_NONE;
 305
 306         return IRQ_HANDLED;
 307 }
 308
 309 void psb_irq_preinstall(struct drm_device *dev)
 310 {
 311         struct drm_psb_private *dev_priv =
 312             (struct drm_psb_private *) dev->dev_private;
 313         unsigned long irqflags;
 314
 315         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 316
 317         if (gma_power_is_on(dev)) {
 318                 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 319                 PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
 320                 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
 321                 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
 322                 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
 323         }
 324         if (dev->vblank[0].enabled)
 325                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
 326         if (dev->vblank[1].enabled)
 327                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
 328
 329         /* FIXME: Handle Medfield irq mask
 330         if (dev->vblank[1].enabled)
 331                 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
 332         if (dev->vblank[2].enabled)
 333                 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
 334         */
 335
 336         /* Revisit this area - want per device masks ? */
 337         if (dev_priv->ops->hotplug)
 338                 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
 339         dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;
 340
 341         /* This register is safe even if display island is off */
 342         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 343         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 344 }
 345
 346 int psb_irq_postinstall(struct drm_device *dev)
 347 {
 348         struct drm_psb_private *dev_priv = dev->dev_private;
 349         unsigned long irqflags;
 350         unsigned int i;
 351
 352         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 353
 354         /* Enable 2D and MMU fault interrupts */
 355         PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2);
 356         PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE);
 357         PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */
 358
 359         /* This register is safe even if display island is off */
 360         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 361         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 362
 363         for (i = 0; i < dev->num_crtcs; ++i) {
 364                 if (dev->vblank[i].enabled)
 365                         psb_enable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
 366                 else
 367                         psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
 368         }
 369
 370         if (dev_priv->ops->hotplug_enable)
 371                 dev_priv->ops->hotplug_enable(dev, true);
 372
 373         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 374         return 0;
 375 }
 376
 377 void psb_irq_uninstall(struct drm_device *dev)
 378 {
 379         struct drm_psb_private *dev_priv = dev->dev_private;
 380         unsigned long irqflags;
 381         unsigned int i;
 382
 383         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 384
 385         if (dev_priv->ops->hotplug_enable)
 386                 dev_priv->ops->hotplug_enable(dev, false);
 387
 388         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 389
 390         for (i = 0; i < dev->num_crtcs; ++i) {
 391                 if (dev->vblank[i].enabled)
 392                         psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
 393         }
 394
 395         dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
 396                                   _PSB_IRQ_MSVDX_FLAG |
 397                                   _LNC_IRQ_TOPAZ_FLAG;
 398
 399         /* These two registers are safe even if display island is off */
 400         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 401         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 402
 403         wmb();
 404
 405         /* This register is safe even if display island is off */
 406         PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
 407         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 408 }
 409
 410 void psb_irq_turn_on_dpst(struct drm_device *dev)
 411 {
 412         struct drm_psb_private *dev_priv =
 413                 (struct drm_psb_private *) dev->dev_private;
 414         u32 hist_reg;
 415         u32 pwm_reg;
 416
 417         if (gma_power_begin(dev, false)) {
 418                 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
 419                 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
 420                 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
 421                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 422
 423                 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
 424                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 425                 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
 426                                                 | PWM_PHASEIN_INT_ENABLE,
 427                                                            PWM_CONTROL_LOGIC);
 428                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 429
 430                 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 431
 432                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 433                 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
 434                                                         HISTOGRAM_INT_CONTROL);
 435                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 436                 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
 437                                                         PWM_CONTROL_LOGIC);
 438
 439                 gma_power_end(dev);
 440         }
 441 }
 442
 443 int psb_irq_enable_dpst(struct drm_device *dev)
 444 {
 445         struct drm_psb_private *dev_priv =
 446                 (struct drm_psb_private *) dev->dev_private;
 447         unsigned long irqflags;
 448
 449         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 450
 451         /* enable DPST */
 452         mid_enable_pipe_event(dev_priv, 0);
 453         psb_irq_turn_on_dpst(dev);
 454
 455         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 456         return 0;
 457 }
 458
 459 void psb_irq_turn_off_dpst(struct drm_device *dev)
 460 {
 461         struct drm_psb_private *dev_priv =
 462             (struct drm_psb_private *) dev->dev_private;
 463         u32 pwm_reg;
 464
 465         if (gma_power_begin(dev, false)) {
 466                 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
 467                 PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 468
 469                 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 470
 471                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 472                 PSB_WVDC32(pwm_reg & ~PWM_PHASEIN_INT_ENABLE,
 473                                                         PWM_CONTROL_LOGIC);
 474                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 475
 476                 gma_power_end(dev);
 477         }
 478 }
 479
 480 int psb_irq_disable_dpst(struct drm_device *dev)
 481 {
 482         struct drm_psb_private *dev_priv =
 483             (struct drm_psb_private *) dev->dev_private;
 484         unsigned long irqflags;
 485
 486         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 487
 488         mid_disable_pipe_event(dev_priv, 0);
 489         psb_irq_turn_off_dpst(dev);
 490
 491         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 492
 493         return 0;
 494 }
 495
 496 /*
 497  * It is used to enable VBLANK interrupt
 498  */
 499 int psb_enable_vblank(struct drm_crtc *crtc)
 500 {
 501         struct drm_device *dev = crtc->dev;
 502         unsigned int pipe = crtc->index;
 503         struct drm_psb_private *dev_priv = dev->dev_private;
 504         unsigned long irqflags;
 505         uint32_t reg_val = 0;
 506         uint32_t pipeconf_reg = mid_pipeconf(pipe);
 507
 508         /* Medfield is different - we should perhaps extract out vblank
 509            and blacklight etc ops */
 510         if (IS_MFLD(dev))
 511                 return mdfld_enable_te(dev, pipe);
 512
 513         if (gma_power_begin(dev, false)) {
 514                 reg_val = REG_READ(pipeconf_reg);
 515                 gma_power_end(dev);
 516         }
 517
 518         if (!(reg_val & PIPEACONF_ENABLE))
 519                 return -EINVAL;
 520
 521         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 522
 523         if (pipe == 0)
 524                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
 525         else if (pipe == 1)
 526                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
 527
 528         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 529         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 530         psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 531
 532         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 533
 534         return 0;
 535 }
 536
 537 /*
 538  * It is used to disable VBLANK interrupt
 539  */
 540 void psb_disable_vblank(struct drm_crtc *crtc)
 541 {
 542         struct drm_device *dev = crtc->dev;
 543         unsigned int pipe = crtc->index;
 544         struct drm_psb_private *dev_priv = dev->dev_private;
 545         unsigned long irqflags;
 546
 547         if (IS_MFLD(dev))
 548                 mdfld_disable_te(dev, pipe);
 549         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 550
 551         if (pipe == 0)
 552                 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
 553         else if (pipe == 1)
 554                 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
 555
 556         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 557         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 558         psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 559
 560         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 561 }
 562
 563 /*
 564  * It is used to enable TE interrupt
 565  */
 566 int mdfld_enable_te(struct drm_device *dev, int pipe)
 567 {
 568         struct drm_psb_private *dev_priv =
 569                 (struct drm_psb_private *) dev->dev_private;
 570         unsigned long irqflags;
 571         uint32_t reg_val = 0;
 572         uint32_t pipeconf_reg = mid_pipeconf(pipe);
 573
 574         if (gma_power_begin(dev, false)) {
 575                 reg_val = REG_READ(pipeconf_reg);
 576                 gma_power_end(dev);
 577         }
 578
 579         if (!(reg_val & PIPEACONF_ENABLE))
 580                 return -EINVAL;
 581
 582         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 583
 584         mid_enable_pipe_event(dev_priv, pipe);
 585         psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
 586
 587         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 588
 589         return 0;
 590 }
 591
 592 /*
 593  * It is used to disable TE interrupt
 594  */
 595 void mdfld_disable_te(struct drm_device *dev, int pipe)
 596 {
 597         struct drm_psb_private *dev_priv =
 598                 (struct drm_psb_private *) dev->dev_private;
 599         unsigned long irqflags;
 600
 601         if (!dev_priv->dsr_enable)
 602                 return;
 603
 604         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 605
 606         mid_disable_pipe_event(dev_priv, pipe);
 607         psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
 608
 609         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 610 }
 611
 612 /* Called from drm generic code, passed a 'crtc', which
 613  * we use as a pipe index
 614  */
 615 u32 psb_get_vblank_counter(struct drm_crtc *crtc)
 616 {
 617         struct drm_device *dev = crtc->dev;
 618         unsigned int pipe = crtc->index;
 619         uint32_t high_frame = PIPEAFRAMEHIGH;
 620         uint32_t low_frame = PIPEAFRAMEPIXEL;
 621         uint32_t pipeconf_reg = PIPEACONF;
 622         uint32_t reg_val = 0;
 623         uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
 624
 625         switch (pipe) {
 626         case 0:
 627                 break;
 628         case 1:
 629                 high_frame = PIPEBFRAMEHIGH;
 630                 low_frame = PIPEBFRAMEPIXEL;
 631                 pipeconf_reg = PIPEBCONF;
 632                 break;
 633         case 2:
 634                 high_frame = PIPECFRAMEHIGH;
 635                 low_frame = PIPECFRAMEPIXEL;
 636                 pipeconf_reg = PIPECCONF;
 637                 break;
 638         default:
 639                 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
 640                 return 0;
 641         }
 642
 643         if (!gma_power_begin(dev, false))
 644                 return 0;
 645
 646         reg_val = REG_READ(pipeconf_reg);
 647
 648         if (!(reg_val & PIPEACONF_ENABLE)) {
 649                 dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n",
 650                                                                 pipe);
 651                 goto psb_get_vblank_counter_exit;
 652         }
 653
 654         /*
 655          * High & low register fields aren't synchronized, so make sure
 656          * we get a low value that's stable across two reads of the high
 657          * register.
 658          */
 659         do {
 660                 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 661                          PIPE_FRAME_HIGH_SHIFT);
 662                 low =  ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 663                         PIPE_FRAME_LOW_SHIFT);
 664                 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 665                          PIPE_FRAME_HIGH_SHIFT);
 666         } while (high1 != high2);
 667
 668         count = (high1 << 8) | low;
 669
 670 psb_get_vblank_counter_exit:
 671
 672         gma_power_end(dev);
 673
 674         return count;
 675 }
 676