Merge tag 'io_uring-5.11-2021-01-16' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / gpu / drm / hisilicon / hibmc / hibmc_drm_drv.c
blobd845657fd99cc4f15034e3ed768e69335462e229
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Hisilicon Hibmc SoC drm driver
4 * Based on the bochs drm driver.
6 * Copyright (c) 2016 Huawei Limited.
8 * Author:
9 * Rongrong Zou <zourongrong@huawei.com>
10 * Rongrong Zou <zourongrong@gmail.com>
11 * Jianhua Li <lijianhua@huawei.com>
14 #include <linux/module.h>
15 #include <linux/pci.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_gem_vram_helper.h>
20 #include <drm/drm_irq.h>
21 #include <drm/drm_managed.h>
22 #include <drm/drm_vblank.h>
24 #include "hibmc_drm_drv.h"
25 #include "hibmc_drm_regs.h"
27 DEFINE_DRM_GEM_FOPS(hibmc_fops);
29 static irqreturn_t hibmc_drm_interrupt(int irq, void *arg)
31 struct drm_device *dev = (struct drm_device *)arg;
32 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
33 u32 status;
35 status = readl(priv->mmio + HIBMC_RAW_INTERRUPT);
37 if (status & HIBMC_RAW_INTERRUPT_VBLANK(1)) {
38 writel(HIBMC_RAW_INTERRUPT_VBLANK(1),
39 priv->mmio + HIBMC_RAW_INTERRUPT);
40 drm_handle_vblank(dev, 0);
43 return IRQ_HANDLED;
46 static const struct drm_driver hibmc_driver = {
47 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
48 .fops = &hibmc_fops,
49 .name = "hibmc",
50 .date = "20160828",
51 .desc = "hibmc drm driver",
52 .major = 1,
53 .minor = 0,
54 .debugfs_init = drm_vram_mm_debugfs_init,
55 .dumb_create = hibmc_dumb_create,
56 .dumb_map_offset = drm_gem_vram_driver_dumb_mmap_offset,
57 .gem_prime_mmap = drm_gem_prime_mmap,
58 .irq_handler = hibmc_drm_interrupt,
61 static int __maybe_unused hibmc_pm_suspend(struct device *dev)
63 struct drm_device *drm_dev = dev_get_drvdata(dev);
65 return drm_mode_config_helper_suspend(drm_dev);
68 static int __maybe_unused hibmc_pm_resume(struct device *dev)
70 struct drm_device *drm_dev = dev_get_drvdata(dev);
72 return drm_mode_config_helper_resume(drm_dev);
75 static const struct dev_pm_ops hibmc_pm_ops = {
76 SET_SYSTEM_SLEEP_PM_OPS(hibmc_pm_suspend,
77 hibmc_pm_resume)
80 static int hibmc_kms_init(struct hibmc_drm_private *priv)
82 int ret;
84 drm_mode_config_init(priv->dev);
85 priv->mode_config_initialized = true;
87 priv->dev->mode_config.min_width = 0;
88 priv->dev->mode_config.min_height = 0;
89 priv->dev->mode_config.max_width = 1920;
90 priv->dev->mode_config.max_height = 1200;
92 priv->dev->mode_config.fb_base = priv->fb_base;
93 priv->dev->mode_config.preferred_depth = 32;
94 priv->dev->mode_config.prefer_shadow = 1;
96 priv->dev->mode_config.funcs = (void *)&hibmc_mode_funcs;
98 ret = hibmc_de_init(priv);
99 if (ret) {
100 drm_err(priv->dev, "failed to init de: %d\n", ret);
101 return ret;
104 ret = hibmc_vdac_init(priv);
105 if (ret) {
106 drm_err(priv->dev, "failed to init vdac: %d\n", ret);
107 return ret;
110 return 0;
113 static void hibmc_kms_fini(struct hibmc_drm_private *priv)
115 if (priv->mode_config_initialized) {
116 drm_mode_config_cleanup(priv->dev);
117 priv->mode_config_initialized = false;
122 * It can operate in one of three modes: 0, 1 or Sleep.
124 void hibmc_set_power_mode(struct hibmc_drm_private *priv, u32 power_mode)
126 u32 control_value = 0;
127 void __iomem *mmio = priv->mmio;
128 u32 input = 1;
130 if (power_mode > HIBMC_PW_MODE_CTL_MODE_SLEEP)
131 return;
133 if (power_mode == HIBMC_PW_MODE_CTL_MODE_SLEEP)
134 input = 0;
136 control_value = readl(mmio + HIBMC_POWER_MODE_CTRL);
137 control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK |
138 HIBMC_PW_MODE_CTL_OSC_INPUT_MASK);
139 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode);
140 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input);
141 writel(control_value, mmio + HIBMC_POWER_MODE_CTRL);
144 void hibmc_set_current_gate(struct hibmc_drm_private *priv, unsigned int gate)
146 u32 gate_reg;
147 u32 mode;
148 void __iomem *mmio = priv->mmio;
150 /* Get current power mode. */
151 mode = (readl(mmio + HIBMC_POWER_MODE_CTRL) &
152 HIBMC_PW_MODE_CTL_MODE_MASK) >> HIBMC_PW_MODE_CTL_MODE_SHIFT;
154 switch (mode) {
155 case HIBMC_PW_MODE_CTL_MODE_MODE0:
156 gate_reg = HIBMC_MODE0_GATE;
157 break;
159 case HIBMC_PW_MODE_CTL_MODE_MODE1:
160 gate_reg = HIBMC_MODE1_GATE;
161 break;
163 default:
164 gate_reg = HIBMC_MODE0_GATE;
165 break;
167 writel(gate, mmio + gate_reg);
170 static void hibmc_hw_config(struct hibmc_drm_private *priv)
172 u32 reg;
174 /* On hardware reset, power mode 0 is default. */
175 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
177 /* Enable display power gate & LOCALMEM power gate*/
178 reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
179 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
180 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
181 reg |= HIBMC_CURR_GATE_DISPLAY(1);
182 reg |= HIBMC_CURR_GATE_LOCALMEM(1);
184 hibmc_set_current_gate(priv, reg);
187 * Reset the memory controller. If the memory controller
188 * is not reset in chip,the system might hang when sw accesses
189 * the memory.The memory should be resetted after
190 * changing the MXCLK.
192 reg = readl(priv->mmio + HIBMC_MISC_CTRL);
193 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
194 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(0);
195 writel(reg, priv->mmio + HIBMC_MISC_CTRL);
197 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
198 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1);
200 writel(reg, priv->mmio + HIBMC_MISC_CTRL);
203 static int hibmc_hw_map(struct hibmc_drm_private *priv)
205 struct drm_device *dev = priv->dev;
206 struct pci_dev *pdev = dev->pdev;
207 resource_size_t addr, size, ioaddr, iosize;
209 ioaddr = pci_resource_start(pdev, 1);
210 iosize = pci_resource_len(pdev, 1);
211 priv->mmio = devm_ioremap(dev->dev, ioaddr, iosize);
212 if (!priv->mmio) {
213 drm_err(dev, "Cannot map mmio region\n");
214 return -ENOMEM;
217 addr = pci_resource_start(pdev, 0);
218 size = pci_resource_len(pdev, 0);
219 priv->fb_map = devm_ioremap(dev->dev, addr, size);
220 if (!priv->fb_map) {
221 drm_err(dev, "Cannot map framebuffer\n");
222 return -ENOMEM;
224 priv->fb_base = addr;
225 priv->fb_size = size;
227 return 0;
230 static int hibmc_hw_init(struct hibmc_drm_private *priv)
232 int ret;
234 ret = hibmc_hw_map(priv);
235 if (ret)
236 return ret;
238 hibmc_hw_config(priv);
240 return 0;
243 static int hibmc_unload(struct drm_device *dev)
245 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
247 drm_atomic_helper_shutdown(dev);
249 if (dev->irq_enabled)
250 drm_irq_uninstall(dev);
252 pci_disable_msi(dev->pdev);
253 hibmc_kms_fini(priv);
254 hibmc_mm_fini(priv);
255 dev->dev_private = NULL;
256 return 0;
259 static int hibmc_load(struct drm_device *dev)
261 struct hibmc_drm_private *priv;
262 int ret;
264 priv = drmm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
265 if (!priv) {
266 drm_err(dev, "no memory to allocate for hibmc_drm_private\n");
267 return -ENOMEM;
269 dev->dev_private = priv;
270 priv->dev = dev;
272 ret = hibmc_hw_init(priv);
273 if (ret)
274 goto err;
276 ret = hibmc_mm_init(priv);
277 if (ret)
278 goto err;
280 ret = hibmc_kms_init(priv);
281 if (ret)
282 goto err;
284 ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
285 if (ret) {
286 drm_err(dev, "failed to initialize vblank: %d\n", ret);
287 goto err;
290 ret = pci_enable_msi(dev->pdev);
291 if (ret) {
292 drm_warn(dev, "enabling MSI failed: %d\n", ret);
293 } else {
294 ret = drm_irq_install(dev, dev->pdev->irq);
295 if (ret)
296 drm_warn(dev, "install irq failed: %d\n", ret);
299 /* reset all the states of crtc/plane/encoder/connector */
300 drm_mode_config_reset(dev);
302 return 0;
304 err:
305 hibmc_unload(dev);
306 drm_err(dev, "failed to initialize drm driver: %d\n", ret);
307 return ret;
310 static int hibmc_pci_probe(struct pci_dev *pdev,
311 const struct pci_device_id *ent)
313 struct drm_device *dev;
314 int ret;
316 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev,
317 "hibmcdrmfb");
318 if (ret)
319 return ret;
321 dev = drm_dev_alloc(&hibmc_driver, &pdev->dev);
322 if (IS_ERR(dev)) {
323 DRM_ERROR("failed to allocate drm_device\n");
324 return PTR_ERR(dev);
327 dev->pdev = pdev;
328 pci_set_drvdata(pdev, dev);
330 ret = pci_enable_device(pdev);
331 if (ret) {
332 drm_err(dev, "failed to enable pci device: %d\n", ret);
333 goto err_free;
336 ret = hibmc_load(dev);
337 if (ret) {
338 drm_err(dev, "failed to load hibmc: %d\n", ret);
339 goto err_disable;
342 ret = drm_dev_register(dev, 0);
343 if (ret) {
344 drm_err(dev, "failed to register drv for userspace access: %d\n",
345 ret);
346 goto err_unload;
349 drm_fbdev_generic_setup(dev, dev->mode_config.preferred_depth);
351 return 0;
353 err_unload:
354 hibmc_unload(dev);
355 err_disable:
356 pci_disable_device(pdev);
357 err_free:
358 drm_dev_put(dev);
360 return ret;
363 static void hibmc_pci_remove(struct pci_dev *pdev)
365 struct drm_device *dev = pci_get_drvdata(pdev);
367 drm_dev_unregister(dev);
368 hibmc_unload(dev);
369 drm_dev_put(dev);
372 static const struct pci_device_id hibmc_pci_table[] = {
373 { PCI_VDEVICE(HUAWEI, 0x1711) },
374 {0,}
377 static struct pci_driver hibmc_pci_driver = {
378 .name = "hibmc-drm",
379 .id_table = hibmc_pci_table,
380 .probe = hibmc_pci_probe,
381 .remove = hibmc_pci_remove,
382 .driver.pm = &hibmc_pm_ops,
385 module_pci_driver(hibmc_pci_driver);
387 MODULE_DEVICE_TABLE(pci, hibmc_pci_table);
388 MODULE_AUTHOR("RongrongZou <zourongrong@huawei.com>");
389 MODULE_DESCRIPTION("DRM Driver for Hisilicon Hibmc");
390 MODULE_LICENSE("GPL v2");