1 config DRM_I915_FENCE_TIMEOUT
2 int "Timeout for unsignaled foreign fences (ms, jiffy granularity)"
3 default 10000 # milliseconds
5 When listening to a foreign fence, we install a supplementary timer
6 to ensure that we are always signaled and our userspace is able to
7 make forward progress. This value specifies the timeout used for an
8 unsignaled foreign fence.
10 May be 0 to disable the timeout, and rely on the foreign fence being
13 config DRM_I915_USERFAULT_AUTOSUSPEND
14 int "Runtime autosuspend delay for userspace GGTT mmaps (ms)"
15 default 250 # milliseconds
17 On runtime suspend, as we suspend the device, we have to revoke
18 userspace GGTT mmaps and force userspace to take a pagefault on
19 their next access. The revocation and subsequent recreation of
20 the GGTT mmap can be very slow and so we impose a small hysteris
21 that complements the runtime-pm autosuspend and provides a lower
22 floor on the autosuspend delay.
24 May be 0 to disable the extra delay and solely use the device level
25 runtime pm autosuspend delay tunable.
27 config DRM_I915_HEARTBEAT_INTERVAL
28 int "Interval between heartbeat pulses (ms)"
29 default 2500 # milliseconds
31 The driver sends a periodic heartbeat down all active engines to
32 check the health of the GPU and undertake regular house-keeping of
33 internal driver state.
35 This is adjustable via
36 /sys/class/drm/card?/engine/*/heartbeat_interval_ms
38 May be 0 to disable heartbeats and therefore disable automatic GPU
41 config DRM_I915_PREEMPT_TIMEOUT
42 int "Preempt timeout (ms, jiffy granularity)"
43 default 640 # milliseconds
45 How long to wait (in milliseconds) for a preemption event to occur
46 when submitting a new context via execlists. If the current context
47 does not hit an arbitration point and yield to HW before the timer
48 expires, the HW will be reset to allow the more important context
51 This is adjustable via
52 /sys/class/drm/card?/engine/*/preempt_timeout_ms
54 May be 0 to disable the timeout.
56 The compiled in default may get overridden at driver probe time on
57 certain platforms and certain engines which will be reflected in the
60 config DRM_I915_MAX_REQUEST_BUSYWAIT
61 int "Busywait for request completion limit (ns)"
62 default 8000 # nanoseconds
64 Before sleeping waiting for a request (GPU operation) to complete,
65 we may spend some time polling for its completion. As the IRQ may
66 take a non-negligible time to setup, we do a short spin first to
67 check if the request will complete in the time it would have taken
68 us to enable the interrupt.
70 This is adjustable via
71 /sys/class/drm/card?/engine/*/max_busywait_duration_ns
73 May be 0 to disable the initial spin. In practice, we estimate
74 the cost of enabling the interrupt (if currently disabled) to be
77 config DRM_I915_STOP_TIMEOUT
78 int "How long to wait for an engine to quiesce gracefully before reset (ms)"
79 default 100 # milliseconds
81 By stopping submission and sleeping for a short time before resetting
82 the GPU, we allow the innocent contexts also on the system to quiesce.
83 It is then less likely for a hanging context to cause collateral
84 damage as the system is reset in order to recover. The corollary is
85 that the reset itself may take longer and so be more disruptive to
86 interactive or low latency workloads.
88 This is adjustable via
89 /sys/class/drm/card?/engine/*/stop_timeout_ms
91 config DRM_I915_TIMESLICE_DURATION
92 int "Scheduling quantum for userspace batches (ms, jiffy granularity)"
93 default 1 # milliseconds
95 When two user batches of equal priority are executing, we will
96 alternate execution of each batch to ensure forward progress of
97 all users. This is necessary in some cases where there may be
98 an implicit dependency between those batches that requires
99 concurrent execution in order for them to proceed, e.g. they
100 interact with each other via userspace semaphores. Each context
101 is scheduled for execution for the timeslice duration, before
102 switching to the next context.
104 This is adjustable via
105 /sys/class/drm/card?/engine/*/timeslice_duration_ms
107 May be 0 to disable timeslicing.