2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_edid.h>
34 #include <drm/drm_probe_helper.h>
37 #include "intel_connector.h"
38 #include "intel_crt.h"
39 #include "intel_ddi.h"
40 #include "intel_display_types.h"
41 #include "intel_fifo_underrun.h"
42 #include "intel_gmbus.h"
43 #include "intel_hotplug.h"
45 /* Here's the desired hotplug mode */
46 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
47 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
48 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
49 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
50 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
51 ADPA_CRT_HOTPLUG_ENABLE)
54 struct intel_encoder base
;
55 /* DPMS state is stored in the connector, which we need in the
56 * encoder's enable/disable callbacks */
57 struct intel_connector
*connector
;
58 bool force_hotplug_required
;
62 static struct intel_crt
*intel_encoder_to_crt(struct intel_encoder
*encoder
)
64 return container_of(encoder
, struct intel_crt
, base
);
67 static struct intel_crt
*intel_attached_crt(struct intel_connector
*connector
)
69 return intel_encoder_to_crt(intel_attached_encoder(connector
));
72 bool intel_crt_port_enabled(struct drm_i915_private
*dev_priv
,
73 i915_reg_t adpa_reg
, enum pipe
*pipe
)
77 val
= intel_de_read(dev_priv
, adpa_reg
);
79 /* asserts want to know the pipe even if the port is disabled */
80 if (HAS_PCH_CPT(dev_priv
))
81 *pipe
= (val
& ADPA_PIPE_SEL_MASK_CPT
) >> ADPA_PIPE_SEL_SHIFT_CPT
;
83 *pipe
= (val
& ADPA_PIPE_SEL_MASK
) >> ADPA_PIPE_SEL_SHIFT
;
85 return val
& ADPA_DAC_ENABLE
;
88 static bool intel_crt_get_hw_state(struct intel_encoder
*encoder
,
91 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
92 struct intel_crt
*crt
= intel_encoder_to_crt(encoder
);
93 intel_wakeref_t wakeref
;
96 wakeref
= intel_display_power_get_if_enabled(dev_priv
,
97 encoder
->power_domain
);
101 ret
= intel_crt_port_enabled(dev_priv
, crt
->adpa_reg
, pipe
);
103 intel_display_power_put(dev_priv
, encoder
->power_domain
, wakeref
);
108 static unsigned int intel_crt_get_flags(struct intel_encoder
*encoder
)
110 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
111 struct intel_crt
*crt
= intel_encoder_to_crt(encoder
);
114 tmp
= intel_de_read(dev_priv
, crt
->adpa_reg
);
116 if (tmp
& ADPA_HSYNC_ACTIVE_HIGH
)
117 flags
|= DRM_MODE_FLAG_PHSYNC
;
119 flags
|= DRM_MODE_FLAG_NHSYNC
;
121 if (tmp
& ADPA_VSYNC_ACTIVE_HIGH
)
122 flags
|= DRM_MODE_FLAG_PVSYNC
;
124 flags
|= DRM_MODE_FLAG_NVSYNC
;
129 static void intel_crt_get_config(struct intel_encoder
*encoder
,
130 struct intel_crtc_state
*pipe_config
)
132 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_ANALOG
);
134 pipe_config
->hw
.adjusted_mode
.flags
|= intel_crt_get_flags(encoder
);
136 pipe_config
->hw
.adjusted_mode
.crtc_clock
= pipe_config
->port_clock
;
139 static void hsw_crt_get_config(struct intel_encoder
*encoder
,
140 struct intel_crtc_state
*pipe_config
)
142 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
144 intel_ddi_get_config(encoder
, pipe_config
);
146 pipe_config
->hw
.adjusted_mode
.flags
&= ~(DRM_MODE_FLAG_PHSYNC
|
147 DRM_MODE_FLAG_NHSYNC
|
148 DRM_MODE_FLAG_PVSYNC
|
149 DRM_MODE_FLAG_NVSYNC
);
150 pipe_config
->hw
.adjusted_mode
.flags
|= intel_crt_get_flags(encoder
);
152 pipe_config
->hw
.adjusted_mode
.crtc_clock
= lpt_get_iclkip(dev_priv
);
155 /* Note: The caller is required to filter out dpms modes not supported by the
157 static void intel_crt_set_dpms(struct intel_encoder
*encoder
,
158 const struct intel_crtc_state
*crtc_state
,
161 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
162 struct intel_crt
*crt
= intel_encoder_to_crt(encoder
);
163 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
164 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->hw
.adjusted_mode
;
167 if (INTEL_GEN(dev_priv
) >= 5)
168 adpa
= ADPA_HOTPLUG_BITS
;
172 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
173 adpa
|= ADPA_HSYNC_ACTIVE_HIGH
;
174 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
175 adpa
|= ADPA_VSYNC_ACTIVE_HIGH
;
177 /* For CPT allow 3 pipe config, for others just use A or B */
178 if (HAS_PCH_LPT(dev_priv
))
179 ; /* Those bits don't exist here */
180 else if (HAS_PCH_CPT(dev_priv
))
181 adpa
|= ADPA_PIPE_SEL_CPT(crtc
->pipe
);
183 adpa
|= ADPA_PIPE_SEL(crtc
->pipe
);
185 if (!HAS_PCH_SPLIT(dev_priv
))
186 intel_de_write(dev_priv
, BCLRPAT(crtc
->pipe
), 0);
189 case DRM_MODE_DPMS_ON
:
190 adpa
|= ADPA_DAC_ENABLE
;
192 case DRM_MODE_DPMS_STANDBY
:
193 adpa
|= ADPA_DAC_ENABLE
| ADPA_HSYNC_CNTL_DISABLE
;
195 case DRM_MODE_DPMS_SUSPEND
:
196 adpa
|= ADPA_DAC_ENABLE
| ADPA_VSYNC_CNTL_DISABLE
;
198 case DRM_MODE_DPMS_OFF
:
199 adpa
|= ADPA_HSYNC_CNTL_DISABLE
| ADPA_VSYNC_CNTL_DISABLE
;
203 intel_de_write(dev_priv
, crt
->adpa_reg
, adpa
);
206 static void intel_disable_crt(struct intel_atomic_state
*state
,
207 struct intel_encoder
*encoder
,
208 const struct intel_crtc_state
*old_crtc_state
,
209 const struct drm_connector_state
*old_conn_state
)
211 intel_crt_set_dpms(encoder
, old_crtc_state
, DRM_MODE_DPMS_OFF
);
214 static void pch_disable_crt(struct intel_atomic_state
*state
,
215 struct intel_encoder
*encoder
,
216 const struct intel_crtc_state
*old_crtc_state
,
217 const struct drm_connector_state
*old_conn_state
)
221 static void pch_post_disable_crt(struct intel_atomic_state
*state
,
222 struct intel_encoder
*encoder
,
223 const struct intel_crtc_state
*old_crtc_state
,
224 const struct drm_connector_state
*old_conn_state
)
226 intel_disable_crt(state
, encoder
, old_crtc_state
, old_conn_state
);
229 static void hsw_disable_crt(struct intel_atomic_state
*state
,
230 struct intel_encoder
*encoder
,
231 const struct intel_crtc_state
*old_crtc_state
,
232 const struct drm_connector_state
*old_conn_state
)
234 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
236 drm_WARN_ON(&dev_priv
->drm
, !old_crtc_state
->has_pch_encoder
);
238 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
241 static void hsw_post_disable_crt(struct intel_atomic_state
*state
,
242 struct intel_encoder
*encoder
,
243 const struct intel_crtc_state
*old_crtc_state
,
244 const struct drm_connector_state
*old_conn_state
)
246 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
248 intel_crtc_vblank_off(old_crtc_state
);
250 intel_disable_pipe(old_crtc_state
);
252 intel_ddi_disable_transcoder_func(old_crtc_state
);
254 ilk_pfit_disable(old_crtc_state
);
256 intel_ddi_disable_pipe_clock(old_crtc_state
);
258 pch_post_disable_crt(state
, encoder
, old_crtc_state
, old_conn_state
);
260 lpt_disable_pch_transcoder(dev_priv
);
261 lpt_disable_iclkip(dev_priv
);
263 intel_ddi_fdi_post_disable(state
, encoder
, old_crtc_state
, old_conn_state
);
265 drm_WARN_ON(&dev_priv
->drm
, !old_crtc_state
->has_pch_encoder
);
267 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
270 static void hsw_pre_pll_enable_crt(struct intel_atomic_state
*state
,
271 struct intel_encoder
*encoder
,
272 const struct intel_crtc_state
*crtc_state
,
273 const struct drm_connector_state
*conn_state
)
275 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
277 drm_WARN_ON(&dev_priv
->drm
, !crtc_state
->has_pch_encoder
);
279 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
282 static void hsw_pre_enable_crt(struct intel_atomic_state
*state
,
283 struct intel_encoder
*encoder
,
284 const struct intel_crtc_state
*crtc_state
,
285 const struct drm_connector_state
*conn_state
)
287 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
288 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
289 enum pipe pipe
= crtc
->pipe
;
291 drm_WARN_ON(&dev_priv
->drm
, !crtc_state
->has_pch_encoder
);
293 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
295 hsw_fdi_link_train(encoder
, crtc_state
);
297 intel_ddi_enable_pipe_clock(encoder
, crtc_state
);
300 static void hsw_enable_crt(struct intel_atomic_state
*state
,
301 struct intel_encoder
*encoder
,
302 const struct intel_crtc_state
*crtc_state
,
303 const struct drm_connector_state
*conn_state
)
305 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
306 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
307 enum pipe pipe
= crtc
->pipe
;
309 drm_WARN_ON(&dev_priv
->drm
, !crtc_state
->has_pch_encoder
);
311 intel_ddi_enable_transcoder_func(encoder
, crtc_state
);
313 intel_enable_pipe(crtc_state
);
315 lpt_pch_enable(crtc_state
);
317 intel_crtc_vblank_on(crtc_state
);
319 intel_crt_set_dpms(encoder
, crtc_state
, DRM_MODE_DPMS_ON
);
321 intel_wait_for_vblank(dev_priv
, pipe
);
322 intel_wait_for_vblank(dev_priv
, pipe
);
323 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
324 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
327 static void intel_enable_crt(struct intel_atomic_state
*state
,
328 struct intel_encoder
*encoder
,
329 const struct intel_crtc_state
*crtc_state
,
330 const struct drm_connector_state
*conn_state
)
332 intel_crt_set_dpms(encoder
, crtc_state
, DRM_MODE_DPMS_ON
);
335 static enum drm_mode_status
336 intel_crt_mode_valid(struct drm_connector
*connector
,
337 struct drm_display_mode
*mode
)
339 struct drm_device
*dev
= connector
->dev
;
340 struct drm_i915_private
*dev_priv
= to_i915(dev
);
341 int max_dotclk
= dev_priv
->max_dotclk_freq
;
344 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
345 return MODE_NO_DBLESCAN
;
347 if (mode
->clock
< 25000)
348 return MODE_CLOCK_LOW
;
350 if (HAS_PCH_LPT(dev_priv
))
352 else if (IS_VALLEYVIEW(dev_priv
))
354 * 270 MHz due to current DPLL limits,
355 * DAC limit supposedly 355 MHz.
358 else if (IS_GEN_RANGE(dev_priv
, 3, 4))
362 if (mode
->clock
> max_clock
)
363 return MODE_CLOCK_HIGH
;
365 if (mode
->clock
> max_dotclk
)
366 return MODE_CLOCK_HIGH
;
368 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
369 if (HAS_PCH_LPT(dev_priv
) &&
370 ilk_get_lanes_required(mode
->clock
, 270000, 24) > 2)
371 return MODE_CLOCK_HIGH
;
373 /* HSW/BDW FDI limited to 4k */
374 if (mode
->hdisplay
> 4096)
375 return MODE_H_ILLEGAL
;
380 static int intel_crt_compute_config(struct intel_encoder
*encoder
,
381 struct intel_crtc_state
*pipe_config
,
382 struct drm_connector_state
*conn_state
)
384 struct drm_display_mode
*adjusted_mode
=
385 &pipe_config
->hw
.adjusted_mode
;
387 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
390 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
395 static int pch_crt_compute_config(struct intel_encoder
*encoder
,
396 struct intel_crtc_state
*pipe_config
,
397 struct drm_connector_state
*conn_state
)
399 struct drm_display_mode
*adjusted_mode
=
400 &pipe_config
->hw
.adjusted_mode
;
402 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
405 pipe_config
->has_pch_encoder
= true;
406 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
411 static int hsw_crt_compute_config(struct intel_encoder
*encoder
,
412 struct intel_crtc_state
*pipe_config
,
413 struct drm_connector_state
*conn_state
)
415 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
416 struct drm_display_mode
*adjusted_mode
=
417 &pipe_config
->hw
.adjusted_mode
;
419 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
422 /* HSW/BDW FDI limited to 4k */
423 if (adjusted_mode
->crtc_hdisplay
> 4096 ||
424 adjusted_mode
->crtc_hblank_start
> 4096)
427 pipe_config
->has_pch_encoder
= true;
428 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
430 /* LPT FDI RX only supports 8bpc. */
431 if (HAS_PCH_LPT(dev_priv
)) {
432 if (pipe_config
->bw_constrained
&& pipe_config
->pipe_bpp
< 24) {
433 drm_dbg_kms(&dev_priv
->drm
,
434 "LPT only supports 24bpp\n");
438 pipe_config
->pipe_bpp
= 24;
441 /* FDI must always be 2.7 GHz */
442 pipe_config
->port_clock
= 135000 * 2;
447 static bool ilk_crt_detect_hotplug(struct drm_connector
*connector
)
449 struct drm_device
*dev
= connector
->dev
;
450 struct intel_crt
*crt
= intel_attached_crt(to_intel_connector(connector
));
451 struct drm_i915_private
*dev_priv
= to_i915(dev
);
455 /* The first time through, trigger an explicit detection cycle */
456 if (crt
->force_hotplug_required
) {
457 bool turn_off_dac
= HAS_PCH_SPLIT(dev_priv
);
460 crt
->force_hotplug_required
= false;
462 save_adpa
= adpa
= intel_de_read(dev_priv
, crt
->adpa_reg
);
463 drm_dbg_kms(&dev_priv
->drm
,
464 "trigger hotplug detect cycle: adpa=0x%x\n", adpa
);
466 adpa
|= ADPA_CRT_HOTPLUG_FORCE_TRIGGER
;
468 adpa
&= ~ADPA_DAC_ENABLE
;
470 intel_de_write(dev_priv
, crt
->adpa_reg
, adpa
);
472 if (intel_de_wait_for_clear(dev_priv
,
474 ADPA_CRT_HOTPLUG_FORCE_TRIGGER
,
476 drm_dbg_kms(&dev_priv
->drm
,
477 "timed out waiting for FORCE_TRIGGER");
480 intel_de_write(dev_priv
, crt
->adpa_reg
, save_adpa
);
481 intel_de_posting_read(dev_priv
, crt
->adpa_reg
);
485 /* Check the status to see if both blue and green are on now */
486 adpa
= intel_de_read(dev_priv
, crt
->adpa_reg
);
487 if ((adpa
& ADPA_CRT_HOTPLUG_MONITOR_MASK
) != 0)
491 drm_dbg_kms(&dev_priv
->drm
, "ironlake hotplug adpa=0x%x, result %d\n",
497 static bool valleyview_crt_detect_hotplug(struct drm_connector
*connector
)
499 struct drm_device
*dev
= connector
->dev
;
500 struct intel_crt
*crt
= intel_attached_crt(to_intel_connector(connector
));
501 struct drm_i915_private
*dev_priv
= to_i915(dev
);
508 * Doing a force trigger causes a hpd interrupt to get sent, which can
509 * get us stuck in a loop if we're polling:
510 * - We enable power wells and reset the ADPA
511 * - output_poll_exec does force probe on VGA, triggering a hpd
512 * - HPD handler waits for poll to unlock dev->mode_config.mutex
513 * - output_poll_exec shuts off the ADPA, unlocks
514 * dev->mode_config.mutex
515 * - HPD handler runs, resets ADPA and brings us back to the start
517 * Just disable HPD interrupts here to prevent this
519 reenable_hpd
= intel_hpd_disable(dev_priv
, crt
->base
.hpd_pin
);
521 save_adpa
= adpa
= intel_de_read(dev_priv
, crt
->adpa_reg
);
522 drm_dbg_kms(&dev_priv
->drm
,
523 "trigger hotplug detect cycle: adpa=0x%x\n", adpa
);
525 adpa
|= ADPA_CRT_HOTPLUG_FORCE_TRIGGER
;
527 intel_de_write(dev_priv
, crt
->adpa_reg
, adpa
);
529 if (intel_de_wait_for_clear(dev_priv
, crt
->adpa_reg
,
530 ADPA_CRT_HOTPLUG_FORCE_TRIGGER
, 1000)) {
531 drm_dbg_kms(&dev_priv
->drm
,
532 "timed out waiting for FORCE_TRIGGER");
533 intel_de_write(dev_priv
, crt
->adpa_reg
, save_adpa
);
536 /* Check the status to see if both blue and green are on now */
537 adpa
= intel_de_read(dev_priv
, crt
->adpa_reg
);
538 if ((adpa
& ADPA_CRT_HOTPLUG_MONITOR_MASK
) != 0)
543 drm_dbg_kms(&dev_priv
->drm
,
544 "valleyview hotplug adpa=0x%x, result %d\n", adpa
, ret
);
547 intel_hpd_enable(dev_priv
, crt
->base
.hpd_pin
);
552 static bool intel_crt_detect_hotplug(struct drm_connector
*connector
)
554 struct drm_device
*dev
= connector
->dev
;
555 struct drm_i915_private
*dev_priv
= to_i915(dev
);
560 if (HAS_PCH_SPLIT(dev_priv
))
561 return ilk_crt_detect_hotplug(connector
);
563 if (IS_VALLEYVIEW(dev_priv
))
564 return valleyview_crt_detect_hotplug(connector
);
567 * On 4 series desktop, CRT detect sequence need to be done twice
568 * to get a reliable result.
571 if (IS_G45(dev_priv
))
576 for (i
= 0; i
< tries
; i
++) {
577 /* turn on the FORCE_DETECT */
578 i915_hotplug_interrupt_update(dev_priv
,
579 CRT_HOTPLUG_FORCE_DETECT
,
580 CRT_HOTPLUG_FORCE_DETECT
);
581 /* wait for FORCE_DETECT to go off */
582 if (intel_de_wait_for_clear(dev_priv
, PORT_HOTPLUG_EN
,
583 CRT_HOTPLUG_FORCE_DETECT
, 1000))
584 drm_dbg_kms(&dev_priv
->drm
,
585 "timed out waiting for FORCE_DETECT to go off");
588 stat
= intel_de_read(dev_priv
, PORT_HOTPLUG_STAT
);
589 if ((stat
& CRT_HOTPLUG_MONITOR_MASK
) != CRT_HOTPLUG_MONITOR_NONE
)
592 /* clear the interrupt we just generated, if any */
593 intel_de_write(dev_priv
, PORT_HOTPLUG_STAT
, CRT_HOTPLUG_INT_STATUS
);
595 i915_hotplug_interrupt_update(dev_priv
, CRT_HOTPLUG_FORCE_DETECT
, 0);
600 static struct edid
*intel_crt_get_edid(struct drm_connector
*connector
,
601 struct i2c_adapter
*i2c
)
605 edid
= drm_get_edid(connector
, i2c
);
607 if (!edid
&& !intel_gmbus_is_forced_bit(i2c
)) {
608 drm_dbg_kms(connector
->dev
,
609 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
610 intel_gmbus_force_bit(i2c
, true);
611 edid
= drm_get_edid(connector
, i2c
);
612 intel_gmbus_force_bit(i2c
, false);
618 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
619 static int intel_crt_ddc_get_modes(struct drm_connector
*connector
,
620 struct i2c_adapter
*adapter
)
625 edid
= intel_crt_get_edid(connector
, adapter
);
629 ret
= intel_connector_update_modes(connector
, edid
);
635 static bool intel_crt_detect_ddc(struct drm_connector
*connector
)
637 struct intel_crt
*crt
= intel_attached_crt(to_intel_connector(connector
));
638 struct drm_i915_private
*dev_priv
= to_i915(crt
->base
.base
.dev
);
640 struct i2c_adapter
*i2c
;
643 BUG_ON(crt
->base
.type
!= INTEL_OUTPUT_ANALOG
);
645 i2c
= intel_gmbus_get_adapter(dev_priv
, dev_priv
->vbt
.crt_ddc_pin
);
646 edid
= intel_crt_get_edid(connector
, i2c
);
649 bool is_digital
= edid
->input
& DRM_EDID_INPUT_DIGITAL
;
652 * This may be a DVI-I connector with a shared DDC
653 * link between analog and digital outputs, so we
654 * have to check the EDID input spec of the attached device.
657 drm_dbg_kms(&dev_priv
->drm
,
658 "CRT detected via DDC:0x50 [EDID]\n");
661 drm_dbg_kms(&dev_priv
->drm
,
662 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
665 drm_dbg_kms(&dev_priv
->drm
,
666 "CRT not detected via DDC:0x50 [no valid EDID found]\n");
674 static enum drm_connector_status
675 intel_crt_load_detect(struct intel_crt
*crt
, u32 pipe
)
677 struct drm_device
*dev
= crt
->base
.base
.dev
;
678 struct drm_i915_private
*dev_priv
= to_i915(dev
);
679 struct intel_uncore
*uncore
= &dev_priv
->uncore
;
684 u32 vblank
, vblank_start
, vblank_end
;
686 i915_reg_t bclrpat_reg
, vtotal_reg
,
687 vblank_reg
, vsync_reg
, pipeconf_reg
, pipe_dsl_reg
;
689 enum drm_connector_status status
;
691 drm_dbg_kms(&dev_priv
->drm
, "starting load-detect on CRT\n");
693 bclrpat_reg
= BCLRPAT(pipe
);
694 vtotal_reg
= VTOTAL(pipe
);
695 vblank_reg
= VBLANK(pipe
);
696 vsync_reg
= VSYNC(pipe
);
697 pipeconf_reg
= PIPECONF(pipe
);
698 pipe_dsl_reg
= PIPEDSL(pipe
);
700 save_bclrpat
= intel_uncore_read(uncore
, bclrpat_reg
);
701 save_vtotal
= intel_uncore_read(uncore
, vtotal_reg
);
702 vblank
= intel_uncore_read(uncore
, vblank_reg
);
704 vtotal
= ((save_vtotal
>> 16) & 0xfff) + 1;
705 vactive
= (save_vtotal
& 0x7ff) + 1;
707 vblank_start
= (vblank
& 0xfff) + 1;
708 vblank_end
= ((vblank
>> 16) & 0xfff) + 1;
710 /* Set the border color to purple. */
711 intel_uncore_write(uncore
, bclrpat_reg
, 0x500050);
713 if (!IS_GEN(dev_priv
, 2)) {
714 u32 pipeconf
= intel_uncore_read(uncore
, pipeconf_reg
);
715 intel_uncore_write(uncore
,
717 pipeconf
| PIPECONF_FORCE_BORDER
);
718 intel_uncore_posting_read(uncore
, pipeconf_reg
);
719 /* Wait for next Vblank to substitue
720 * border color for Color info */
721 intel_wait_for_vblank(dev_priv
, pipe
);
722 st00
= intel_uncore_read8(uncore
, _VGA_MSR_WRITE
);
723 status
= ((st00
& (1 << 4)) != 0) ?
724 connector_status_connected
:
725 connector_status_disconnected
;
727 intel_uncore_write(uncore
, pipeconf_reg
, pipeconf
);
729 bool restore_vblank
= false;
733 * If there isn't any border, add some.
734 * Yes, this will flicker
736 if (vblank_start
<= vactive
&& vblank_end
>= vtotal
) {
737 u32 vsync
= intel_de_read(dev_priv
, vsync_reg
);
738 u32 vsync_start
= (vsync
& 0xffff) + 1;
740 vblank_start
= vsync_start
;
741 intel_uncore_write(uncore
,
744 ((vblank_end
- 1) << 16));
745 restore_vblank
= true;
747 /* sample in the vertical border, selecting the larger one */
748 if (vblank_start
- vactive
>= vtotal
- vblank_end
)
749 vsample
= (vblank_start
+ vactive
) >> 1;
751 vsample
= (vtotal
+ vblank_end
) >> 1;
754 * Wait for the border to be displayed
756 while (intel_uncore_read(uncore
, pipe_dsl_reg
) >= vactive
)
758 while ((dsl
= intel_uncore_read(uncore
, pipe_dsl_reg
)) <=
762 * Watch ST00 for an entire scanline
768 /* Read the ST00 VGA status register */
769 st00
= intel_uncore_read8(uncore
, _VGA_MSR_WRITE
);
772 } while ((intel_uncore_read(uncore
, pipe_dsl_reg
) == dsl
));
774 /* restore vblank if necessary */
776 intel_uncore_write(uncore
, vblank_reg
, vblank
);
778 * If more than 3/4 of the scanline detected a monitor,
779 * then it is assumed to be present. This works even on i830,
780 * where there isn't any way to force the border color across
783 status
= detect
* 4 > count
* 3 ?
784 connector_status_connected
:
785 connector_status_disconnected
;
788 /* Restore previous settings */
789 intel_uncore_write(uncore
, bclrpat_reg
, save_bclrpat
);
794 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id
*id
)
796 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id
->ident
);
800 static const struct dmi_system_id intel_spurious_crt_detect
[] = {
802 .callback
= intel_spurious_crt_detect_dmi_callback
,
805 DMI_MATCH(DMI_SYS_VENDOR
, "ACER"),
806 DMI_MATCH(DMI_PRODUCT_NAME
, "ZGB"),
810 .callback
= intel_spurious_crt_detect_dmi_callback
,
811 .ident
= "Intel DZ77BH-55K",
813 DMI_MATCH(DMI_BOARD_VENDOR
, "Intel Corporation"),
814 DMI_MATCH(DMI_BOARD_NAME
, "DZ77BH-55K"),
821 intel_crt_detect(struct drm_connector
*connector
,
822 struct drm_modeset_acquire_ctx
*ctx
,
825 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
826 struct intel_crt
*crt
= intel_attached_crt(to_intel_connector(connector
));
827 struct intel_encoder
*intel_encoder
= &crt
->base
;
828 intel_wakeref_t wakeref
;
830 struct intel_load_detect_pipe tmp
;
832 drm_dbg_kms(&dev_priv
->drm
, "[CONNECTOR:%d:%s] force=%d\n",
833 connector
->base
.id
, connector
->name
,
836 if (!INTEL_DISPLAY_ENABLED(dev_priv
))
837 return connector_status_disconnected
;
839 if (dev_priv
->params
.load_detect_test
) {
840 wakeref
= intel_display_power_get(dev_priv
,
841 intel_encoder
->power_domain
);
845 /* Skip machines without VGA that falsely report hotplug events */
846 if (dmi_check_system(intel_spurious_crt_detect
))
847 return connector_status_disconnected
;
849 wakeref
= intel_display_power_get(dev_priv
,
850 intel_encoder
->power_domain
);
852 if (I915_HAS_HOTPLUG(dev_priv
)) {
853 /* We can not rely on the HPD pin always being correctly wired
854 * up, for example many KVM do not pass it through, and so
855 * only trust an assertion that the monitor is connected.
857 if (intel_crt_detect_hotplug(connector
)) {
858 drm_dbg_kms(&dev_priv
->drm
,
859 "CRT detected via hotplug\n");
860 status
= connector_status_connected
;
863 drm_dbg_kms(&dev_priv
->drm
,
864 "CRT not detected via hotplug\n");
867 if (intel_crt_detect_ddc(connector
)) {
868 status
= connector_status_connected
;
872 /* Load detection is broken on HPD capable machines. Whoever wants a
873 * broken monitor (without edid) to work behind a broken kvm (that fails
874 * to have the right resistors for HP detection) needs to fix this up.
875 * For now just bail out. */
876 if (I915_HAS_HOTPLUG(dev_priv
)) {
877 status
= connector_status_disconnected
;
883 status
= connector
->status
;
887 /* for pre-945g platforms use load detect */
888 ret
= intel_get_load_detect_pipe(connector
, &tmp
, ctx
);
890 if (intel_crt_detect_ddc(connector
))
891 status
= connector_status_connected
;
892 else if (INTEL_GEN(dev_priv
) < 4)
893 status
= intel_crt_load_detect(crt
,
894 to_intel_crtc(connector
->state
->crtc
)->pipe
);
895 else if (dev_priv
->params
.load_detect_test
)
896 status
= connector_status_disconnected
;
898 status
= connector_status_unknown
;
899 intel_release_load_detect_pipe(connector
, &tmp
, ctx
);
900 } else if (ret
== 0) {
901 status
= connector_status_unknown
;
907 intel_display_power_put(dev_priv
, intel_encoder
->power_domain
, wakeref
);
910 * Make sure the refs for power wells enabled during detect are
911 * dropped to avoid a new detect cycle triggered by HPD polling.
913 intel_display_power_flush_work(dev_priv
);
918 static int intel_crt_get_modes(struct drm_connector
*connector
)
920 struct drm_device
*dev
= connector
->dev
;
921 struct drm_i915_private
*dev_priv
= to_i915(dev
);
922 struct intel_crt
*crt
= intel_attached_crt(to_intel_connector(connector
));
923 struct intel_encoder
*intel_encoder
= &crt
->base
;
924 intel_wakeref_t wakeref
;
925 struct i2c_adapter
*i2c
;
928 wakeref
= intel_display_power_get(dev_priv
,
929 intel_encoder
->power_domain
);
931 i2c
= intel_gmbus_get_adapter(dev_priv
, dev_priv
->vbt
.crt_ddc_pin
);
932 ret
= intel_crt_ddc_get_modes(connector
, i2c
);
933 if (ret
|| !IS_G4X(dev_priv
))
936 /* Try to probe digital port for output in DVI-I -> VGA mode. */
937 i2c
= intel_gmbus_get_adapter(dev_priv
, GMBUS_PIN_DPB
);
938 ret
= intel_crt_ddc_get_modes(connector
, i2c
);
941 intel_display_power_put(dev_priv
, intel_encoder
->power_domain
, wakeref
);
946 void intel_crt_reset(struct drm_encoder
*encoder
)
948 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
949 struct intel_crt
*crt
= intel_encoder_to_crt(to_intel_encoder(encoder
));
951 if (INTEL_GEN(dev_priv
) >= 5) {
954 adpa
= intel_de_read(dev_priv
, crt
->adpa_reg
);
955 adpa
&= ~ADPA_CRT_HOTPLUG_MASK
;
956 adpa
|= ADPA_HOTPLUG_BITS
;
957 intel_de_write(dev_priv
, crt
->adpa_reg
, adpa
);
958 intel_de_posting_read(dev_priv
, crt
->adpa_reg
);
960 drm_dbg_kms(&dev_priv
->drm
, "crt adpa set to 0x%x\n", adpa
);
961 crt
->force_hotplug_required
= true;
967 * Routines for controlling stuff on the analog port
970 static const struct drm_connector_funcs intel_crt_connector_funcs
= {
971 .fill_modes
= drm_helper_probe_single_connector_modes
,
972 .late_register
= intel_connector_register
,
973 .early_unregister
= intel_connector_unregister
,
974 .destroy
= intel_connector_destroy
,
975 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
976 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
979 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs
= {
980 .detect_ctx
= intel_crt_detect
,
981 .mode_valid
= intel_crt_mode_valid
,
982 .get_modes
= intel_crt_get_modes
,
985 static const struct drm_encoder_funcs intel_crt_enc_funcs
= {
986 .reset
= intel_crt_reset
,
987 .destroy
= intel_encoder_destroy
,
990 void intel_crt_init(struct drm_i915_private
*dev_priv
)
992 struct drm_connector
*connector
;
993 struct intel_crt
*crt
;
994 struct intel_connector
*intel_connector
;
998 if (HAS_PCH_SPLIT(dev_priv
))
1000 else if (IS_VALLEYVIEW(dev_priv
))
1001 adpa_reg
= VLV_ADPA
;
1005 adpa
= intel_de_read(dev_priv
, adpa_reg
);
1006 if ((adpa
& ADPA_DAC_ENABLE
) == 0) {
1008 * On some machines (some IVB at least) CRT can be
1009 * fused off, but there's no known fuse bit to
1010 * indicate that. On these machine the ADPA register
1011 * works normally, except the DAC enable bit won't
1012 * take. So the only way to tell is attempt to enable
1013 * it and see what happens.
1015 intel_de_write(dev_priv
, adpa_reg
,
1016 adpa
| ADPA_DAC_ENABLE
| ADPA_HSYNC_CNTL_DISABLE
| ADPA_VSYNC_CNTL_DISABLE
);
1017 if ((intel_de_read(dev_priv
, adpa_reg
) & ADPA_DAC_ENABLE
) == 0)
1019 intel_de_write(dev_priv
, adpa_reg
, adpa
);
1022 crt
= kzalloc(sizeof(struct intel_crt
), GFP_KERNEL
);
1026 intel_connector
= intel_connector_alloc();
1027 if (!intel_connector
) {
1032 connector
= &intel_connector
->base
;
1033 crt
->connector
= intel_connector
;
1034 drm_connector_init(&dev_priv
->drm
, &intel_connector
->base
,
1035 &intel_crt_connector_funcs
, DRM_MODE_CONNECTOR_VGA
);
1037 drm_encoder_init(&dev_priv
->drm
, &crt
->base
.base
, &intel_crt_enc_funcs
,
1038 DRM_MODE_ENCODER_DAC
, "CRT");
1040 intel_connector_attach_encoder(intel_connector
, &crt
->base
);
1042 crt
->base
.type
= INTEL_OUTPUT_ANALOG
;
1043 crt
->base
.cloneable
= (1 << INTEL_OUTPUT_DVO
) | (1 << INTEL_OUTPUT_HDMI
);
1044 if (IS_I830(dev_priv
))
1045 crt
->base
.pipe_mask
= BIT(PIPE_A
);
1047 crt
->base
.pipe_mask
= ~0;
1049 if (IS_GEN(dev_priv
, 2))
1050 connector
->interlace_allowed
= 0;
1052 connector
->interlace_allowed
= 1;
1053 connector
->doublescan_allowed
= 0;
1055 crt
->adpa_reg
= adpa_reg
;
1057 crt
->base
.power_domain
= POWER_DOMAIN_PORT_CRT
;
1059 if (I915_HAS_HOTPLUG(dev_priv
) &&
1060 !dmi_check_system(intel_spurious_crt_detect
)) {
1061 crt
->base
.hpd_pin
= HPD_CRT
;
1062 crt
->base
.hotplug
= intel_encoder_hotplug
;
1063 intel_connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
1065 intel_connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
;
1068 if (HAS_DDI(dev_priv
)) {
1069 crt
->base
.port
= PORT_E
;
1070 crt
->base
.get_config
= hsw_crt_get_config
;
1071 crt
->base
.get_hw_state
= intel_ddi_get_hw_state
;
1072 crt
->base
.compute_config
= hsw_crt_compute_config
;
1073 crt
->base
.pre_pll_enable
= hsw_pre_pll_enable_crt
;
1074 crt
->base
.pre_enable
= hsw_pre_enable_crt
;
1075 crt
->base
.enable
= hsw_enable_crt
;
1076 crt
->base
.disable
= hsw_disable_crt
;
1077 crt
->base
.post_disable
= hsw_post_disable_crt
;
1079 if (HAS_PCH_SPLIT(dev_priv
)) {
1080 crt
->base
.compute_config
= pch_crt_compute_config
;
1081 crt
->base
.disable
= pch_disable_crt
;
1082 crt
->base
.post_disable
= pch_post_disable_crt
;
1084 crt
->base
.compute_config
= intel_crt_compute_config
;
1085 crt
->base
.disable
= intel_disable_crt
;
1087 crt
->base
.port
= PORT_NONE
;
1088 crt
->base
.get_config
= intel_crt_get_config
;
1089 crt
->base
.get_hw_state
= intel_crt_get_hw_state
;
1090 crt
->base
.enable
= intel_enable_crt
;
1092 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1094 drm_connector_helper_add(connector
, &intel_crt_connector_helper_funcs
);
1097 * TODO: find a proper way to discover whether we need to set the the
1098 * polarity and link reversal bits or not, instead of relying on the
1101 if (HAS_PCH_LPT(dev_priv
)) {
1102 u32 fdi_config
= FDI_RX_POLARITY_REVERSED_LPT
|
1103 FDI_RX_LINK_REVERSAL_OVERRIDE
;
1105 dev_priv
->fdi_rx_config
= intel_de_read(dev_priv
,
1106 FDI_RX_CTL(PIPE_A
)) & fdi_config
;
1109 intel_crt_reset(&crt
->base
.base
);