drivers/gpu/drm/i915/display/intel_dpll_mgr.h

   1 /*
   2  * Copyright © 2012-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DPLL_MGR_H_
  26 #define _INTEL_DPLL_MGR_H_
  27
  28 #include <linux/types.h>
  29
  30 #include "intel_display.h"
  31 #include "intel_wakeref.h"
  32
  33 /*FIXME: Move this to a more appropriate place. */
  34 #define abs_diff(a, b) ({                       \
  35         typeof(a) __a = (a);                    \
  36         typeof(b) __b = (b);                    \
  37         (void) (&__a == &__b);                  \
  38         __a > __b ? (__a - __b) : (__b - __a); })
  39
  40 struct drm_device;
  41 struct drm_i915_private;
  42 struct intel_atomic_state;
  43 struct intel_crtc;
  44 struct intel_crtc_state;
  45 struct intel_encoder;
  46 struct intel_shared_dpll;
  47
  48 /**
  49  * enum intel_dpll_id - possible DPLL ids
  50  *
  51  * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
  52  */
  53 enum intel_dpll_id {
  54         /**
  55          * @DPLL_ID_PRIVATE: non-shared dpll in use
  56          */
  57         DPLL_ID_PRIVATE = -1,
  58
  59         /**
  60          * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
  61          */
  62         DPLL_ID_PCH_PLL_A = 0,
  63         /**
  64          * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
  65          */
  66         DPLL_ID_PCH_PLL_B = 1,
  67
  68
  69         /**
  70          * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1
  71          */
  72         DPLL_ID_WRPLL1 = 0,
  73         /**
  74          * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2
  75          */
  76         DPLL_ID_WRPLL2 = 1,
  77         /**
  78          * @DPLL_ID_SPLL: HSW and BDW SPLL
  79          */
  80         DPLL_ID_SPLL = 2,
  81         /**
  82          * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL
  83          */
  84         DPLL_ID_LCPLL_810 = 3,
  85         /**
  86          * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL
  87          */
  88         DPLL_ID_LCPLL_1350 = 4,
  89         /**
  90          * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL
  91          */
  92         DPLL_ID_LCPLL_2700 = 5,
  93
  94
  95         /**
  96          * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0
  97          */
  98         DPLL_ID_SKL_DPLL0 = 0,
  99         /**
 100          * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1
 101          */
 102         DPLL_ID_SKL_DPLL1 = 1,
 103         /**
 104          * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2
 105          */
 106         DPLL_ID_SKL_DPLL2 = 2,
 107         /**
 108          * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3
 109          */
 110         DPLL_ID_SKL_DPLL3 = 3,
 111
 112
 113         /**
 114          * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
 115          */
 116         DPLL_ID_ICL_DPLL0 = 0,
 117         /**
 118          * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
 119          */
 120         DPLL_ID_ICL_DPLL1 = 1,
 121         /**
 122          * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
 123          */
 124         DPLL_ID_EHL_DPLL4 = 2,
 125         /**
 126          * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
 127          */
 128         DPLL_ID_ICL_TBTPLL = 2,
 129         /**
 130          * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
 131          *                      TGL TC PLL 1 port 1 (TC1)
 132          */
 133         DPLL_ID_ICL_MGPLL1 = 3,
 134         /**
 135          * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
 136          *                      TGL TC PLL 1 port 2 (TC2)
 137          */
 138         DPLL_ID_ICL_MGPLL2 = 4,
 139         /**
 140          * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
 141          *                      TGL TC PLL 1 port 3 (TC3)
 142          */
 143         DPLL_ID_ICL_MGPLL3 = 5,
 144         /**
 145          * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
 146          *                      TGL TC PLL 1 port 4 (TC4)
 147          */
 148         DPLL_ID_ICL_MGPLL4 = 6,
 149         /**
 150          * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
 151          */
 152         DPLL_ID_TGL_MGPLL5 = 7,
 153         /**
 154          * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
 155          */
 156         DPLL_ID_TGL_MGPLL6 = 8,
 157
 158         /**
 159          * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
 160          */
 161         DPLL_ID_DG1_DPLL0 = 0,
 162         /**
 163          * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
 164          */
 165         DPLL_ID_DG1_DPLL1 = 1,
 166         /**
 167          * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
 168          */
 169         DPLL_ID_DG1_DPLL2 = 2,
 170         /**
 171          * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
 172          */
 173         DPLL_ID_DG1_DPLL3 = 3,
 174 };
 175
 176 #define I915_NUM_PLLS 9
 177
 178 enum icl_port_dpll_id {
 179         ICL_PORT_DPLL_DEFAULT,
 180         ICL_PORT_DPLL_MG_PHY,
 181
 182         ICL_PORT_DPLL_COUNT,
 183 };
 184
 185 struct intel_dpll_hw_state {
 186         /* i9xx, pch plls */
 187         u32 dpll;
 188         u32 dpll_md;
 189         u32 fp0;
 190         u32 fp1;
 191
 192         /* hsw, bdw */
 193         u32 wrpll;
 194         u32 spll;
 195
 196         /* skl */
 197         /*
 198          * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
 199          * lower part of ctrl1 and they get shifted into position when writing
 200          * the register.  This allows us to easily compare the state to share
 201          * the DPLL.
 202          */
 203         u32 ctrl1;
 204         /* HDMI only, 0 when used for DP */
 205         u32 cfgcr1, cfgcr2;
 206
 207         /* cnl */
 208         u32 cfgcr0;
 209         /* CNL also uses cfgcr1 */
 210
 211         /* bxt */
 212         u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
 213
 214         /*
 215          * ICL uses the following, already defined:
 216          * u32 cfgcr0, cfgcr1;
 217          */
 218         u32 mg_refclkin_ctl;
 219         u32 mg_clktop2_coreclkctl1;
 220         u32 mg_clktop2_hsclkctl;
 221         u32 mg_pll_div0;
 222         u32 mg_pll_div1;
 223         u32 mg_pll_lf;
 224         u32 mg_pll_frac_lock;
 225         u32 mg_pll_ssc;
 226         u32 mg_pll_bias;
 227         u32 mg_pll_tdc_coldst_bias;
 228         u32 mg_pll_bias_mask;
 229         u32 mg_pll_tdc_coldst_bias_mask;
 230 };
 231
 232 /**
 233  * struct intel_shared_dpll_state - hold the DPLL atomic state
 234  *
 235  * This structure holds an atomic state for the DPLL, that can represent
 236  * either its current state (in struct &intel_shared_dpll) or a desired
 237  * future state which would be applied by an atomic mode set (stored in
 238  * a struct &intel_atomic_state).
 239  *
 240  * See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
 241  */
 242 struct intel_shared_dpll_state {
 243         /**
 244          * @crtc_mask: mask of CRTC using this DPLL, active or not
 245          */
 246         unsigned crtc_mask;
 247
 248         /**
 249          * @hw_state: hardware configuration for the DPLL stored in
 250          * struct &intel_dpll_hw_state.
 251          */
 252         struct intel_dpll_hw_state hw_state;
 253 };
 254
 255 /**
 256  * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs
 257  */
 258 struct intel_shared_dpll_funcs {
 259         /**
 260          * @prepare:
 261          *
 262          * Optional hook to perform operations prior to enabling the PLL.
 263          * Called from intel_prepare_shared_dpll() function unless the PLL
 264          * is already enabled.
 265          */
 266         void (*prepare)(struct drm_i915_private *dev_priv,
 267                         struct intel_shared_dpll *pll);
 268
 269         /**
 270          * @enable:
 271          *
 272          * Hook for enabling the pll, called from intel_enable_shared_dpll()
 273          * if the pll is not already enabled.
 274          */
 275         void (*enable)(struct drm_i915_private *dev_priv,
 276                        struct intel_shared_dpll *pll);
 277
 278         /**
 279          * @disable:
 280          *
 281          * Hook for disabling the pll, called from intel_disable_shared_dpll()
 282          * only when it is safe to disable the pll, i.e., there are no more
 283          * tracked users for it.
 284          */
 285         void (*disable)(struct drm_i915_private *dev_priv,
 286                         struct intel_shared_dpll *pll);
 287
 288         /**
 289          * @get_hw_state:
 290          *
 291          * Hook for reading the values currently programmed to the DPLL
 292          * registers. This is used for initial hw state readout and state
 293          * verification after a mode set.
 294          */
 295         bool (*get_hw_state)(struct drm_i915_private *dev_priv,
 296                              struct intel_shared_dpll *pll,
 297                              struct intel_dpll_hw_state *hw_state);
 298
 299         /**
 300          * @get_freq:
 301          *
 302          * Hook for calculating the pll's output frequency based on its
 303          * passed in state.
 304          */
 305         int (*get_freq)(struct drm_i915_private *i915,
 306                         const struct intel_shared_dpll *pll,
 307                         const struct intel_dpll_hw_state *pll_state);
 308 };
 309
 310 /**
 311  * struct dpll_info - display PLL platform specific info
 312  */
 313 struct dpll_info {
 314         /**
 315          * @name: DPLL name; used for logging
 316          */
 317         const char *name;
 318
 319         /**
 320          * @funcs: platform specific hooks
 321          */
 322         const struct intel_shared_dpll_funcs *funcs;
 323
 324         /**
 325          * @id: unique indentifier for this DPLL; should match the index in the
 326          * dev_priv->shared_dplls array
 327          */
 328         enum intel_dpll_id id;
 329
 330 #define INTEL_DPLL_ALWAYS_ON    (1 << 0)
 331         /**
 332          * @flags:
 333          *
 334          * INTEL_DPLL_ALWAYS_ON
 335          *     Inform the state checker that the DPLL is kept enabled even if
 336          *     not in use by any CRTC.
 337          */
 338         u32 flags;
 339 };
 340
 341 /**
 342  * struct intel_shared_dpll - display PLL with tracked state and users
 343  */
 344 struct intel_shared_dpll {
 345         /**
 346          * @state:
 347          *
 348          * Store the state for the pll, including its hw state
 349          * and CRTCs using it.
 350          */
 351         struct intel_shared_dpll_state state;
 352
 353         /**
 354          * @active_mask: mask of active CRTCs (i.e. DPMS on) using this DPLL
 355          */
 356         unsigned active_mask;
 357
 358         /**
 359          * @on: is the PLL actually active? Disabled during modeset
 360          */
 361         bool on;
 362
 363         /**
 364          * @info: platform specific info
 365          */
 366         const struct dpll_info *info;
 367
 368         /**
 369          * @wakeref: In some platforms a device-level runtime pm reference may
 370          * need to be grabbed to disable DC states while this DPLL is enabled
 371          */
 372         intel_wakeref_t wakeref;
 373 };
 374
 375 #define SKL_DPLL0 0
 376 #define SKL_DPLL1 1
 377 #define SKL_DPLL2 2
 378 #define SKL_DPLL3 3
 379
 380 /* shared dpll functions */
 381 struct intel_shared_dpll *
 382 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
 383                             enum intel_dpll_id id);
 384 enum intel_dpll_id
 385 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
 386                          struct intel_shared_dpll *pll);
 387 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 388                         struct intel_shared_dpll *pll,
 389                         bool state);
 390 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 391 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 392 bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
 393                                 struct intel_crtc *crtc,
 394                                 struct intel_encoder *encoder);
 395 void intel_release_shared_dplls(struct intel_atomic_state *state,
 396                                 struct intel_crtc *crtc);
 397 void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
 398                               enum icl_port_dpll_id port_dpll_id);
 399 void intel_update_active_dpll(struct intel_atomic_state *state,
 400                               struct intel_crtc *crtc,
 401                               struct intel_encoder *encoder);
 402 int intel_dpll_get_freq(struct drm_i915_private *i915,
 403                         const struct intel_shared_dpll *pll,
 404                         const struct intel_dpll_hw_state *pll_state);
 405 bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
 406                              struct intel_shared_dpll *pll,
 407                              struct intel_dpll_hw_state *hw_state);
 408 void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
 409 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
 410 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
 411 void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
 412 void intel_shared_dpll_init(struct drm_device *dev);
 413 void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
 414 void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
 415
 416 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
 417                               const struct intel_dpll_hw_state *hw_state);
 418 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
 419 bool intel_dpll_is_combophy(enum intel_dpll_id id);
 420
 421 #endif /* _INTEL_DPLL_MGR_H_ */