drivers/gpu/drm/i915/gvt/display.h

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  26  *
  27  * Contributors:
  28  *    Terrence Xu <terrence.xu@intel.com>
  29  *    Changbin Du <changbin.du@intel.com>
  30  *    Bing Niu <bing.niu@intel.com>
  31  *    Zhi Wang <zhi.a.wang@intel.com>
  32  *
  33  */
  34
  35 #ifndef _GVT_DISPLAY_H_
  36 #define _GVT_DISPLAY_H_
  37
  38 #include <linux/types.h>
  39
  40 struct intel_gvt;
  41 struct intel_vgpu;
  42
  43 #define SBI_REG_MAX     20
  44 #define DPCD_SIZE       0x700
  45
  46 #define intel_vgpu_port(vgpu, port) \
  47         (&(vgpu->display.ports[port]))
  48
  49 #define intel_vgpu_has_monitor_on_port(vgpu, port) \
  50         (intel_vgpu_port(vgpu, port)->edid && \
  51                 intel_vgpu_port(vgpu, port)->edid->data_valid)
  52
  53 #define intel_vgpu_port_is_dp(vgpu, port) \
  54         ((intel_vgpu_port(vgpu, port)->type == GVT_DP_A) || \
  55         (intel_vgpu_port(vgpu, port)->type == GVT_DP_B) || \
  56         (intel_vgpu_port(vgpu, port)->type == GVT_DP_C) || \
  57         (intel_vgpu_port(vgpu, port)->type == GVT_DP_D))
  58
  59 #define INTEL_GVT_MAX_UEVENT_VARS       3
  60
  61 /* DPCD start */
  62 #define DPCD_SIZE       0x700
  63
  64 /* DPCD */
  65 #define DP_SET_POWER            0x600
  66 #define DP_SET_POWER_D0         0x1
  67 #define AUX_NATIVE_WRITE        0x8
  68 #define AUX_NATIVE_READ         0x9
  69
  70 #define AUX_NATIVE_REPLY_MASK   (0x3 << 4)
  71 #define AUX_NATIVE_REPLY_ACK    (0x0 << 4)
  72 #define AUX_NATIVE_REPLY_NAK    (0x1 << 4)
  73 #define AUX_NATIVE_REPLY_DEFER  (0x2 << 4)
  74
  75 #define AUX_BURST_SIZE          20
  76
  77 /* DPCD addresses */
  78 #define DPCD_REV                        0x000
  79 #define DPCD_MAX_LINK_RATE              0x001
  80 #define DPCD_MAX_LANE_COUNT             0x002
  81
  82 #define DPCD_TRAINING_PATTERN_SET       0x102
  83 #define DPCD_SINK_COUNT                 0x200
  84 #define DPCD_LANE0_1_STATUS             0x202
  85 #define DPCD_LANE2_3_STATUS             0x203
  86 #define DPCD_LANE_ALIGN_STATUS_UPDATED  0x204
  87 #define DPCD_SINK_STATUS                0x205
  88
  89 /* link training */
  90 #define DPCD_TRAINING_PATTERN_SET_MASK  0x03
  91 #define DPCD_LINK_TRAINING_DISABLED     0x00
  92 #define DPCD_TRAINING_PATTERN_1         0x01
  93 #define DPCD_TRAINING_PATTERN_2         0x02
  94
  95 #define DPCD_CP_READY_MASK              (1 << 6)
  96
  97 /* lane status */
  98 #define DPCD_LANES_CR_DONE              0x11
  99 #define DPCD_LANES_EQ_DONE              0x22
 100 #define DPCD_SYMBOL_LOCKED              0x44
 101
 102 #define DPCD_INTERLANE_ALIGN_DONE       0x01
 103
 104 #define DPCD_SINK_IN_SYNC               0x03
 105 /* DPCD end */
 106
 107 #define SBI_RESPONSE_MASK               0x3
 108 #define SBI_RESPONSE_SHIFT              0x1
 109 #define SBI_STAT_MASK                   0x1
 110 #define SBI_STAT_SHIFT                  0x0
 111 #define SBI_OPCODE_SHIFT                8
 112 #define SBI_OPCODE_MASK                 (0xff << SBI_OPCODE_SHIFT)
 113 #define SBI_CMD_IORD                    2
 114 #define SBI_CMD_IOWR                    3
 115 #define SBI_CMD_CRRD                    6
 116 #define SBI_CMD_CRWR                    7
 117 #define SBI_ADDR_OFFSET_SHIFT           16
 118 #define SBI_ADDR_OFFSET_MASK            (0xffff << SBI_ADDR_OFFSET_SHIFT)
 119
 120 struct intel_vgpu_sbi_register {
 121         unsigned int offset;
 122         u32 value;
 123 };
 124
 125 struct intel_vgpu_sbi {
 126         int number;
 127         struct intel_vgpu_sbi_register registers[SBI_REG_MAX];
 128 };
 129
 130 enum intel_gvt_plane_type {
 131         PRIMARY_PLANE = 0,
 132         CURSOR_PLANE,
 133         SPRITE_PLANE,
 134         MAX_PLANE
 135 };
 136
 137 struct intel_vgpu_dpcd_data {
 138         bool data_valid;
 139         u8 data[DPCD_SIZE];
 140 };
 141
 142 enum intel_vgpu_port_type {
 143         GVT_CRT = 0,
 144         GVT_DP_A,
 145         GVT_DP_B,
 146         GVT_DP_C,
 147         GVT_DP_D,
 148         GVT_HDMI_B,
 149         GVT_HDMI_C,
 150         GVT_HDMI_D,
 151         GVT_PORT_MAX
 152 };
 153
 154 enum intel_vgpu_edid {
 155         GVT_EDID_1024_768,
 156         GVT_EDID_1920_1200,
 157         GVT_EDID_NUM,
 158 };
 159
 160 struct intel_vgpu_port {
 161         /* per display EDID information */
 162         struct intel_vgpu_edid_data *edid;
 163         /* per display DPCD information */
 164         struct intel_vgpu_dpcd_data *dpcd;
 165         int type;
 166         enum intel_vgpu_edid id;
 167 };
 168
 169 static inline char *vgpu_edid_str(enum intel_vgpu_edid id)
 170 {
 171         switch (id) {
 172         case GVT_EDID_1024_768:
 173                 return "1024x768";
 174         case GVT_EDID_1920_1200:
 175                 return "1920x1200";
 176         default:
 177                 return "";
 178         }
 179 }
 180
 181 static inline unsigned int vgpu_edid_xres(enum intel_vgpu_edid id)
 182 {
 183         switch (id) {
 184         case GVT_EDID_1024_768:
 185                 return 1024;
 186         case GVT_EDID_1920_1200:
 187                 return 1920;
 188         default:
 189                 return 0;
 190         }
 191 }
 192
 193 static inline unsigned int vgpu_edid_yres(enum intel_vgpu_edid id)
 194 {
 195         switch (id) {
 196         case GVT_EDID_1024_768:
 197                 return 768;
 198         case GVT_EDID_1920_1200:
 199                 return 1200;
 200         default:
 201                 return 0;
 202         }
 203 }
 204
 205 void intel_gvt_emulate_vblank(struct intel_gvt *gvt);
 206 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt);
 207
 208 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution);
 209 void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
 210 void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
 211
 212 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
 213
 214 #endif