drivers/gpu/drm/i915/gvt/execlist.h

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  25  *    Zhi Wang <zhi.a.wang@intel.com>
  26  *
  27  * Contributors:
  28  *    Min He <min.he@intel.com>
  29  *    Bing Niu <bing.niu@intel.com>
  30  *    Ping Gao <ping.a.gao@intel.com>
  31  *    Tina Zhang <tina.zhang@intel.com>
  32  *
  33  */
  34
  35 #ifndef _GVT_EXECLIST_H_
  36 #define _GVT_EXECLIST_H_
  37
  38 #include <linux/types.h>
  39
  40 struct execlist_ctx_descriptor_format {
  41         union {
  42                 u32 ldw;
  43                 struct {
  44                         u32 valid                  : 1;
  45                         u32 force_pd_restore       : 1;
  46                         u32 force_restore          : 1;
  47                         u32 addressing_mode        : 2;
  48                         u32 llc_coherency          : 1;
  49                         u32 fault_handling         : 2;
  50                         u32 privilege_access       : 1;
  51                         u32 reserved               : 3;
  52                         u32 lrca                   : 20;
  53                 };
  54         };
  55         union {
  56                 u32 udw;
  57                 u32 context_id;
  58         };
  59 };
  60
  61 struct execlist_status_format {
  62         union {
  63                 u32 ldw;
  64                 struct {
  65                         u32 current_execlist_pointer       :1;
  66                         u32 execlist_write_pointer         :1;
  67                         u32 execlist_queue_full            :1;
  68                         u32 execlist_1_valid               :1;
  69                         u32 execlist_0_valid               :1;
  70                         u32 last_ctx_switch_reason         :9;
  71                         u32 current_active_elm_status      :2;
  72                         u32 arbitration_enable             :1;
  73                         u32 execlist_1_active              :1;
  74                         u32 execlist_0_active              :1;
  75                         u32 reserved                       :13;
  76                 };
  77         };
  78         union {
  79                 u32 udw;
  80                 u32 context_id;
  81         };
  82 };
  83
  84 struct execlist_context_status_pointer_format {
  85         union {
  86                 u32 dw;
  87                 struct {
  88                         u32 write_ptr              :3;
  89                         u32 reserved               :5;
  90                         u32 read_ptr               :3;
  91                         u32 reserved2              :5;
  92                         u32 mask                   :16;
  93                 };
  94         };
  95 };
  96
  97 struct execlist_context_status_format {
  98         union {
  99                 u32 ldw;
 100                 struct {
 101                         u32 idle_to_active         :1;
 102                         u32 preempted              :1;
 103                         u32 element_switch         :1;
 104                         u32 active_to_idle         :1;
 105                         u32 context_complete       :1;
 106                         u32 wait_on_sync_flip      :1;
 107                         u32 wait_on_vblank         :1;
 108                         u32 wait_on_semaphore      :1;
 109                         u32 wait_on_scanline       :1;
 110                         u32 reserved               :2;
 111                         u32 semaphore_wait_mode    :1;
 112                         u32 display_plane          :3;
 113                         u32 lite_restore           :1;
 114                         u32 reserved_2             :16;
 115                 };
 116         };
 117         union {
 118                 u32 udw;
 119                 u32 context_id;
 120         };
 121 };
 122
 123 struct execlist_mmio_pair {
 124         u32 addr;
 125         u32 val;
 126 };
 127
 128 /* The first 52 dwords in register state context */
 129 struct execlist_ring_context {
 130         u32 nop1;
 131         u32 lri_cmd_1;
 132         struct execlist_mmio_pair ctx_ctrl;
 133         struct execlist_mmio_pair ring_header;
 134         struct execlist_mmio_pair ring_tail;
 135         struct execlist_mmio_pair rb_start;
 136         struct execlist_mmio_pair rb_ctrl;
 137         struct execlist_mmio_pair bb_cur_head_UDW;
 138         struct execlist_mmio_pair bb_cur_head_LDW;
 139         struct execlist_mmio_pair bb_state;
 140         struct execlist_mmio_pair second_bb_addr_UDW;
 141         struct execlist_mmio_pair second_bb_addr_LDW;
 142         struct execlist_mmio_pair second_bb_state;
 143         struct execlist_mmio_pair bb_per_ctx_ptr;
 144         struct execlist_mmio_pair rcs_indirect_ctx;
 145         struct execlist_mmio_pair rcs_indirect_ctx_offset;
 146         u32 nop2;
 147         u32 nop3;
 148         u32 nop4;
 149         u32 lri_cmd_2;
 150         struct execlist_mmio_pair ctx_timestamp;
 151         /*
 152          * pdps[8]={ pdp3_UDW, pdp3_LDW, pdp2_UDW, pdp2_LDW,
 153          *           pdp1_UDW, pdp1_LDW, pdp0_UDW, pdp0_LDW}
 154          */
 155         struct execlist_mmio_pair pdps[8];
 156 };
 157
 158 struct intel_vgpu_elsp_dwords {
 159         u32 data[4];
 160         u32 index;
 161 };
 162
 163 struct intel_vgpu_execlist_slot {
 164         struct execlist_ctx_descriptor_format ctx[2];
 165         u32 index;
 166 };
 167
 168 struct intel_vgpu_execlist {
 169         struct intel_vgpu_execlist_slot slot[2];
 170         struct intel_vgpu_execlist_slot *running_slot;
 171         struct intel_vgpu_execlist_slot *pending_slot;
 172         struct execlist_ctx_descriptor_format *running_context;
 173         struct intel_vgpu *vgpu;
 174         struct intel_vgpu_elsp_dwords elsp_dwords;
 175         const struct intel_engine_cs *engine;
 176 };
 177
 178 void intel_vgpu_clean_execlist(struct intel_vgpu *vgpu);
 179
 180 int intel_vgpu_init_execlist(struct intel_vgpu *vgpu);
 181
 182 int intel_vgpu_submit_execlist(struct intel_vgpu *vgpu,
 183                                const struct intel_engine_cs *engine);
 184
 185 void intel_vgpu_reset_execlist(struct intel_vgpu *vgpu,
 186                                intel_engine_mask_t engine_mask);
 187
 188 #endif /*_GVT_EXECLIST_H_*/