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Merge tag 'io_uring-5.11-2021-01-16' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_pm.c
bloba20b5051f18c11b58e58570899f46a4c83b99a05
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/module.h>
29 #include <linux/pm_runtime.h>
30
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_fourcc.h>
33 #include <drm/drm_plane_helper.h>
34
35 #include "display/intel_atomic.h"
36 #include "display/intel_atomic_plane.h"
37 #include "display/intel_bw.h"
38 #include "display/intel_display_types.h"
39 #include "display/intel_fbc.h"
40 #include "display/intel_sprite.h"
41
42 #include "gt/intel_llc.h"
43
44 #include "i915_drv.h"
45 #include "i915_fixed.h"
46 #include "i915_irq.h"
47 #include "i915_trace.h"
48 #include "intel_pm.h"
49 #include "intel_sideband.h"
50 #include "../../../platform/x86/intel_ips.h"
51
52 /* Stores plane specific WM parameters */
53 struct skl_wm_params {
54 bool x_tiled, y_tiled;
55 bool rc_surface;
56 bool is_planar;
57 u32 width;
58 u8 cpp;
59 u32 plane_pixel_rate;
60 u32 y_min_scanlines;
61 u32 plane_bytes_per_line;
62 uint_fixed_16_16_t plane_blocks_per_line;
63 uint_fixed_16_16_t y_tile_minimum;
64 u32 linetime_us;
65 u32 dbuf_block_size;
66 };
67
68 /* used in computing the new watermarks state */
69 struct intel_wm_config {
70 unsigned int num_pipes_active;
71 bool sprites_enabled;
72 bool sprites_scaled;
73 };
74
75 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
76 {
77 if (HAS_LLC(dev_priv)) {
78 /*
79 * WaCompressedResourceDisplayNewHashMode:skl,kbl
80 * Display WA #0390: skl,kbl
81 *
82 * Must match Sampler, Pixel Back End, and Media. See
83 * WaCompressedResourceSamplerPbeMediaNewHashMode.
84 */
85 I915_WRITE(CHICKEN_PAR1_1,
86 I915_READ(CHICKEN_PAR1_1) |
87 SKL_DE_COMPRESSED_HASH_MODE);
88 }
89
90 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
91 I915_WRITE(CHICKEN_PAR1_1,
92 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
93
94 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
95 I915_WRITE(GEN8_CHICKEN_DCPR_1,
96 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
97
98 /*
99 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
100 * Display WA #0859: skl,bxt,kbl,glk,cfl
101 */
102 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
103 DISP_FBC_MEMORY_WAKE);
104 }
105
106 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
107 {
108 gen9_init_clock_gating(dev_priv);
109
110 /* WaDisableSDEUnitClockGating:bxt */
111 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
112 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
113
114 /*
115 * FIXME:
116 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
117 */
118 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
119 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
120
121 /*
122 * Wa: Backlight PWM may stop in the asserted state, causing backlight
123 * to stay fully on.
124 */
125 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
126 PWM1_GATING_DIS | PWM2_GATING_DIS);
127
128 /*
129 * Lower the display internal timeout.
130 * This is needed to avoid any hard hangs when DSI port PLL
131 * is off and a MMIO access is attempted by any privilege
132 * application, using batch buffers or any other means.
133 */
134 I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950));
135
136 /*
137 * WaFbcTurnOffFbcWatermark:bxt
138 * Display WA #0562: bxt
139 */
140 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
141 DISP_FBC_WM_DIS);
142
143 /*
144 * WaFbcHighMemBwCorruptionAvoidance:bxt
145 * Display WA #0883: bxt
146 */
147 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
148 ILK_DPFC_DISABLE_DUMMY0);
149 }
150
151 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
152 {
153 gen9_init_clock_gating(dev_priv);
154
155 /*
156 * WaDisablePWMClockGating:glk
157 * Backlight PWM may stop in the asserted state, causing backlight
158 * to stay fully on.
159 */
160 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
161 PWM1_GATING_DIS | PWM2_GATING_DIS);
162 }
163
164 static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
165 {
166 u32 tmp;
167
168 tmp = I915_READ(CLKCFG);
169
170 switch (tmp & CLKCFG_FSB_MASK) {
171 case CLKCFG_FSB_533:
172 dev_priv->fsb_freq = 533; /* 133*4 */
173 break;
174 case CLKCFG_FSB_800:
175 dev_priv->fsb_freq = 800; /* 200*4 */
176 break;
177 case CLKCFG_FSB_667:
178 dev_priv->fsb_freq = 667; /* 167*4 */
179 break;
180 case CLKCFG_FSB_400:
181 dev_priv->fsb_freq = 400; /* 100*4 */
182 break;
183 }
184
185 switch (tmp & CLKCFG_MEM_MASK) {
186 case CLKCFG_MEM_533:
187 dev_priv->mem_freq = 533;
188 break;
189 case CLKCFG_MEM_667:
190 dev_priv->mem_freq = 667;
191 break;
192 case CLKCFG_MEM_800:
193 dev_priv->mem_freq = 800;
194 break;
195 }
196
197 /* detect pineview DDR3 setting */
198 tmp = I915_READ(CSHRDDR3CTL);
199 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
200 }
201
202 static void ilk_get_mem_freq(struct drm_i915_private *dev_priv)
203 {
204 u16 ddrpll, csipll;
205
206 ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
207 csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0);
208
209 switch (ddrpll & 0xff) {
210 case 0xc:
211 dev_priv->mem_freq = 800;
212 break;
213 case 0x10:
214 dev_priv->mem_freq = 1066;
215 break;
216 case 0x14:
217 dev_priv->mem_freq = 1333;
218 break;
219 case 0x18:
220 dev_priv->mem_freq = 1600;
221 break;
222 default:
223 drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
224 ddrpll & 0xff);
225 dev_priv->mem_freq = 0;
226 break;
227 }
228
229 switch (csipll & 0x3ff) {
230 case 0x00c:
231 dev_priv->fsb_freq = 3200;
232 break;
233 case 0x00e:
234 dev_priv->fsb_freq = 3733;
235 break;
236 case 0x010:
237 dev_priv->fsb_freq = 4266;
238 break;
239 case 0x012:
240 dev_priv->fsb_freq = 4800;
241 break;
242 case 0x014:
243 dev_priv->fsb_freq = 5333;
244 break;
245 case 0x016:
246 dev_priv->fsb_freq = 5866;
247 break;
248 case 0x018:
249 dev_priv->fsb_freq = 6400;
250 break;
251 default:
252 drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n",
253 csipll & 0x3ff);
254 dev_priv->fsb_freq = 0;
255 break;
256 }
257 }
258
259 static const struct cxsr_latency cxsr_latency_table[] = {
260 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
261 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
262 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
263 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
264 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
265
266 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
267 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
268 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
269 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
270 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
271
272 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
273 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
274 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
275 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
276 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
277
278 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
279 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
280 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
281 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
282 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
283
284 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
285 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
286 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
287 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
288 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
289
290 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
291 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
292 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
293 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
294 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
295 };
296
297 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
298 bool is_ddr3,
299 int fsb,
300 int mem)
301 {
302 const struct cxsr_latency *latency;
303 int i;
304
305 if (fsb == 0 || mem == 0)
306 return NULL;
307
308 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
309 latency = &cxsr_latency_table[i];
310 if (is_desktop == latency->is_desktop &&
311 is_ddr3 == latency->is_ddr3 &&
312 fsb == latency->fsb_freq && mem == latency->mem_freq)
313 return latency;
314 }
315
316 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
317
318 return NULL;
319 }
320
321 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
322 {
323 u32 val;
324
325 vlv_punit_get(dev_priv);
326
327 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
328 if (enable)
329 val &= ~FORCE_DDR_HIGH_FREQ;
330 else
331 val |= FORCE_DDR_HIGH_FREQ;
332 val &= ~FORCE_DDR_LOW_FREQ;
333 val |= FORCE_DDR_FREQ_REQ_ACK;
334 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
335
336 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
337 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
338 drm_err(&dev_priv->drm,
339 "timed out waiting for Punit DDR DVFS request\n");
340
341 vlv_punit_put(dev_priv);
342 }
343
344 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
345 {
346 u32 val;
347
348 vlv_punit_get(dev_priv);
349
350 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
351 if (enable)
352 val |= DSP_MAXFIFO_PM5_ENABLE;
353 else
354 val &= ~DSP_MAXFIFO_PM5_ENABLE;
355 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
356
357 vlv_punit_put(dev_priv);
358 }
359
360 #define FW_WM(value, plane) \
361 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
362
363 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
364 {
365 bool was_enabled;
366 u32 val;
367
368 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
369 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
370 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
371 POSTING_READ(FW_BLC_SELF_VLV);
372 } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
373 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
374 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
375 POSTING_READ(FW_BLC_SELF);
376 } else if (IS_PINEVIEW(dev_priv)) {
377 val = I915_READ(DSPFW3);
378 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
379 if (enable)
380 val |= PINEVIEW_SELF_REFRESH_EN;
381 else
382 val &= ~PINEVIEW_SELF_REFRESH_EN;
383 I915_WRITE(DSPFW3, val);
384 POSTING_READ(DSPFW3);
385 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
386 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
387 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
388 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
389 I915_WRITE(FW_BLC_SELF, val);
390 POSTING_READ(FW_BLC_SELF);
391 } else if (IS_I915GM(dev_priv)) {
392 /*
393 * FIXME can't find a bit like this for 915G, and
394 * and yet it does have the related watermark in
395 * FW_BLC_SELF. What's going on?
396 */
397 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
398 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
399 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
400 I915_WRITE(INSTPM, val);
401 POSTING_READ(INSTPM);
402 } else {
403 return false;
404 }
405
406 trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
407
408 drm_dbg_kms(&dev_priv->drm, "memory self-refresh is %s (was %s)\n",
409 enableddisabled(enable),
410 enableddisabled(was_enabled));
411
412 return was_enabled;
413 }
414
415 /**
416 * intel_set_memory_cxsr - Configure CxSR state
417 * @dev_priv: i915 device
418 * @enable: Allow vs. disallow CxSR
419 *
420 * Allow or disallow the system to enter a special CxSR
421 * (C-state self refresh) state. What typically happens in CxSR mode
422 * is that several display FIFOs may get combined into a single larger
423 * FIFO for a particular plane (so called max FIFO mode) to allow the
424 * system to defer memory fetches longer, and the memory will enter
425 * self refresh.
426 *
427 * Note that enabling CxSR does not guarantee that the system enter
428 * this special mode, nor does it guarantee that the system stays
429 * in that mode once entered. So this just allows/disallows the system
430 * to autonomously utilize the CxSR mode. Other factors such as core
431 * C-states will affect when/if the system actually enters/exits the
432 * CxSR mode.
433 *
434 * Note that on VLV/CHV this actually only controls the max FIFO mode,
435 * and the system is free to enter/exit memory self refresh at any time
436 * even when the use of CxSR has been disallowed.
437 *
438 * While the system is actually in the CxSR/max FIFO mode, some plane
439 * control registers will not get latched on vblank. Thus in order to
440 * guarantee the system will respond to changes in the plane registers
441 * we must always disallow CxSR prior to making changes to those registers.
442 * Unfortunately the system will re-evaluate the CxSR conditions at
443 * frame start which happens after vblank start (which is when the plane
444 * registers would get latched), so we can't proceed with the plane update
445 * during the same frame where we disallowed CxSR.
446 *
447 * Certain platforms also have a deeper HPLL SR mode. Fortunately the
448 * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
449 * the hardware w.r.t. HPLL SR when writing to plane registers.
450 * Disallowing just CxSR is sufficient.
451 */
452 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
453 {
454 bool ret;
455
456 mutex_lock(&dev_priv->wm.wm_mutex);
457 ret = _intel_set_memory_cxsr(dev_priv, enable);
458 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
459 dev_priv->wm.vlv.cxsr = enable;
460 else if (IS_G4X(dev_priv))
461 dev_priv->wm.g4x.cxsr = enable;
462 mutex_unlock(&dev_priv->wm.wm_mutex);
463
464 return ret;
465 }
466
467 /*
468 * Latency for FIFO fetches is dependent on several factors:
469 * - memory configuration (speed, channels)
470 * - chipset
471 * - current MCH state
472 * It can be fairly high in some situations, so here we assume a fairly
473 * pessimal value. It's a tradeoff between extra memory fetches (if we
474 * set this value too high, the FIFO will fetch frequently to stay full)
475 * and power consumption (set it too low to save power and we might see
476 * FIFO underruns and display "flicker").
477 *
478 * A value of 5us seems to be a good balance; safe for very low end
479 * platforms but not overly aggressive on lower latency configs.
480 */
481 static const int pessimal_latency_ns = 5000;
482
483 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
484 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
485
486 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
487 {
488 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
489 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
490 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
491 enum pipe pipe = crtc->pipe;
492 int sprite0_start, sprite1_start;
493 u32 dsparb, dsparb2, dsparb3;
494
495 switch (pipe) {
496 case PIPE_A:
497 dsparb = I915_READ(DSPARB);
498 dsparb2 = I915_READ(DSPARB2);
499 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
500 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
501 break;
502 case PIPE_B:
503 dsparb = I915_READ(DSPARB);
504 dsparb2 = I915_READ(DSPARB2);
505 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
506 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
507 break;
508 case PIPE_C:
509 dsparb2 = I915_READ(DSPARB2);
510 dsparb3 = I915_READ(DSPARB3);
511 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
512 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
513 break;
514 default:
515 MISSING_CASE(pipe);
516 return;
517 }
518
519 fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
520 fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
521 fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
522 fifo_state->plane[PLANE_CURSOR] = 63;
523 }
524
525 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
526 enum i9xx_plane_id i9xx_plane)
527 {
528 u32 dsparb = I915_READ(DSPARB);
529 int size;
530
531 size = dsparb & 0x7f;
532 if (i9xx_plane == PLANE_B)
533 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
534
535 drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
536 dsparb, plane_name(i9xx_plane), size);
537
538 return size;
539 }
540
541 static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
542 enum i9xx_plane_id i9xx_plane)
543 {
544 u32 dsparb = I915_READ(DSPARB);
545 int size;
546
547 size = dsparb & 0x1ff;
548 if (i9xx_plane == PLANE_B)
549 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
550 size >>= 1; /* Convert to cachelines */
551
552 drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
553 dsparb, plane_name(i9xx_plane), size);
554
555 return size;
556 }
557
558 static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
559 enum i9xx_plane_id i9xx_plane)
560 {
561 u32 dsparb = I915_READ(DSPARB);
562 int size;
563
564 size = dsparb & 0x7f;
565 size >>= 2; /* Convert to cachelines */
566
567 drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
568 dsparb, plane_name(i9xx_plane), size);
569
570 return size;
571 }
572
573 /* Pineview has different values for various configs */
574 static const struct intel_watermark_params pnv_display_wm = {
575 .fifo_size = PINEVIEW_DISPLAY_FIFO,
576 .max_wm = PINEVIEW_MAX_WM,
577 .default_wm = PINEVIEW_DFT_WM,
578 .guard_size = PINEVIEW_GUARD_WM,
579 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
580 };
581
582 static const struct intel_watermark_params pnv_display_hplloff_wm = {
583 .fifo_size = PINEVIEW_DISPLAY_FIFO,
584 .max_wm = PINEVIEW_MAX_WM,
585 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
586 .guard_size = PINEVIEW_GUARD_WM,
587 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
588 };
589
590 static const struct intel_watermark_params pnv_cursor_wm = {
591 .fifo_size = PINEVIEW_CURSOR_FIFO,
592 .max_wm = PINEVIEW_CURSOR_MAX_WM,
593 .default_wm = PINEVIEW_CURSOR_DFT_WM,
594 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
595 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
596 };
597
598 static const struct intel_watermark_params pnv_cursor_hplloff_wm = {
599 .fifo_size = PINEVIEW_CURSOR_FIFO,
600 .max_wm = PINEVIEW_CURSOR_MAX_WM,
601 .default_wm = PINEVIEW_CURSOR_DFT_WM,
602 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
603 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
604 };
605
606 static const struct intel_watermark_params i965_cursor_wm_info = {
607 .fifo_size = I965_CURSOR_FIFO,
608 .max_wm = I965_CURSOR_MAX_WM,
609 .default_wm = I965_CURSOR_DFT_WM,
610 .guard_size = 2,
611 .cacheline_size = I915_FIFO_LINE_SIZE,
612 };
613
614 static const struct intel_watermark_params i945_wm_info = {
615 .fifo_size = I945_FIFO_SIZE,
616 .max_wm = I915_MAX_WM,
617 .default_wm = 1,
618 .guard_size = 2,
619 .cacheline_size = I915_FIFO_LINE_SIZE,
620 };
621
622 static const struct intel_watermark_params i915_wm_info = {
623 .fifo_size = I915_FIFO_SIZE,
624 .max_wm = I915_MAX_WM,
625 .default_wm = 1,
626 .guard_size = 2,
627 .cacheline_size = I915_FIFO_LINE_SIZE,
628 };
629
630 static const struct intel_watermark_params i830_a_wm_info = {
631 .fifo_size = I855GM_FIFO_SIZE,
632 .max_wm = I915_MAX_WM,
633 .default_wm = 1,
634 .guard_size = 2,
635 .cacheline_size = I830_FIFO_LINE_SIZE,
636 };
637
638 static const struct intel_watermark_params i830_bc_wm_info = {
639 .fifo_size = I855GM_FIFO_SIZE,
640 .max_wm = I915_MAX_WM/2,
641 .default_wm = 1,
642 .guard_size = 2,
643 .cacheline_size = I830_FIFO_LINE_SIZE,
644 };
645
646 static const struct intel_watermark_params i845_wm_info = {
647 .fifo_size = I830_FIFO_SIZE,
648 .max_wm = I915_MAX_WM,
649 .default_wm = 1,
650 .guard_size = 2,
651 .cacheline_size = I830_FIFO_LINE_SIZE,
652 };
653
654 /**
655 * intel_wm_method1 - Method 1 / "small buffer" watermark formula
656 * @pixel_rate: Pipe pixel rate in kHz
657 * @cpp: Plane bytes per pixel
658 * @latency: Memory wakeup latency in 0.1us units
659 *
660 * Compute the watermark using the method 1 or "small buffer"
661 * formula. The caller may additonally add extra cachelines
662 * to account for TLB misses and clock crossings.
663 *
664 * This method is concerned with the short term drain rate
665 * of the FIFO, ie. it does not account for blanking periods
666 * which would effectively reduce the average drain rate across
667 * a longer period. The name "small" refers to the fact the
668 * FIFO is relatively small compared to the amount of data
669 * fetched.
670 *
671 * The FIFO level vs. time graph might look something like:
672 *
673 * |\ |\
674 * | \ | \
675 * __---__---__ (- plane active, _ blanking)
676 * -> time
677 *
678 * or perhaps like this:
679 *
680 * |\|\ |\|\
681 * __----__----__ (- plane active, _ blanking)
682 * -> time
683 *
684 * Returns:
685 * The watermark in bytes
686 */
687 static unsigned int intel_wm_method1(unsigned int pixel_rate,
688 unsigned int cpp,
689 unsigned int latency)
690 {
691 u64 ret;
692
693 ret = mul_u32_u32(pixel_rate, cpp * latency);
694 ret = DIV_ROUND_UP_ULL(ret, 10000);
695
696 return ret;
697 }
698
699 /**
700 * intel_wm_method2 - Method 2 / "large buffer" watermark formula
701 * @pixel_rate: Pipe pixel rate in kHz
702 * @htotal: Pipe horizontal total
703 * @width: Plane width in pixels
704 * @cpp: Plane bytes per pixel
705 * @latency: Memory wakeup latency in 0.1us units
706 *
707 * Compute the watermark using the method 2 or "large buffer"
708 * formula. The caller may additonally add extra cachelines
709 * to account for TLB misses and clock crossings.
710 *
711 * This method is concerned with the long term drain rate
712 * of the FIFO, ie. it does account for blanking periods
713 * which effectively reduce the average drain rate across
714 * a longer period. The name "large" refers to the fact the
715 * FIFO is relatively large compared to the amount of data
716 * fetched.
717 *
718 * The FIFO level vs. time graph might look something like:
719 *
720 * |\___ |\___
721 * | \___ | \___
722 * | \ | \
723 * __ --__--__--__--__--__--__ (- plane active, _ blanking)
724 * -> time
725 *
726 * Returns:
727 * The watermark in bytes
728 */
729 static unsigned int intel_wm_method2(unsigned int pixel_rate,
730 unsigned int htotal,
731 unsigned int width,
732 unsigned int cpp,
733 unsigned int latency)
734 {
735 unsigned int ret;
736
737 /*
738 * FIXME remove once all users are computing
739 * watermarks in the correct place.
740 */
741 if (WARN_ON_ONCE(htotal == 0))
742 htotal = 1;
743
744 ret = (latency * pixel_rate) / (htotal * 10000);
745 ret = (ret + 1) * width * cpp;
746
747 return ret;
748 }
749
750 /**
751 * intel_calculate_wm - calculate watermark level
752 * @pixel_rate: pixel clock
753 * @wm: chip FIFO params
754 * @fifo_size: size of the FIFO buffer
755 * @cpp: bytes per pixel
756 * @latency_ns: memory latency for the platform
757 *
758 * Calculate the watermark level (the level at which the display plane will
759 * start fetching from memory again). Each chip has a different display
760 * FIFO size and allocation, so the caller needs to figure that out and pass
761 * in the correct intel_watermark_params structure.
762 *
763 * As the pixel clock runs, the FIFO will be drained at a rate that depends
764 * on the pixel size. When it reaches the watermark level, it'll start
765 * fetching FIFO line sized based chunks from memory until the FIFO fills
766 * past the watermark point. If the FIFO drains completely, a FIFO underrun
767 * will occur, and a display engine hang could result.
768 */
769 static unsigned int intel_calculate_wm(int pixel_rate,
770 const struct intel_watermark_params *wm,
771 int fifo_size, int cpp,
772 unsigned int latency_ns)
773 {
774 int entries, wm_size;
775
776 /*
777 * Note: we need to make sure we don't overflow for various clock &
778 * latency values.
779 * clocks go from a few thousand to several hundred thousand.
780 * latency is usually a few thousand
781 */
782 entries = intel_wm_method1(pixel_rate, cpp,
783 latency_ns / 100);
784 entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
785 wm->guard_size;
786 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
787
788 wm_size = fifo_size - entries;
789 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
790
791 /* Don't promote wm_size to unsigned... */
792 if (wm_size > wm->max_wm)
793 wm_size = wm->max_wm;
794 if (wm_size <= 0)
795 wm_size = wm->default_wm;
796
797 /*
798 * Bspec seems to indicate that the value shouldn't be lower than
799 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
800 * Lets go for 8 which is the burst size since certain platforms
801 * already use a hardcoded 8 (which is what the spec says should be
802 * done).
803 */
804 if (wm_size <= 8)
805 wm_size = 8;
806
807 return wm_size;
808 }
809
810 static bool is_disabling(int old, int new, int threshold)
811 {
812 return old >= threshold && new < threshold;
813 }
814
815 static bool is_enabling(int old, int new, int threshold)
816 {
817 return old < threshold && new >= threshold;
818 }
819
820 static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
821 {
822 return dev_priv->wm.max_level + 1;
823 }
824
825 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
826 const struct intel_plane_state *plane_state)
827 {
828 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
829
830 /* FIXME check the 'enable' instead */
831 if (!crtc_state->hw.active)
832 return false;
833
834 /*
835 * Treat cursor with fb as always visible since cursor updates
836 * can happen faster than the vrefresh rate, and the current
837 * watermark code doesn't handle that correctly. Cursor updates
838 * which set/clear the fb or change the cursor size are going
839 * to get throttled by intel_legacy_cursor_update() to work
840 * around this problem with the watermark code.
841 */
842 if (plane->id == PLANE_CURSOR)
843 return plane_state->hw.fb != NULL;
844 else
845 return plane_state->uapi.visible;
846 }
847
848 static bool intel_crtc_active(struct intel_crtc *crtc)
849 {
850 /* Be paranoid as we can arrive here with only partial
851 * state retrieved from the hardware during setup.
852 *
853 * We can ditch the adjusted_mode.crtc_clock check as soon
854 * as Haswell has gained clock readout/fastboot support.
855 *
856 * We can ditch the crtc->primary->state->fb check as soon as we can
857 * properly reconstruct framebuffers.
858 *
859 * FIXME: The intel_crtc->active here should be switched to
860 * crtc->state->active once we have proper CRTC states wired up
861 * for atomic.
862 */
863 return crtc->active && crtc->base.primary->state->fb &&
864 crtc->config->hw.adjusted_mode.crtc_clock;
865 }
866
867 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
868 {
869 struct intel_crtc *crtc, *enabled = NULL;
870
871 for_each_intel_crtc(&dev_priv->drm, crtc) {
872 if (intel_crtc_active(crtc)) {
873 if (enabled)
874 return NULL;
875 enabled = crtc;
876 }
877 }
878
879 return enabled;
880 }
881
882 static void pnv_update_wm(struct intel_crtc *unused_crtc)
883 {
884 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
885 struct intel_crtc *crtc;
886 const struct cxsr_latency *latency;
887 u32 reg;
888 unsigned int wm;
889
890 latency = intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
891 dev_priv->is_ddr3,
892 dev_priv->fsb_freq,
893 dev_priv->mem_freq);
894 if (!latency) {
895 drm_dbg_kms(&dev_priv->drm,
896 "Unknown FSB/MEM found, disable CxSR\n");
897 intel_set_memory_cxsr(dev_priv, false);
898 return;
899 }
900
901 crtc = single_enabled_crtc(dev_priv);
902 if (crtc) {
903 const struct drm_display_mode *pipe_mode =
904 &crtc->config->hw.pipe_mode;
905 const struct drm_framebuffer *fb =
906 crtc->base.primary->state->fb;
907 int cpp = fb->format->cpp[0];
908 int clock = pipe_mode->crtc_clock;
909
910 /* Display SR */
911 wm = intel_calculate_wm(clock, &pnv_display_wm,
912 pnv_display_wm.fifo_size,
913 cpp, latency->display_sr);
914 reg = I915_READ(DSPFW1);
915 reg &= ~DSPFW_SR_MASK;
916 reg |= FW_WM(wm, SR);
917 I915_WRITE(DSPFW1, reg);
918 drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
919
920 /* cursor SR */
921 wm = intel_calculate_wm(clock, &pnv_cursor_wm,
922 pnv_display_wm.fifo_size,
923 4, latency->cursor_sr);
924 reg = I915_READ(DSPFW3);
925 reg &= ~DSPFW_CURSOR_SR_MASK;
926 reg |= FW_WM(wm, CURSOR_SR);
927 I915_WRITE(DSPFW3, reg);
928
929 /* Display HPLL off SR */
930 wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
931 pnv_display_hplloff_wm.fifo_size,
932 cpp, latency->display_hpll_disable);
933 reg = I915_READ(DSPFW3);
934 reg &= ~DSPFW_HPLL_SR_MASK;
935 reg |= FW_WM(wm, HPLL_SR);
936 I915_WRITE(DSPFW3, reg);
937
938 /* cursor HPLL off SR */
939 wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
940 pnv_display_hplloff_wm.fifo_size,
941 4, latency->cursor_hpll_disable);
942 reg = I915_READ(DSPFW3);
943 reg &= ~DSPFW_HPLL_CURSOR_MASK;
944 reg |= FW_WM(wm, HPLL_CURSOR);
945 I915_WRITE(DSPFW3, reg);
946 drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
947
948 intel_set_memory_cxsr(dev_priv, true);
949 } else {
950 intel_set_memory_cxsr(dev_priv, false);
951 }
952 }
953
954 /*
955 * Documentation says:
956 * "If the line size is small, the TLB fetches can get in the way of the
957 * data fetches, causing some lag in the pixel data return which is not
958 * accounted for in the above formulas. The following adjustment only
959 * needs to be applied if eight whole lines fit in the buffer at once.
960 * The WM is adjusted upwards by the difference between the FIFO size
961 * and the size of 8 whole lines. This adjustment is always performed
962 * in the actual pixel depth regardless of whether FBC is enabled or not."
963 */
964 static unsigned int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)
965 {
966 int tlb_miss = fifo_size * 64 - width * cpp * 8;
967
968 return max(0, tlb_miss);
969 }
970
971 static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
972 const struct g4x_wm_values *wm)
973 {
974 enum pipe pipe;
975
976 for_each_pipe(dev_priv, pipe)
977 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
978
979 I915_WRITE(DSPFW1,
980 FW_WM(wm->sr.plane, SR) |
981 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
982 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
983 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
984 I915_WRITE(DSPFW2,
985 (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
986 FW_WM(wm->sr.fbc, FBC_SR) |
987 FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
988 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
989 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
990 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
991 I915_WRITE(DSPFW3,
992 (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
993 FW_WM(wm->sr.cursor, CURSOR_SR) |
994 FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
995 FW_WM(wm->hpll.plane, HPLL_SR));
996
997 POSTING_READ(DSPFW1);
998 }
999
1000 #define FW_WM_VLV(value, plane) \
1001 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
1002
1003 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
1004 const struct vlv_wm_values *wm)
1005 {
1006 enum pipe pipe;
1007
1008 for_each_pipe(dev_priv, pipe) {
1009 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
1010
1011 I915_WRITE(VLV_DDL(pipe),
1012 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
1013 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
1014 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
1015 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
1016 }
1017
1018 /*
1019 * Zero the (unused) WM1 watermarks, and also clear all the
1020 * high order bits so that there are no out of bounds values
1021 * present in the registers during the reprogramming.
1022 */
1023 I915_WRITE(DSPHOWM, 0);
1024 I915_WRITE(DSPHOWM1, 0);
1025 I915_WRITE(DSPFW4, 0);
1026 I915_WRITE(DSPFW5, 0);
1027 I915_WRITE(DSPFW6, 0);
1028
1029 I915_WRITE(DSPFW1,
1030 FW_WM(wm->sr.plane, SR) |
1031 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
1032 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
1033 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
1034 I915_WRITE(DSPFW2,
1035 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
1036 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
1037 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1038 I915_WRITE(DSPFW3,
1039 FW_WM(wm->sr.cursor, CURSOR_SR));
1040
1041 if (IS_CHERRYVIEW(dev_priv)) {
1042 I915_WRITE(DSPFW7_CHV,
1043 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1044 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1045 I915_WRITE(DSPFW8_CHV,
1046 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
1047 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
1048 I915_WRITE(DSPFW9_CHV,
1049 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
1050 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
1051 I915_WRITE(DSPHOWM,
1052 FW_WM(wm->sr.plane >> 9, SR_HI) |
1053 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
1054 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
1055 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1056 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1057 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1058 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1059 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1060 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1061 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1062 } else {
1063 I915_WRITE(DSPFW7,
1064 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1065 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1066 I915_WRITE(DSPHOWM,
1067 FW_WM(wm->sr.plane >> 9, SR_HI) |
1068 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1069 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1070 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1071 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1072 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1073 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1074 }
1075
1076 POSTING_READ(DSPFW1);
1077 }
1078
1079 #undef FW_WM_VLV
1080
1081 static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
1082 {
1083 /* all latencies in usec */
1084 dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
1085 dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
1086 dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
1087
1088 dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
1089 }
1090
1091 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
1092 {
1093 /*
1094 * DSPCNTR[13] supposedly controls whether the
1095 * primary plane can use the FIFO space otherwise
1096 * reserved for the sprite plane. It's not 100% clear
1097 * what the actual FIFO size is, but it looks like we
1098 * can happily set both primary and sprite watermarks
1099 * up to 127 cachelines. So that would seem to mean
1100 * that either DSPCNTR[13] doesn't do anything, or that
1101 * the total FIFO is >= 256 cachelines in size. Either
1102 * way, we don't seem to have to worry about this
1103 * repartitioning as the maximum watermark value the
1104 * register can hold for each plane is lower than the
1105 * minimum FIFO size.
1106 */
1107 switch (plane_id) {
1108 case PLANE_CURSOR:
1109 return 63;
1110 case PLANE_PRIMARY:
1111 return level == G4X_WM_LEVEL_NORMAL ? 127 : 511;
1112 case PLANE_SPRITE0:
1113 return level == G4X_WM_LEVEL_NORMAL ? 127 : 0;
1114 default:
1115 MISSING_CASE(plane_id);
1116 return 0;
1117 }
1118 }
1119
1120 static int g4x_fbc_fifo_size(int level)
1121 {
1122 switch (level) {
1123 case G4X_WM_LEVEL_SR:
1124 return 7;
1125 case G4X_WM_LEVEL_HPLL:
1126 return 15;
1127 default:
1128 MISSING_CASE(level);
1129 return 0;
1130 }
1131 }
1132
1133 static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
1134 const struct intel_plane_state *plane_state,
1135 int level)
1136 {
1137 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1138 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1139 const struct drm_display_mode *pipe_mode =
1140 &crtc_state->hw.pipe_mode;
1141 unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
1142 unsigned int clock, htotal, cpp, width, wm;
1143
1144 if (latency == 0)
1145 return USHRT_MAX;
1146
1147 if (!intel_wm_plane_visible(crtc_state, plane_state))
1148 return 0;
1149
1150 cpp = plane_state->hw.fb->format->cpp[0];
1151
1152 /*
1153 * Not 100% sure which way ELK should go here as the
1154 * spec only says CL/CTG should assume 32bpp and BW
1155 * doesn't need to. But as these things followed the
1156 * mobile vs. desktop lines on gen3 as well, let's
1157 * assume ELK doesn't need this.
1158 *
1159 * The spec also fails to list such a restriction for
1160 * the HPLL watermark, which seems a little strange.
1161 * Let's use 32bpp for the HPLL watermark as well.
1162 */
1163 if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY &&
1164 level != G4X_WM_LEVEL_NORMAL)
1165 cpp = max(cpp, 4u);
1166
1167 clock = pipe_mode->crtc_clock;
1168 htotal = pipe_mode->crtc_htotal;
1169
1170 width = drm_rect_width(&plane_state->uapi.dst);
1171
1172 if (plane->id == PLANE_CURSOR) {
1173 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1174 } else if (plane->id == PLANE_PRIMARY &&
1175 level == G4X_WM_LEVEL_NORMAL) {
1176 wm = intel_wm_method1(clock, cpp, latency);
1177 } else {
1178 unsigned int small, large;
1179
1180 small = intel_wm_method1(clock, cpp, latency);
1181 large = intel_wm_method2(clock, htotal, width, cpp, latency);
1182
1183 wm = min(small, large);
1184 }
1185
1186 wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
1187 width, cpp);
1188
1189 wm = DIV_ROUND_UP(wm, 64) + 2;
1190
1191 return min_t(unsigned int, wm, USHRT_MAX);
1192 }
1193
1194 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1195 int level, enum plane_id plane_id, u16 value)
1196 {
1197 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1198 bool dirty = false;
1199
1200 for (; level < intel_wm_num_levels(dev_priv); level++) {
1201 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1202
1203 dirty |= raw->plane[plane_id] != value;
1204 raw->plane[plane_id] = value;
1205 }
1206
1207 return dirty;
1208 }
1209
1210 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
1211 int level, u16 value)
1212 {
1213 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1214 bool dirty = false;
1215
1216 /* NORMAL level doesn't have an FBC watermark */
1217 level = max(level, G4X_WM_LEVEL_SR);
1218
1219 for (; level < intel_wm_num_levels(dev_priv); level++) {
1220 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1221
1222 dirty |= raw->fbc != value;
1223 raw->fbc = value;
1224 }
1225
1226 return dirty;
1227 }
1228
1229 static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
1230 const struct intel_plane_state *plane_state,
1231 u32 pri_val);
1232
1233 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1234 const struct intel_plane_state *plane_state)
1235 {
1236 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1237 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1238 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1239 enum plane_id plane_id = plane->id;
1240 bool dirty = false;
1241 int level;
1242
1243 if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1244 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1245 if (plane_id == PLANE_PRIMARY)
1246 dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);
1247 goto out;
1248 }
1249
1250 for (level = 0; level < num_levels; level++) {
1251 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1252 int wm, max_wm;
1253
1254 wm = g4x_compute_wm(crtc_state, plane_state, level);
1255 max_wm = g4x_plane_fifo_size(plane_id, level);
1256
1257 if (wm > max_wm)
1258 break;
1259
1260 dirty |= raw->plane[plane_id] != wm;
1261 raw->plane[plane_id] = wm;
1262
1263 if (plane_id != PLANE_PRIMARY ||
1264 level == G4X_WM_LEVEL_NORMAL)
1265 continue;
1266
1267 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1268 raw->plane[plane_id]);
1269 max_wm = g4x_fbc_fifo_size(level);
1270
1271 /*
1272 * FBC wm is not mandatory as we
1273 * can always just disable its use.
1274 */
1275 if (wm > max_wm)
1276 wm = USHRT_MAX;
1277
1278 dirty |= raw->fbc != wm;
1279 raw->fbc = wm;
1280 }
1281
1282 /* mark watermarks as invalid */
1283 dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1284
1285 if (plane_id == PLANE_PRIMARY)
1286 dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
1287
1288 out:
1289 if (dirty) {
1290 drm_dbg_kms(&dev_priv->drm,
1291 "%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1292 plane->base.name,
1293 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1294 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1295 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1296
1297 if (plane_id == PLANE_PRIMARY)
1298 drm_dbg_kms(&dev_priv->drm,
1299 "FBC watermarks: SR=%d, HPLL=%d\n",
1300 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1301 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1302 }
1303
1304 return dirty;
1305 }
1306
1307 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1308 enum plane_id plane_id, int level)
1309 {
1310 const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1311
1312 return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
1313 }
1314
1315 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
1316 int level)
1317 {
1318 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1319
1320 if (level > dev_priv->wm.max_level)
1321 return false;
1322
1323 return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1324 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1325 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1326 }
1327
1328 /* mark all levels starting from 'level' as invalid */
1329 static void g4x_invalidate_wms(struct intel_crtc *crtc,
1330 struct g4x_wm_state *wm_state, int level)
1331 {
1332 if (level <= G4X_WM_LEVEL_NORMAL) {
1333 enum plane_id plane_id;
1334
1335 for_each_plane_id_on_crtc(crtc, plane_id)
1336 wm_state->wm.plane[plane_id] = USHRT_MAX;
1337 }
1338
1339 if (level <= G4X_WM_LEVEL_SR) {
1340 wm_state->cxsr = false;
1341 wm_state->sr.cursor = USHRT_MAX;
1342 wm_state->sr.plane = USHRT_MAX;
1343 wm_state->sr.fbc = USHRT_MAX;
1344 }
1345
1346 if (level <= G4X_WM_LEVEL_HPLL) {
1347 wm_state->hpll_en = false;
1348 wm_state->hpll.cursor = USHRT_MAX;
1349 wm_state->hpll.plane = USHRT_MAX;
1350 wm_state->hpll.fbc = USHRT_MAX;
1351 }
1352 }
1353
1354 static bool g4x_compute_fbc_en(const struct g4x_wm_state *wm_state,
1355 int level)
1356 {
1357 if (level < G4X_WM_LEVEL_SR)
1358 return false;
1359
1360 if (level >= G4X_WM_LEVEL_SR &&
1361 wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
1362 return false;
1363
1364 if (level >= G4X_WM_LEVEL_HPLL &&
1365 wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1366 return false;
1367
1368 return true;
1369 }
1370
1371 static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1372 {
1373 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1374 struct intel_atomic_state *state =
1375 to_intel_atomic_state(crtc_state->uapi.state);
1376 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
1377 int num_active_planes = hweight8(crtc_state->active_planes &
1378 ~BIT(PLANE_CURSOR));
1379 const struct g4x_pipe_wm *raw;
1380 const struct intel_plane_state *old_plane_state;
1381 const struct intel_plane_state *new_plane_state;
1382 struct intel_plane *plane;
1383 enum plane_id plane_id;
1384 int i, level;
1385 unsigned int dirty = 0;
1386
1387 for_each_oldnew_intel_plane_in_state(state, plane,
1388 old_plane_state,
1389 new_plane_state, i) {
1390 if (new_plane_state->hw.crtc != &crtc->base &&
1391 old_plane_state->hw.crtc != &crtc->base)
1392 continue;
1393
1394 if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
1395 dirty |= BIT(plane->id);
1396 }
1397
1398 if (!dirty)
1399 return 0;
1400
1401 level = G4X_WM_LEVEL_NORMAL;
1402 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1403 goto out;
1404
1405 raw = &crtc_state->wm.g4x.raw[level];
1406 for_each_plane_id_on_crtc(crtc, plane_id)
1407 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1408
1409 level = G4X_WM_LEVEL_SR;
1410 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1411 goto out;
1412
1413 raw = &crtc_state->wm.g4x.raw[level];
1414 wm_state->sr.plane = raw->plane[PLANE_PRIMARY];
1415 wm_state->sr.cursor = raw->plane[PLANE_CURSOR];
1416 wm_state->sr.fbc = raw->fbc;
1417
1418 wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
1419
1420 level = G4X_WM_LEVEL_HPLL;
1421 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1422 goto out;
1423
1424 raw = &crtc_state->wm.g4x.raw[level];
1425 wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];
1426 wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];
1427 wm_state->hpll.fbc = raw->fbc;
1428
1429 wm_state->hpll_en = wm_state->cxsr;
1430
1431 level++;
1432
1433 out:
1434 if (level == G4X_WM_LEVEL_NORMAL)
1435 return -EINVAL;
1436
1437 /* invalidate the higher levels */
1438 g4x_invalidate_wms(crtc, wm_state, level);
1439
1440 /*
1441 * Determine if the FBC watermark(s) can be used. IF
1442 * this isn't the case we prefer to disable the FBC
1443 * watermark(s) rather than disable the SR/HPLL
1444 * level(s) entirely. 'level-1' is the highest valid
1445 * level here.
1446 */
1447 wm_state->fbc_en = g4x_compute_fbc_en(wm_state, level - 1);
1448
1449 return 0;
1450 }
1451
1452 static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
1453 {
1454 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1455 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1456 struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
1457 const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
1458 struct intel_atomic_state *intel_state =
1459 to_intel_atomic_state(new_crtc_state->uapi.state);
1460 const struct intel_crtc_state *old_crtc_state =
1461 intel_atomic_get_old_crtc_state(intel_state, crtc);
1462 const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
1463 enum plane_id plane_id;
1464
1465 if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
1466 *intermediate = *optimal;
1467
1468 intermediate->cxsr = false;
1469 intermediate->hpll_en = false;
1470 goto out;
1471 }
1472
1473 intermediate->cxsr = optimal->cxsr && active->cxsr &&
1474 !new_crtc_state->disable_cxsr;
1475 intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&
1476 !new_crtc_state->disable_cxsr;
1477 intermediate->fbc_en = optimal->fbc_en && active->fbc_en;
1478
1479 for_each_plane_id_on_crtc(crtc, plane_id) {
1480 intermediate->wm.plane[plane_id] =
1481 max(optimal->wm.plane[plane_id],
1482 active->wm.plane[plane_id]);
1483
1484 drm_WARN_ON(&dev_priv->drm, intermediate->wm.plane[plane_id] >
1485 g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
1486 }
1487
1488 intermediate->sr.plane = max(optimal->sr.plane,
1489 active->sr.plane);
1490 intermediate->sr.cursor = max(optimal->sr.cursor,
1491 active->sr.cursor);
1492 intermediate->sr.fbc = max(optimal->sr.fbc,
1493 active->sr.fbc);
1494
1495 intermediate->hpll.plane = max(optimal->hpll.plane,
1496 active->hpll.plane);
1497 intermediate->hpll.cursor = max(optimal->hpll.cursor,
1498 active->hpll.cursor);
1499 intermediate->hpll.fbc = max(optimal->hpll.fbc,
1500 active->hpll.fbc);
1501
1502 drm_WARN_ON(&dev_priv->drm,
1503 (intermediate->sr.plane >
1504 g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
1505 intermediate->sr.cursor >
1506 g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
1507 intermediate->cxsr);
1508 drm_WARN_ON(&dev_priv->drm,
1509 (intermediate->sr.plane >
1510 g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
1511 intermediate->sr.cursor >
1512 g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
1513 intermediate->hpll_en);
1514
1515 drm_WARN_ON(&dev_priv->drm,
1516 intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
1517 intermediate->fbc_en && intermediate->cxsr);
1518 drm_WARN_ON(&dev_priv->drm,
1519 intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
1520 intermediate->fbc_en && intermediate->hpll_en);
1521
1522 out:
1523 /*
1524 * If our intermediate WM are identical to the final WM, then we can
1525 * omit the post-vblank programming; only update if it's different.
1526 */
1527 if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
1528 new_crtc_state->wm.need_postvbl_update = true;
1529
1530 return 0;
1531 }
1532
1533 static void g4x_merge_wm(struct drm_i915_private *dev_priv,
1534 struct g4x_wm_values *wm)
1535 {
1536 struct intel_crtc *crtc;
1537 int num_active_pipes = 0;
1538
1539 wm->cxsr = true;
1540 wm->hpll_en = true;
1541 wm->fbc_en = true;
1542
1543 for_each_intel_crtc(&dev_priv->drm, crtc) {
1544 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1545
1546 if (!crtc->active)
1547 continue;
1548
1549 if (!wm_state->cxsr)
1550 wm->cxsr = false;
1551 if (!wm_state->hpll_en)
1552 wm->hpll_en = false;
1553 if (!wm_state->fbc_en)
1554 wm->fbc_en = false;
1555
1556 num_active_pipes++;
1557 }
1558
1559 if (num_active_pipes != 1) {
1560 wm->cxsr = false;
1561 wm->hpll_en = false;
1562 wm->fbc_en = false;
1563 }
1564
1565 for_each_intel_crtc(&dev_priv->drm, crtc) {
1566 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1567 enum pipe pipe = crtc->pipe;
1568
1569 wm->pipe[pipe] = wm_state->wm;
1570 if (crtc->active && wm->cxsr)
1571 wm->sr = wm_state->sr;
1572 if (crtc->active && wm->hpll_en)
1573 wm->hpll = wm_state->hpll;
1574 }
1575 }
1576
1577 static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
1578 {
1579 struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
1580 struct g4x_wm_values new_wm = {};
1581
1582 g4x_merge_wm(dev_priv, &new_wm);
1583
1584 if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
1585 return;
1586
1587 if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1588 _intel_set_memory_cxsr(dev_priv, false);
1589
1590 g4x_write_wm_values(dev_priv, &new_wm);
1591
1592 if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1593 _intel_set_memory_cxsr(dev_priv, true);
1594
1595 *old_wm = new_wm;
1596 }
1597
1598 static void g4x_initial_watermarks(struct intel_atomic_state *state,
1599 struct intel_crtc *crtc)
1600 {
1601 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1602 const struct intel_crtc_state *crtc_state =
1603 intel_atomic_get_new_crtc_state(state, crtc);
1604
1605 mutex_lock(&dev_priv->wm.wm_mutex);
1606 crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1607 g4x_program_watermarks(dev_priv);
1608 mutex_unlock(&dev_priv->wm.wm_mutex);
1609 }
1610
1611 static void g4x_optimize_watermarks(struct intel_atomic_state *state,
1612 struct intel_crtc *crtc)
1613 {
1614 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1615 const struct intel_crtc_state *crtc_state =
1616 intel_atomic_get_new_crtc_state(state, crtc);
1617
1618 if (!crtc_state->wm.need_postvbl_update)
1619 return;
1620
1621 mutex_lock(&dev_priv->wm.wm_mutex);
1622 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1623 g4x_program_watermarks(dev_priv);
1624 mutex_unlock(&dev_priv->wm.wm_mutex);
1625 }
1626
1627 /* latency must be in 0.1us units. */
1628 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
1629 unsigned int htotal,
1630 unsigned int width,
1631 unsigned int cpp,
1632 unsigned int latency)
1633 {
1634 unsigned int ret;
1635
1636 ret = intel_wm_method2(pixel_rate, htotal,
1637 width, cpp, latency);
1638 ret = DIV_ROUND_UP(ret, 64);
1639
1640 return ret;
1641 }
1642
1643 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
1644 {
1645 /* all latencies in usec */
1646 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1647
1648 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1649
1650 if (IS_CHERRYVIEW(dev_priv)) {
1651 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1652 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1653
1654 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1655 }
1656 }
1657
1658 static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
1659 const struct intel_plane_state *plane_state,
1660 int level)
1661 {
1662 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1663 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1664 const struct drm_display_mode *pipe_mode =
1665 &crtc_state->hw.pipe_mode;
1666 unsigned int clock, htotal, cpp, width, wm;
1667
1668 if (dev_priv->wm.pri_latency[level] == 0)
1669 return USHRT_MAX;
1670
1671 if (!intel_wm_plane_visible(crtc_state, plane_state))
1672 return 0;
1673
1674 cpp = plane_state->hw.fb->format->cpp[0];
1675 clock = pipe_mode->crtc_clock;
1676 htotal = pipe_mode->crtc_htotal;
1677 width = crtc_state->pipe_src_w;
1678
1679 if (plane->id == PLANE_CURSOR) {
1680 /*
1681 * FIXME the formula gives values that are
1682 * too big for the cursor FIFO, and hence we
1683 * would never be able to use cursors. For
1684 * now just hardcode the watermark.
1685 */
1686 wm = 63;
1687 } else {
1688 wm = vlv_wm_method2(clock, htotal, width, cpp,
1689 dev_priv->wm.pri_latency[level] * 10);
1690 }
1691
1692 return min_t(unsigned int, wm, USHRT_MAX);
1693 }
1694
1695 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
1696 {
1697 return (active_planes & (BIT(PLANE_SPRITE0) |
1698 BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
1699 }
1700
1701 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
1702 {
1703 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1704 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1705 const struct g4x_pipe_wm *raw =
1706 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1707 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1708 unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1709 int num_active_planes = hweight8(active_planes);
1710 const int fifo_size = 511;
1711 int fifo_extra, fifo_left = fifo_size;
1712 int sprite0_fifo_extra = 0;
1713 unsigned int total_rate;
1714 enum plane_id plane_id;
1715
1716 /*
1717 * When enabling sprite0 after sprite1 has already been enabled
1718 * we tend to get an underrun unless sprite0 already has some
1719 * FIFO space allcoated. Hence we always allocate at least one
1720 * cacheline for sprite0 whenever sprite1 is enabled.
1721 *
1722 * All other plane enable sequences appear immune to this problem.
1723 */
1724 if (vlv_need_sprite0_fifo_workaround(active_planes))
1725 sprite0_fifo_extra = 1;
1726
1727 total_rate = raw->plane[PLANE_PRIMARY] +
1728 raw->plane[PLANE_SPRITE0] +
1729 raw->plane[PLANE_SPRITE1] +
1730 sprite0_fifo_extra;
1731
1732 if (total_rate > fifo_size)
1733 return -EINVAL;
1734
1735 if (total_rate == 0)
1736 total_rate = 1;
1737
1738 for_each_plane_id_on_crtc(crtc, plane_id) {
1739 unsigned int rate;
1740
1741 if ((active_planes & BIT(plane_id)) == 0) {
1742 fifo_state->plane[plane_id] = 0;
1743 continue;
1744 }
1745
1746 rate = raw->plane[plane_id];
1747 fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1748 fifo_left -= fifo_state->plane[plane_id];
1749 }
1750
1751 fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;
1752 fifo_left -= sprite0_fifo_extra;
1753
1754 fifo_state->plane[PLANE_CURSOR] = 63;
1755
1756 fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);
1757
1758 /* spread the remainder evenly */
1759 for_each_plane_id_on_crtc(crtc, plane_id) {
1760 int plane_extra;
1761
1762 if (fifo_left == 0)
1763 break;
1764
1765 if ((active_planes & BIT(plane_id)) == 0)
1766 continue;
1767
1768 plane_extra = min(fifo_extra, fifo_left);
1769 fifo_state->plane[plane_id] += plane_extra;
1770 fifo_left -= plane_extra;
1771 }
1772
1773 drm_WARN_ON(&dev_priv->drm, active_planes != 0 && fifo_left != 0);
1774
1775 /* give it all to the first plane if none are active */
1776 if (active_planes == 0) {
1777 drm_WARN_ON(&dev_priv->drm, fifo_left != fifo_size);
1778 fifo_state->plane[PLANE_PRIMARY] = fifo_left;
1779 }
1780
1781 return 0;
1782 }
1783
1784 /* mark all levels starting from 'level' as invalid */
1785 static void vlv_invalidate_wms(struct intel_crtc *crtc,
1786 struct vlv_wm_state *wm_state, int level)
1787 {
1788 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1789
1790 for (; level < intel_wm_num_levels(dev_priv); level++) {
1791 enum plane_id plane_id;
1792
1793 for_each_plane_id_on_crtc(crtc, plane_id)
1794 wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1795
1796 wm_state->sr[level].cursor = USHRT_MAX;
1797 wm_state->sr[level].plane = USHRT_MAX;
1798 }
1799 }
1800
1801 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1802 {
1803 if (wm > fifo_size)
1804 return USHRT_MAX;
1805 else
1806 return fifo_size - wm;
1807 }
1808
1809 /*
1810 * Starting from 'level' set all higher
1811 * levels to 'value' in the "raw" watermarks.
1812 */
1813 static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1814 int level, enum plane_id plane_id, u16 value)
1815 {
1816 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1817 int num_levels = intel_wm_num_levels(dev_priv);
1818 bool dirty = false;
1819
1820 for (; level < num_levels; level++) {
1821 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1822
1823 dirty |= raw->plane[plane_id] != value;
1824 raw->plane[plane_id] = value;
1825 }
1826
1827 return dirty;
1828 }
1829
1830 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1831 const struct intel_plane_state *plane_state)
1832 {
1833 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1834 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1835 enum plane_id plane_id = plane->id;
1836 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1837 int level;
1838 bool dirty = false;
1839
1840 if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1841 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1842 goto out;
1843 }
1844
1845 for (level = 0; level < num_levels; level++) {
1846 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1847 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1848 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1849
1850 if (wm > max_wm)
1851 break;
1852
1853 dirty |= raw->plane[plane_id] != wm;
1854 raw->plane[plane_id] = wm;
1855 }
1856
1857 /* mark all higher levels as invalid */
1858 dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1859
1860 out:
1861 if (dirty)
1862 drm_dbg_kms(&dev_priv->drm,
1863 "%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1864 plane->base.name,
1865 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1866 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1867 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1868
1869 return dirty;
1870 }
1871
1872 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1873 enum plane_id plane_id, int level)
1874 {
1875 const struct g4x_pipe_wm *raw =
1876 &crtc_state->wm.vlv.raw[level];
1877 const struct vlv_fifo_state *fifo_state =
1878 &crtc_state->wm.vlv.fifo_state;
1879
1880 return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1881 }
1882
1883 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
1884 {
1885 return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1886 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1887 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
1888 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1889 }
1890
1891 static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1892 {
1893 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1894 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1895 struct intel_atomic_state *state =
1896 to_intel_atomic_state(crtc_state->uapi.state);
1897 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1898 const struct vlv_fifo_state *fifo_state =
1899 &crtc_state->wm.vlv.fifo_state;
1900 int num_active_planes = hweight8(crtc_state->active_planes &
1901 ~BIT(PLANE_CURSOR));
1902 bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
1903 const struct intel_plane_state *old_plane_state;
1904 const struct intel_plane_state *new_plane_state;
1905 struct intel_plane *plane;
1906 enum plane_id plane_id;
1907 int level, ret, i;
1908 unsigned int dirty = 0;
1909
1910 for_each_oldnew_intel_plane_in_state(state, plane,
1911 old_plane_state,
1912 new_plane_state, i) {
1913 if (new_plane_state->hw.crtc != &crtc->base &&
1914 old_plane_state->hw.crtc != &crtc->base)
1915 continue;
1916
1917 if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
1918 dirty |= BIT(plane->id);
1919 }
1920
1921 /*
1922 * DSPARB registers may have been reset due to the
1923 * power well being turned off. Make sure we restore
1924 * them to a consistent state even if no primary/sprite
1925 * planes are initially active.
1926 */
1927 if (needs_modeset)
1928 crtc_state->fifo_changed = true;
1929
1930 if (!dirty)
1931 return 0;
1932
1933 /* cursor changes don't warrant a FIFO recompute */
1934 if (dirty & ~BIT(PLANE_CURSOR)) {
1935 const struct intel_crtc_state *old_crtc_state =
1936 intel_atomic_get_old_crtc_state(state, crtc);
1937 const struct vlv_fifo_state *old_fifo_state =
1938 &old_crtc_state->wm.vlv.fifo_state;
1939
1940 ret = vlv_compute_fifo(crtc_state);
1941 if (ret)
1942 return ret;
1943
1944 if (needs_modeset ||
1945 memcmp(old_fifo_state, fifo_state,
1946 sizeof(*fifo_state)) != 0)
1947 crtc_state->fifo_changed = true;
1948 }
1949
1950 /* initially allow all levels */
1951 wm_state->num_levels = intel_wm_num_levels(dev_priv);
1952 /*
1953 * Note that enabling cxsr with no primary/sprite planes
1954 * enabled can wedge the pipe. Hence we only allow cxsr
1955 * with exactly one enabled primary/sprite plane.
1956 */
1957 wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1958
1959 for (level = 0; level < wm_state->num_levels; level++) {
1960 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1961 const int sr_fifo_size = INTEL_NUM_PIPES(dev_priv) * 512 - 1;
1962
1963 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
1964 break;
1965
1966 for_each_plane_id_on_crtc(crtc, plane_id) {
1967 wm_state->wm[level].plane[plane_id] =
1968 vlv_invert_wm_value(raw->plane[plane_id],
1969 fifo_state->plane[plane_id]);
1970 }
1971
1972 wm_state->sr[level].plane =
1973 vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
1974 raw->plane[PLANE_SPRITE0],
1975 raw->plane[PLANE_SPRITE1]),
1976 sr_fifo_size);
1977
1978 wm_state->sr[level].cursor =
1979 vlv_invert_wm_value(raw->plane[PLANE_CURSOR],
1980 63);
1981 }
1982
1983 if (level == 0)
1984 return -EINVAL;
1985
1986 /* limit to only levels we can actually handle */
1987 wm_state->num_levels = level;
1988
1989 /* invalidate the higher levels */
1990 vlv_invalidate_wms(crtc, wm_state, level);
1991
1992 return 0;
1993 }
1994
1995 #define VLV_FIFO(plane, value) \
1996 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1997
1998 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
1999 struct intel_crtc *crtc)
2000 {
2001 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2002 struct intel_uncore *uncore = &dev_priv->uncore;
2003 const struct intel_crtc_state *crtc_state =
2004 intel_atomic_get_new_crtc_state(state, crtc);
2005 const struct vlv_fifo_state *fifo_state =
2006 &crtc_state->wm.vlv.fifo_state;
2007 int sprite0_start, sprite1_start, fifo_size;
2008 u32 dsparb, dsparb2, dsparb3;
2009
2010 if (!crtc_state->fifo_changed)
2011 return;
2012
2013 sprite0_start = fifo_state->plane[PLANE_PRIMARY];
2014 sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
2015 fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
2016
2017 drm_WARN_ON(&dev_priv->drm, fifo_state->plane[PLANE_CURSOR] != 63);
2018 drm_WARN_ON(&dev_priv->drm, fifo_size != 511);
2019
2020 trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
2021
2022 /*
2023 * uncore.lock serves a double purpose here. It allows us to
2024 * use the less expensive I915_{READ,WRITE}_FW() functions, and
2025 * it protects the DSPARB registers from getting clobbered by
2026 * parallel updates from multiple pipes.
2027 *
2028 * intel_pipe_update_start() has already disabled interrupts
2029 * for us, so a plain spin_lock() is sufficient here.
2030 */
2031 spin_lock(&uncore->lock);
2032
2033 switch (crtc->pipe) {
2034 case PIPE_A:
2035 dsparb = intel_uncore_read_fw(uncore, DSPARB);
2036 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2037
2038 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
2039 VLV_FIFO(SPRITEB, 0xff));
2040 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
2041 VLV_FIFO(SPRITEB, sprite1_start));
2042
2043 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
2044 VLV_FIFO(SPRITEB_HI, 0x1));
2045 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
2046 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
2047
2048 intel_uncore_write_fw(uncore, DSPARB, dsparb);
2049 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2050 break;
2051 case PIPE_B:
2052 dsparb = intel_uncore_read_fw(uncore, DSPARB);
2053 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2054
2055 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
2056 VLV_FIFO(SPRITED, 0xff));
2057 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
2058 VLV_FIFO(SPRITED, sprite1_start));
2059
2060 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
2061 VLV_FIFO(SPRITED_HI, 0xff));
2062 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
2063 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
2064
2065 intel_uncore_write_fw(uncore, DSPARB, dsparb);
2066 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2067 break;
2068 case PIPE_C:
2069 dsparb3 = intel_uncore_read_fw(uncore, DSPARB3);
2070 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2071
2072 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
2073 VLV_FIFO(SPRITEF, 0xff));
2074 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
2075 VLV_FIFO(SPRITEF, sprite1_start));
2076
2077 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
2078 VLV_FIFO(SPRITEF_HI, 0xff));
2079 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
2080 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
2081
2082 intel_uncore_write_fw(uncore, DSPARB3, dsparb3);
2083 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2084 break;
2085 default:
2086 break;
2087 }
2088
2089 intel_uncore_posting_read_fw(uncore, DSPARB);
2090
2091 spin_unlock(&uncore->lock);
2092 }
2093
2094 #undef VLV_FIFO
2095
2096 static int vlv_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
2097 {
2098 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
2099 struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
2100 const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
2101 struct intel_atomic_state *intel_state =
2102 to_intel_atomic_state(new_crtc_state->uapi.state);
2103 const struct intel_crtc_state *old_crtc_state =
2104 intel_atomic_get_old_crtc_state(intel_state, crtc);
2105 const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
2106 int level;
2107
2108 if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
2109 *intermediate = *optimal;
2110
2111 intermediate->cxsr = false;
2112 goto out;
2113 }
2114
2115 intermediate->num_levels = min(optimal->num_levels, active->num_levels);
2116 intermediate->cxsr = optimal->cxsr && active->cxsr &&
2117 !new_crtc_state->disable_cxsr;
2118
2119 for (level = 0; level < intermediate->num_levels; level++) {
2120 enum plane_id plane_id;
2121
2122 for_each_plane_id_on_crtc(crtc, plane_id) {
2123 intermediate->wm[level].plane[plane_id] =
2124 min(optimal->wm[level].plane[plane_id],
2125 active->wm[level].plane[plane_id]);
2126 }
2127
2128 intermediate->sr[level].plane = min(optimal->sr[level].plane,
2129 active->sr[level].plane);
2130 intermediate->sr[level].cursor = min(optimal->sr[level].cursor,
2131 active->sr[level].cursor);
2132 }
2133
2134 vlv_invalidate_wms(crtc, intermediate, level);
2135
2136 out:
2137 /*
2138 * If our intermediate WM are identical to the final WM, then we can
2139 * omit the post-vblank programming; only update if it's different.
2140 */
2141 if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
2142 new_crtc_state->wm.need_postvbl_update = true;
2143
2144 return 0;
2145 }
2146
2147 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
2148 struct vlv_wm_values *wm)
2149 {
2150 struct intel_crtc *crtc;
2151 int num_active_pipes = 0;
2152
2153 wm->level = dev_priv->wm.max_level;
2154 wm->cxsr = true;
2155
2156 for_each_intel_crtc(&dev_priv->drm, crtc) {
2157 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2158
2159 if (!crtc->active)
2160 continue;
2161
2162 if (!wm_state->cxsr)
2163 wm->cxsr = false;
2164
2165 num_active_pipes++;
2166 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
2167 }
2168
2169 if (num_active_pipes != 1)
2170 wm->cxsr = false;
2171
2172 if (num_active_pipes > 1)
2173 wm->level = VLV_WM_LEVEL_PM2;
2174
2175 for_each_intel_crtc(&dev_priv->drm, crtc) {
2176 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2177 enum pipe pipe = crtc->pipe;
2178
2179 wm->pipe[pipe] = wm_state->wm[wm->level];
2180 if (crtc->active && wm->cxsr)
2181 wm->sr = wm_state->sr[wm->level];
2182
2183 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2184 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2185 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2186 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
2187 }
2188 }
2189
2190 static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
2191 {
2192 struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
2193 struct vlv_wm_values new_wm = {};
2194
2195 vlv_merge_wm(dev_priv, &new_wm);
2196
2197 if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
2198 return;
2199
2200 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2201 chv_set_memory_dvfs(dev_priv, false);
2202
2203 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2204 chv_set_memory_pm5(dev_priv, false);
2205
2206 if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
2207 _intel_set_memory_cxsr(dev_priv, false);
2208
2209 vlv_write_wm_values(dev_priv, &new_wm);
2210
2211 if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
2212 _intel_set_memory_cxsr(dev_priv, true);
2213
2214 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2215 chv_set_memory_pm5(dev_priv, true);
2216
2217 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2218 chv_set_memory_dvfs(dev_priv, true);
2219
2220 *old_wm = new_wm;
2221 }
2222
2223 static void vlv_initial_watermarks(struct intel_atomic_state *state,
2224 struct intel_crtc *crtc)
2225 {
2226 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2227 const struct intel_crtc_state *crtc_state =
2228 intel_atomic_get_new_crtc_state(state, crtc);
2229
2230 mutex_lock(&dev_priv->wm.wm_mutex);
2231 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2232 vlv_program_watermarks(dev_priv);
2233 mutex_unlock(&dev_priv->wm.wm_mutex);
2234 }
2235
2236 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
2237 struct intel_crtc *crtc)
2238 {
2239 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2240 const struct intel_crtc_state *crtc_state =
2241 intel_atomic_get_new_crtc_state(state, crtc);
2242
2243 if (!crtc_state->wm.need_postvbl_update)
2244 return;
2245
2246 mutex_lock(&dev_priv->wm.wm_mutex);
2247 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2248 vlv_program_watermarks(dev_priv);
2249 mutex_unlock(&dev_priv->wm.wm_mutex);
2250 }
2251
2252 static void i965_update_wm(struct intel_crtc *unused_crtc)
2253 {
2254 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2255 struct intel_crtc *crtc;
2256 int srwm = 1;
2257 int cursor_sr = 16;
2258 bool cxsr_enabled;
2259
2260 /* Calc sr entries for one plane configs */
2261 crtc = single_enabled_crtc(dev_priv);
2262 if (crtc) {
2263 /* self-refresh has much higher latency */
2264 static const int sr_latency_ns = 12000;
2265 const struct drm_display_mode *pipe_mode =
2266 &crtc->config->hw.pipe_mode;
2267 const struct drm_framebuffer *fb =
2268 crtc->base.primary->state->fb;
2269 int clock = pipe_mode->crtc_clock;
2270 int htotal = pipe_mode->crtc_htotal;
2271 int hdisplay = crtc->config->pipe_src_w;
2272 int cpp = fb->format->cpp[0];
2273 int entries;
2274
2275 entries = intel_wm_method2(clock, htotal,
2276 hdisplay, cpp, sr_latency_ns / 100);
2277 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
2278 srwm = I965_FIFO_SIZE - entries;
2279 if (srwm < 0)
2280 srwm = 1;
2281 srwm &= 0x1ff;
2282 drm_dbg_kms(&dev_priv->drm,
2283 "self-refresh entries: %d, wm: %d\n",
2284 entries, srwm);
2285
2286 entries = intel_wm_method2(clock, htotal,
2287 crtc->base.cursor->state->crtc_w, 4,
2288 sr_latency_ns / 100);
2289 entries = DIV_ROUND_UP(entries,
2290 i965_cursor_wm_info.cacheline_size) +
2291 i965_cursor_wm_info.guard_size;
2292
2293 cursor_sr = i965_cursor_wm_info.fifo_size - entries;
2294 if (cursor_sr > i965_cursor_wm_info.max_wm)
2295 cursor_sr = i965_cursor_wm_info.max_wm;
2296
2297 drm_dbg_kms(&dev_priv->drm,
2298 "self-refresh watermark: display plane %d "
2299 "cursor %d\n", srwm, cursor_sr);
2300
2301 cxsr_enabled = true;
2302 } else {
2303 cxsr_enabled = false;
2304 /* Turn off self refresh if both pipes are enabled */
2305 intel_set_memory_cxsr(dev_priv, false);
2306 }
2307
2308 drm_dbg_kms(&dev_priv->drm,
2309 "Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2310 srwm);
2311
2312 /* 965 has limitations... */
2313 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
2314 FW_WM(8, CURSORB) |
2315 FW_WM(8, PLANEB) |
2316 FW_WM(8, PLANEA));
2317 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
2318 FW_WM(8, PLANEC_OLD));
2319 /* update cursor SR watermark */
2320 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
2321
2322 if (cxsr_enabled)
2323 intel_set_memory_cxsr(dev_priv, true);
2324 }
2325
2326 #undef FW_WM
2327
2328 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2329 {
2330 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2331 const struct intel_watermark_params *wm_info;
2332 u32 fwater_lo;
2333 u32 fwater_hi;
2334 int cwm, srwm = 1;
2335 int fifo_size;
2336 int planea_wm, planeb_wm;
2337 struct intel_crtc *crtc, *enabled = NULL;
2338
2339 if (IS_I945GM(dev_priv))
2340 wm_info = &i945_wm_info;
2341 else if (!IS_GEN(dev_priv, 2))
2342 wm_info = &i915_wm_info;
2343 else
2344 wm_info = &i830_a_wm_info;
2345
2346 fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
2347 crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
2348 if (intel_crtc_active(crtc)) {
2349 const struct drm_display_mode *pipe_mode =
2350 &crtc->config->hw.pipe_mode;
2351 const struct drm_framebuffer *fb =
2352 crtc->base.primary->state->fb;
2353 int cpp;
2354
2355 if (IS_GEN(dev_priv, 2))
2356 cpp = 4;
2357 else
2358 cpp = fb->format->cpp[0];
2359
2360 planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
2361 wm_info, fifo_size, cpp,
2362 pessimal_latency_ns);
2363 enabled = crtc;
2364 } else {
2365 planea_wm = fifo_size - wm_info->guard_size;
2366 if (planea_wm > (long)wm_info->max_wm)
2367 planea_wm = wm_info->max_wm;
2368 }
2369
2370 if (IS_GEN(dev_priv, 2))
2371 wm_info = &i830_bc_wm_info;
2372
2373 fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
2374 crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
2375 if (intel_crtc_active(crtc)) {
2376 const struct drm_display_mode *pipe_mode =
2377 &crtc->config->hw.pipe_mode;
2378 const struct drm_framebuffer *fb =
2379 crtc->base.primary->state->fb;
2380 int cpp;
2381
2382 if (IS_GEN(dev_priv, 2))
2383 cpp = 4;
2384 else
2385 cpp = fb->format->cpp[0];
2386
2387 planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
2388 wm_info, fifo_size, cpp,
2389 pessimal_latency_ns);
2390 if (enabled == NULL)
2391 enabled = crtc;
2392 else
2393 enabled = NULL;
2394 } else {
2395 planeb_wm = fifo_size - wm_info->guard_size;
2396 if (planeb_wm > (long)wm_info->max_wm)
2397 planeb_wm = wm_info->max_wm;
2398 }
2399
2400 drm_dbg_kms(&dev_priv->drm,
2401 "FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2402
2403 if (IS_I915GM(dev_priv) && enabled) {
2404 struct drm_i915_gem_object *obj;
2405
2406 obj = intel_fb_obj(enabled->base.primary->state->fb);
2407
2408 /* self-refresh seems busted with untiled */
2409 if (!i915_gem_object_is_tiled(obj))
2410 enabled = NULL;
2411 }
2412
2413 /*
2414 * Overlay gets an aggressive default since video jitter is bad.
2415 */
2416 cwm = 2;
2417
2418 /* Play safe and disable self-refresh before adjusting watermarks. */
2419 intel_set_memory_cxsr(dev_priv, false);
2420
2421 /* Calc sr entries for one plane configs */
2422 if (HAS_FW_BLC(dev_priv) && enabled) {
2423 /* self-refresh has much higher latency */
2424 static const int sr_latency_ns = 6000;
2425 const struct drm_display_mode *pipe_mode =
2426 &enabled->config->hw.pipe_mode;
2427 const struct drm_framebuffer *fb =
2428 enabled->base.primary->state->fb;
2429 int clock = pipe_mode->crtc_clock;
2430 int htotal = pipe_mode->crtc_htotal;
2431 int hdisplay = enabled->config->pipe_src_w;
2432 int cpp;
2433 int entries;
2434
2435 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2436 cpp = 4;
2437 else
2438 cpp = fb->format->cpp[0];
2439
2440 entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
2441 sr_latency_ns / 100);
2442 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
2443 drm_dbg_kms(&dev_priv->drm,
2444 "self-refresh entries: %d\n", entries);
2445 srwm = wm_info->fifo_size - entries;
2446 if (srwm < 0)
2447 srwm = 1;
2448
2449 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2450 I915_WRITE(FW_BLC_SELF,
2451 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2452 else
2453 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2454 }
2455
2456 drm_dbg_kms(&dev_priv->drm,
2457 "Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2458 planea_wm, planeb_wm, cwm, srwm);
2459
2460 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2461 fwater_hi = (cwm & 0x1f);
2462
2463 /* Set request length to 8 cachelines per fetch */
2464 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2465 fwater_hi = fwater_hi | (1 << 8);
2466
2467 I915_WRITE(FW_BLC, fwater_lo);
2468 I915_WRITE(FW_BLC2, fwater_hi);
2469
2470 if (enabled)
2471 intel_set_memory_cxsr(dev_priv, true);
2472 }
2473
2474 static void i845_update_wm(struct intel_crtc *unused_crtc)
2475 {
2476 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2477 struct intel_crtc *crtc;
2478 const struct drm_display_mode *pipe_mode;
2479 u32 fwater_lo;
2480 int planea_wm;
2481
2482 crtc = single_enabled_crtc(dev_priv);
2483 if (crtc == NULL)
2484 return;
2485
2486 pipe_mode = &crtc->config->hw.pipe_mode;
2487 planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
2488 &i845_wm_info,
2489 dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
2490 4, pessimal_latency_ns);
2491 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2492 fwater_lo |= (3<<8) | planea_wm;
2493
2494 drm_dbg_kms(&dev_priv->drm,
2495 "Setting FIFO watermarks - A: %d\n", planea_wm);
2496
2497 I915_WRITE(FW_BLC, fwater_lo);
2498 }
2499
2500 /* latency must be in 0.1us units. */
2501 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
2502 unsigned int cpp,
2503 unsigned int latency)
2504 {
2505 unsigned int ret;
2506
2507 ret = intel_wm_method1(pixel_rate, cpp, latency);
2508 ret = DIV_ROUND_UP(ret, 64) + 2;
2509
2510 return ret;
2511 }
2512
2513 /* latency must be in 0.1us units. */
2514 static unsigned int ilk_wm_method2(unsigned int pixel_rate,
2515 unsigned int htotal,
2516 unsigned int width,
2517 unsigned int cpp,
2518 unsigned int latency)
2519 {
2520 unsigned int ret;
2521
2522 ret = intel_wm_method2(pixel_rate, htotal,
2523 width, cpp, latency);
2524 ret = DIV_ROUND_UP(ret, 64) + 2;
2525
2526 return ret;
2527 }
2528
2529 static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp)
2530 {
2531 /*
2532 * Neither of these should be possible since this function shouldn't be
2533 * called if the CRTC is off or the plane is invisible. But let's be
2534 * extra paranoid to avoid a potential divide-by-zero if we screw up
2535 * elsewhere in the driver.
2536 */
2537 if (WARN_ON(!cpp))
2538 return 0;
2539 if (WARN_ON(!horiz_pixels))
2540 return 0;
2541
2542 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
2543 }
2544
2545 struct ilk_wm_maximums {
2546 u16 pri;
2547 u16 spr;
2548 u16 cur;
2549 u16 fbc;
2550 };
2551
2552 /*
2553 * For both WM_PIPE and WM_LP.
2554 * mem_value must be in 0.1us units.
2555 */
2556 static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
2557 const struct intel_plane_state *plane_state,
2558 u32 mem_value, bool is_lp)
2559 {
2560 u32 method1, method2;
2561 int cpp;
2562
2563 if (mem_value == 0)
2564 return U32_MAX;
2565
2566 if (!intel_wm_plane_visible(crtc_state, plane_state))
2567 return 0;
2568
2569 cpp = plane_state->hw.fb->format->cpp[0];
2570
2571 method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
2572
2573 if (!is_lp)
2574 return method1;
2575
2576 method2 = ilk_wm_method2(crtc_state->pixel_rate,
2577 crtc_state->hw.pipe_mode.crtc_htotal,
2578 drm_rect_width(&plane_state->uapi.dst),
2579 cpp, mem_value);
2580
2581 return min(method1, method2);
2582 }
2583
2584 /*
2585 * For both WM_PIPE and WM_LP.
2586 * mem_value must be in 0.1us units.
2587 */
2588 static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
2589 const struct intel_plane_state *plane_state,
2590 u32 mem_value)
2591 {
2592 u32 method1, method2;
2593 int cpp;
2594
2595 if (mem_value == 0)
2596 return U32_MAX;
2597
2598 if (!intel_wm_plane_visible(crtc_state, plane_state))
2599 return 0;
2600
2601 cpp = plane_state->hw.fb->format->cpp[0];
2602
2603 method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
2604 method2 = ilk_wm_method2(crtc_state->pixel_rate,
2605 crtc_state->hw.pipe_mode.crtc_htotal,
2606 drm_rect_width(&plane_state->uapi.dst),
2607 cpp, mem_value);
2608 return min(method1, method2);
2609 }
2610
2611 /*
2612 * For both WM_PIPE and WM_LP.
2613 * mem_value must be in 0.1us units.
2614 */
2615 static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
2616 const struct intel_plane_state *plane_state,
2617 u32 mem_value)
2618 {
2619 int cpp;
2620
2621 if (mem_value == 0)
2622 return U32_MAX;
2623
2624 if (!intel_wm_plane_visible(crtc_state, plane_state))
2625 return 0;
2626
2627 cpp = plane_state->hw.fb->format->cpp[0];
2628
2629 return ilk_wm_method2(crtc_state->pixel_rate,
2630 crtc_state->hw.pipe_mode.crtc_htotal,
2631 drm_rect_width(&plane_state->uapi.dst),
2632 cpp, mem_value);
2633 }
2634
2635 /* Only for WM_LP. */
2636 static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
2637 const struct intel_plane_state *plane_state,
2638 u32 pri_val)
2639 {
2640 int cpp;
2641
2642 if (!intel_wm_plane_visible(crtc_state, plane_state))
2643 return 0;
2644
2645 cpp = plane_state->hw.fb->format->cpp[0];
2646
2647 return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->uapi.dst),
2648 cpp);
2649 }
2650
2651 static unsigned int
2652 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
2653 {
2654 if (INTEL_GEN(dev_priv) >= 8)
2655 return 3072;
2656 else if (INTEL_GEN(dev_priv) >= 7)
2657 return 768;
2658 else
2659 return 512;
2660 }
2661
2662 static unsigned int
2663 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
2664 int level, bool is_sprite)
2665 {
2666 if (INTEL_GEN(dev_priv) >= 8)
2667 /* BDW primary/sprite plane watermarks */
2668 return level == 0 ? 255 : 2047;
2669 else if (INTEL_GEN(dev_priv) >= 7)
2670 /* IVB/HSW primary/sprite plane watermarks */
2671 return level == 0 ? 127 : 1023;
2672 else if (!is_sprite)
2673 /* ILK/SNB primary plane watermarks */
2674 return level == 0 ? 127 : 511;
2675 else
2676 /* ILK/SNB sprite plane watermarks */
2677 return level == 0 ? 63 : 255;
2678 }
2679
2680 static unsigned int
2681 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
2682 {
2683 if (INTEL_GEN(dev_priv) >= 7)
2684 return level == 0 ? 63 : 255;
2685 else
2686 return level == 0 ? 31 : 63;
2687 }
2688
2689 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
2690 {
2691 if (INTEL_GEN(dev_priv) >= 8)
2692 return 31;
2693 else
2694 return 15;
2695 }
2696
2697 /* Calculate the maximum primary/sprite plane watermark */
2698 static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
2699 int level,
2700 const struct intel_wm_config *config,
2701 enum intel_ddb_partitioning ddb_partitioning,
2702 bool is_sprite)
2703 {
2704 unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
2705
2706 /* if sprites aren't enabled, sprites get nothing */
2707 if (is_sprite && !config->sprites_enabled)
2708 return 0;
2709
2710 /* HSW allows LP1+ watermarks even with multiple pipes */
2711 if (level == 0 || config->num_pipes_active > 1) {
2712 fifo_size /= INTEL_NUM_PIPES(dev_priv);
2713
2714 /*
2715 * For some reason the non self refresh
2716 * FIFO size is only half of the self
2717 * refresh FIFO size on ILK/SNB.
2718 */
2719 if (INTEL_GEN(dev_priv) <= 6)
2720 fifo_size /= 2;
2721 }
2722
2723 if (config->sprites_enabled) {
2724 /* level 0 is always calculated with 1:1 split */
2725 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2726 if (is_sprite)
2727 fifo_size *= 5;
2728 fifo_size /= 6;
2729 } else {
2730 fifo_size /= 2;
2731 }
2732 }
2733
2734 /* clamp to max that the registers can hold */
2735 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
2736 }
2737
2738 /* Calculate the maximum cursor plane watermark */
2739 static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
2740 int level,
2741 const struct intel_wm_config *config)
2742 {
2743 /* HSW LP1+ watermarks w/ multiple pipes */
2744 if (level > 0 && config->num_pipes_active > 1)
2745 return 64;
2746
2747 /* otherwise just report max that registers can hold */
2748 return ilk_cursor_wm_reg_max(dev_priv, level);
2749 }
2750
2751 static void ilk_compute_wm_maximums(const struct drm_i915_private *dev_priv,
2752 int level,
2753 const struct intel_wm_config *config,
2754 enum intel_ddb_partitioning ddb_partitioning,
2755 struct ilk_wm_maximums *max)
2756 {
2757 max->pri = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, false);
2758 max->spr = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, true);
2759 max->cur = ilk_cursor_wm_max(dev_priv, level, config);
2760 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2761 }
2762
2763 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
2764 int level,
2765 struct ilk_wm_maximums *max)
2766 {
2767 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2768 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2769 max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2770 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2771 }
2772
2773 static bool ilk_validate_wm_level(int level,
2774 const struct ilk_wm_maximums *max,
2775 struct intel_wm_level *result)
2776 {
2777 bool ret;
2778
2779 /* already determined to be invalid? */
2780 if (!result->enable)
2781 return false;
2782
2783 result->enable = result->pri_val <= max->pri &&
2784 result->spr_val <= max->spr &&
2785 result->cur_val <= max->cur;
2786
2787 ret = result->enable;
2788
2789 /*
2790 * HACK until we can pre-compute everything,
2791 * and thus fail gracefully if LP0 watermarks
2792 * are exceeded...
2793 */
2794 if (level == 0 && !result->enable) {
2795 if (result->pri_val > max->pri)
2796 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2797 level, result->pri_val, max->pri);
2798 if (result->spr_val > max->spr)
2799 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2800 level, result->spr_val, max->spr);
2801 if (result->cur_val > max->cur)
2802 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2803 level, result->cur_val, max->cur);
2804
2805 result->pri_val = min_t(u32, result->pri_val, max->pri);
2806 result->spr_val = min_t(u32, result->spr_val, max->spr);
2807 result->cur_val = min_t(u32, result->cur_val, max->cur);
2808 result->enable = true;
2809 }
2810
2811 return ret;
2812 }
2813
2814 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2815 const struct intel_crtc *crtc,
2816 int level,
2817 struct intel_crtc_state *crtc_state,
2818 const struct intel_plane_state *pristate,
2819 const struct intel_plane_state *sprstate,
2820 const struct intel_plane_state *curstate,
2821 struct intel_wm_level *result)
2822 {
2823 u16 pri_latency = dev_priv->wm.pri_latency[level];
2824 u16 spr_latency = dev_priv->wm.spr_latency[level];
2825 u16 cur_latency = dev_priv->wm.cur_latency[level];
2826
2827 /* WM1+ latency values stored in 0.5us units */
2828 if (level > 0) {
2829 pri_latency *= 5;
2830 spr_latency *= 5;
2831 cur_latency *= 5;
2832 }
2833
2834 if (pristate) {
2835 result->pri_val = ilk_compute_pri_wm(crtc_state, pristate,
2836 pri_latency, level);
2837 result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val);
2838 }
2839
2840 if (sprstate)
2841 result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency);
2842
2843 if (curstate)
2844 result->cur_val = ilk_compute_cur_wm(crtc_state, curstate, cur_latency);
2845
2846 result->enable = true;
2847 }
2848
2849 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2850 u16 wm[8])
2851 {
2852 struct intel_uncore *uncore = &dev_priv->uncore;
2853
2854 if (INTEL_GEN(dev_priv) >= 9) {
2855 u32 val;
2856 int ret, i;
2857 int level, max_level = ilk_wm_max_level(dev_priv);
2858
2859 /* read the first set of memory latencies[0:3] */
2860 val = 0; /* data0 to be programmed to 0 for first set */
2861 ret = sandybridge_pcode_read(dev_priv,
2862 GEN9_PCODE_READ_MEM_LATENCY,
2863 &val, NULL);
2864
2865 if (ret) {
2866 drm_err(&dev_priv->drm,
2867 "SKL Mailbox read error = %d\n", ret);
2868 return;
2869 }
2870
2871 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2872 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2873 GEN9_MEM_LATENCY_LEVEL_MASK;
2874 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2875 GEN9_MEM_LATENCY_LEVEL_MASK;
2876 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2877 GEN9_MEM_LATENCY_LEVEL_MASK;
2878
2879 /* read the second set of memory latencies[4:7] */
2880 val = 1; /* data0 to be programmed to 1 for second set */
2881 ret = sandybridge_pcode_read(dev_priv,
2882 GEN9_PCODE_READ_MEM_LATENCY,
2883 &val, NULL);
2884 if (ret) {
2885 drm_err(&dev_priv->drm,
2886 "SKL Mailbox read error = %d\n", ret);
2887 return;
2888 }
2889
2890 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2891 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2892 GEN9_MEM_LATENCY_LEVEL_MASK;
2893 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2894 GEN9_MEM_LATENCY_LEVEL_MASK;
2895 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2896 GEN9_MEM_LATENCY_LEVEL_MASK;
2897
2898 /*
2899 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2900 * need to be disabled. We make sure to sanitize the values out
2901 * of the punit to satisfy this requirement.
2902 */
2903 for (level = 1; level <= max_level; level++) {
2904 if (wm[level] == 0) {
2905 for (i = level + 1; i <= max_level; i++)
2906 wm[i] = 0;
2907 break;
2908 }
2909 }
2910
2911 /*
2912 * WaWmMemoryReadLatency:skl+,glk
2913 *
2914 * punit doesn't take into account the read latency so we need
2915 * to add 2us to the various latency levels we retrieve from the
2916 * punit when level 0 response data us 0us.
2917 */
2918 if (wm[0] == 0) {
2919 wm[0] += 2;
2920 for (level = 1; level <= max_level; level++) {
2921 if (wm[level] == 0)
2922 break;
2923 wm[level] += 2;
2924 }
2925 }
2926
2927 /*
2928 * WA Level-0 adjustment for 16GB DIMMs: SKL+
2929 * If we could not get dimm info enable this WA to prevent from
2930 * any underrun. If not able to get Dimm info assume 16GB dimm
2931 * to avoid any underrun.
2932 */
2933 if (dev_priv->dram_info.is_16gb_dimm)
2934 wm[0] += 1;
2935
2936 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2937 u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
2938
2939 wm[0] = (sskpd >> 56) & 0xFF;
2940 if (wm[0] == 0)
2941 wm[0] = sskpd & 0xF;
2942 wm[1] = (sskpd >> 4) & 0xFF;
2943 wm[2] = (sskpd >> 12) & 0xFF;
2944 wm[3] = (sskpd >> 20) & 0x1FF;
2945 wm[4] = (sskpd >> 32) & 0x1FF;
2946 } else if (INTEL_GEN(dev_priv) >= 6) {
2947 u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
2948
2949 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2950 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2951 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2952 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2953 } else if (INTEL_GEN(dev_priv) >= 5) {
2954 u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
2955
2956 /* ILK primary LP0 latency is 700 ns */
2957 wm[0] = 7;
2958 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2959 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2960 } else {
2961 MISSING_CASE(INTEL_DEVID(dev_priv));
2962 }
2963 }
2964
2965 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2966 u16 wm[5])
2967 {
2968 /* ILK sprite LP0 latency is 1300 ns */
2969 if (IS_GEN(dev_priv, 5))
2970 wm[0] = 13;
2971 }
2972
2973 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2974 u16 wm[5])
2975 {
2976 /* ILK cursor LP0 latency is 1300 ns */
2977 if (IS_GEN(dev_priv, 5))
2978 wm[0] = 13;
2979 }
2980
2981 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2982 {
2983 /* how many WM levels are we expecting */
2984 if (INTEL_GEN(dev_priv) >= 9)
2985 return 7;
2986 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2987 return 4;
2988 else if (INTEL_GEN(dev_priv) >= 6)
2989 return 3;
2990 else
2991 return 2;
2992 }
2993
2994 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2995 const char *name,
2996 const u16 wm[8])
2997 {
2998 int level, max_level = ilk_wm_max_level(dev_priv);
2999
3000 for (level = 0; level <= max_level; level++) {
3001 unsigned int latency = wm[level];
3002
3003 if (latency == 0) {
3004 drm_dbg_kms(&dev_priv->drm,
3005 "%s WM%d latency not provided\n",
3006 name, level);
3007 continue;
3008 }
3009
3010 /*
3011 * - latencies are in us on gen9.
3012 * - before then, WM1+ latency values are in 0.5us units
3013 */
3014 if (INTEL_GEN(dev_priv) >= 9)
3015 latency *= 10;
3016 else if (level > 0)
3017 latency *= 5;
3018
3019 drm_dbg_kms(&dev_priv->drm,
3020 "%s WM%d latency %u (%u.%u usec)\n", name, level,
3021 wm[level], latency / 10, latency % 10);
3022 }
3023 }
3024
3025 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
3026 u16 wm[5], u16 min)
3027 {
3028 int level, max_level = ilk_wm_max_level(dev_priv);
3029
3030 if (wm[0] >= min)
3031 return false;
3032
3033 wm[0] = max(wm[0], min);
3034 for (level = 1; level <= max_level; level++)
3035 wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5));
3036
3037 return true;
3038 }
3039
3040 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
3041 {
3042 bool changed;
3043
3044 /*
3045 * The BIOS provided WM memory latency values are often
3046 * inadequate for high resolution displays. Adjust them.
3047 */
3048 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
3049 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
3050 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
3051
3052 if (!changed)
3053 return;
3054
3055 drm_dbg_kms(&dev_priv->drm,
3056 "WM latency values increased to avoid potential underruns\n");
3057 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3058 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3059 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3060 }
3061
3062 static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
3063 {
3064 /*
3065 * On some SNB machines (Thinkpad X220 Tablet at least)
3066 * LP3 usage can cause vblank interrupts to be lost.
3067 * The DEIIR bit will go high but it looks like the CPU
3068 * never gets interrupted.
3069 *
3070 * It's not clear whether other interrupt source could
3071 * be affected or if this is somehow limited to vblank
3072 * interrupts only. To play it safe we disable LP3
3073 * watermarks entirely.
3074 */
3075 if (dev_priv->wm.pri_latency[3] == 0 &&
3076 dev_priv->wm.spr_latency[3] == 0 &&
3077 dev_priv->wm.cur_latency[3] == 0)
3078 return;
3079
3080 dev_priv->wm.pri_latency[3] = 0;
3081 dev_priv->wm.spr_latency[3] = 0;
3082 dev_priv->wm.cur_latency[3] = 0;
3083
3084 drm_dbg_kms(&dev_priv->drm,
3085 "LP3 watermarks disabled due to potential for lost interrupts\n");
3086 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3087 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3088 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3089 }
3090
3091 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
3092 {
3093 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
3094
3095 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
3096 sizeof(dev_priv->wm.pri_latency));
3097 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
3098 sizeof(dev_priv->wm.pri_latency));
3099
3100 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
3101 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
3102
3103 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3104 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3105 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3106
3107 if (IS_GEN(dev_priv, 6)) {
3108 snb_wm_latency_quirk(dev_priv);
3109 snb_wm_lp3_irq_quirk(dev_priv);
3110 }
3111 }
3112
3113 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
3114 {
3115 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
3116 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
3117 }
3118
3119 static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
3120 struct intel_pipe_wm *pipe_wm)
3121 {
3122 /* LP0 watermark maximums depend on this pipe alone */
3123 const struct intel_wm_config config = {
3124 .num_pipes_active = 1,
3125 .sprites_enabled = pipe_wm->sprites_enabled,
3126 .sprites_scaled = pipe_wm->sprites_scaled,
3127 };
3128 struct ilk_wm_maximums max;
3129
3130 /* LP0 watermarks always use 1/2 DDB partitioning */
3131 ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max);
3132
3133 /* At least LP0 must be valid */
3134 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
3135 drm_dbg_kms(&dev_priv->drm, "LP0 watermark invalid\n");
3136 return false;
3137 }
3138
3139 return true;
3140 }
3141
3142 /* Compute new watermarks for the pipe */
3143 static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
3144 {
3145 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3146 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3147 struct intel_pipe_wm *pipe_wm;
3148 struct intel_plane *plane;
3149 const struct intel_plane_state *plane_state;
3150 const struct intel_plane_state *pristate = NULL;
3151 const struct intel_plane_state *sprstate = NULL;
3152 const struct intel_plane_state *curstate = NULL;
3153 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
3154 struct ilk_wm_maximums max;
3155
3156 pipe_wm = &crtc_state->wm.ilk.optimal;
3157
3158 intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
3159 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
3160 pristate = plane_state;
3161 else if (plane->base.type == DRM_PLANE_TYPE_OVERLAY)
3162 sprstate = plane_state;
3163 else if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
3164 curstate = plane_state;
3165 }
3166
3167 pipe_wm->pipe_enabled = crtc_state->hw.active;
3168 if (sprstate) {
3169 pipe_wm->sprites_enabled = sprstate->uapi.visible;
3170 pipe_wm->sprites_scaled = sprstate->uapi.visible &&
3171 (drm_rect_width(&sprstate->uapi.dst) != drm_rect_width(&sprstate->uapi.src) >> 16 ||
3172 drm_rect_height(&sprstate->uapi.dst) != drm_rect_height(&sprstate->uapi.src) >> 16);
3173 }
3174
3175 usable_level = max_level;
3176
3177 /* ILK/SNB: LP2+ watermarks only w/o sprites */
3178 if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
3179 usable_level = 1;
3180
3181 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3182 if (pipe_wm->sprites_scaled)
3183 usable_level = 0;
3184
3185 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3186 ilk_compute_wm_level(dev_priv, crtc, 0, crtc_state,
3187 pristate, sprstate, curstate, &pipe_wm->wm[0]);
3188
3189 if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
3190 return -EINVAL;
3191
3192 ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
3193
3194 for (level = 1; level <= usable_level; level++) {
3195 struct intel_wm_level *wm = &pipe_wm->wm[level];
3196
3197 ilk_compute_wm_level(dev_priv, crtc, level, crtc_state,
3198 pristate, sprstate, curstate, wm);
3199
3200 /*
3201 * Disable any watermark level that exceeds the
3202 * register maximums since such watermarks are
3203 * always invalid.
3204 */
3205 if (!ilk_validate_wm_level(level, &max, wm)) {
3206 memset(wm, 0, sizeof(*wm));
3207 break;
3208 }
3209 }
3210
3211 return 0;
3212 }
3213
3214 /*
3215 * Build a set of 'intermediate' watermark values that satisfy both the old
3216 * state and the new state. These can be programmed to the hardware
3217 * immediately.
3218 */
3219 static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
3220 {
3221 struct intel_crtc *intel_crtc = to_intel_crtc(newstate->uapi.crtc);
3222 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3223 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
3224 struct intel_atomic_state *intel_state =
3225 to_intel_atomic_state(newstate->uapi.state);
3226 const struct intel_crtc_state *oldstate =
3227 intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
3228 const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
3229 int level, max_level = ilk_wm_max_level(dev_priv);
3230
3231 /*
3232 * Start with the final, target watermarks, then combine with the
3233 * currently active watermarks to get values that are safe both before
3234 * and after the vblank.
3235 */
3236 *a = newstate->wm.ilk.optimal;
3237 if (!newstate->hw.active || drm_atomic_crtc_needs_modeset(&newstate->uapi) ||
3238 intel_state->skip_intermediate_wm)
3239 return 0;
3240
3241 a->pipe_enabled |= b->pipe_enabled;
3242 a->sprites_enabled |= b->sprites_enabled;
3243 a->sprites_scaled |= b->sprites_scaled;
3244
3245 for (level = 0; level <= max_level; level++) {
3246 struct intel_wm_level *a_wm = &a->wm[level];
3247 const struct intel_wm_level *b_wm = &b->wm[level];
3248
3249 a_wm->enable &= b_wm->enable;
3250 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
3251 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
3252 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
3253 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
3254 }
3255
3256 /*
3257 * We need to make sure that these merged watermark values are
3258 * actually a valid configuration themselves. If they're not,
3259 * there's no safe way to transition from the old state to
3260 * the new state, so we need to fail the atomic transaction.
3261 */
3262 if (!ilk_validate_pipe_wm(dev_priv, a))
3263 return -EINVAL;
3264
3265 /*
3266 * If our intermediate WM are identical to the final WM, then we can
3267 * omit the post-vblank programming; only update if it's different.
3268 */
3269 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
3270 newstate->wm.need_postvbl_update = true;
3271
3272 return 0;
3273 }
3274
3275 /*
3276 * Merge the watermarks from all active pipes for a specific level.
3277 */
3278 static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
3279 int level,
3280 struct intel_wm_level *ret_wm)
3281 {
3282 const struct intel_crtc *intel_crtc;
3283
3284 ret_wm->enable = true;
3285
3286 for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
3287 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
3288 const struct intel_wm_level *wm = &active->wm[level];
3289
3290 if (!active->pipe_enabled)
3291 continue;
3292
3293 /*
3294 * The watermark values may have been used in the past,
3295 * so we must maintain them in the registers for some
3296 * time even if the level is now disabled.
3297 */
3298 if (!wm->enable)
3299 ret_wm->enable = false;
3300
3301 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
3302 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
3303 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
3304 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
3305 }
3306 }
3307
3308 /*
3309 * Merge all low power watermarks for all active pipes.
3310 */
3311 static void ilk_wm_merge(struct drm_i915_private *dev_priv,
3312 const struct intel_wm_config *config,
3313 const struct ilk_wm_maximums *max,
3314 struct intel_pipe_wm *merged)
3315 {
3316 int level, max_level = ilk_wm_max_level(dev_priv);
3317 int last_enabled_level = max_level;
3318
3319 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3320 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
3321 config->num_pipes_active > 1)
3322 last_enabled_level = 0;
3323
3324 /* ILK: FBC WM must be disabled always */
3325 merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
3326
3327 /* merge each WM1+ level */
3328 for (level = 1; level <= max_level; level++) {
3329 struct intel_wm_level *wm = &merged->wm[level];
3330
3331 ilk_merge_wm_level(dev_priv, level, wm);
3332
3333 if (level > last_enabled_level)
3334 wm->enable = false;
3335 else if (!ilk_validate_wm_level(level, max, wm))
3336 /* make sure all following levels get disabled */
3337 last_enabled_level = level - 1;
3338
3339 /*
3340 * The spec says it is preferred to disable
3341 * FBC WMs instead of disabling a WM level.
3342 */
3343 if (wm->fbc_val > max->fbc) {
3344 if (wm->enable)
3345 merged->fbc_wm_enabled = false;
3346 wm->fbc_val = 0;
3347 }
3348 }
3349
3350 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3351 /*
3352 * FIXME this is racy. FBC might get enabled later.
3353 * What we should check here is whether FBC can be
3354 * enabled sometime later.
3355 */
3356 if (IS_GEN(dev_priv, 5) && !merged->fbc_wm_enabled &&
3357 intel_fbc_is_active(dev_priv)) {
3358 for (level = 2; level <= max_level; level++) {
3359 struct intel_wm_level *wm = &merged->wm[level];
3360
3361 wm->enable = false;
3362 }
3363 }
3364 }
3365
3366 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
3367 {
3368 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3369 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3370 }
3371
3372 /* The value we need to program into the WM_LPx latency field */
3373 static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
3374 int level)
3375 {
3376 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3377 return 2 * level;
3378 else
3379 return dev_priv->wm.pri_latency[level];
3380 }
3381
3382 static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
3383 const struct intel_pipe_wm *merged,
3384 enum intel_ddb_partitioning partitioning,
3385 struct ilk_wm_values *results)
3386 {
3387 struct intel_crtc *intel_crtc;
3388 int level, wm_lp;
3389
3390 results->enable_fbc_wm = merged->fbc_wm_enabled;
3391 results->partitioning = partitioning;
3392
3393 /* LP1+ register values */
3394 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3395 const struct intel_wm_level *r;
3396
3397 level = ilk_wm_lp_to_level(wm_lp, merged);
3398
3399 r = &merged->wm[level];
3400
3401 /*
3402 * Maintain the watermark values even if the level is
3403 * disabled. Doing otherwise could cause underruns.
3404 */
3405 results->wm_lp[wm_lp - 1] =
3406 (ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) |
3407 (r->pri_val << WM1_LP_SR_SHIFT) |
3408 r->cur_val;
3409
3410 if (r->enable)
3411 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
3412
3413 if (INTEL_GEN(dev_priv) >= 8)
3414 results->wm_lp[wm_lp - 1] |=
3415 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
3416 else
3417 results->wm_lp[wm_lp - 1] |=
3418 r->fbc_val << WM1_LP_FBC_SHIFT;
3419
3420 /*
3421 * Always set WM1S_LP_EN when spr_val != 0, even if the
3422 * level is disabled. Doing otherwise could cause underruns.
3423 */
3424 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
3425 drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
3426 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
3427 } else
3428 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
3429 }
3430
3431 /* LP0 register values */
3432 for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
3433 enum pipe pipe = intel_crtc->pipe;
3434 const struct intel_pipe_wm *pipe_wm = &intel_crtc->wm.active.ilk;
3435 const struct intel_wm_level *r = &pipe_wm->wm[0];
3436
3437 if (drm_WARN_ON(&dev_priv->drm, !r->enable))
3438 continue;
3439
3440 results->wm_pipe[pipe] =
3441 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
3442 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
3443 r->cur_val;
3444 }
3445 }
3446
3447 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3448 * case both are at the same level. Prefer r1 in case they're the same. */
3449 static struct intel_pipe_wm *
3450 ilk_find_best_result(struct drm_i915_private *dev_priv,
3451 struct intel_pipe_wm *r1,
3452 struct intel_pipe_wm *r2)
3453 {
3454 int level, max_level = ilk_wm_max_level(dev_priv);
3455 int level1 = 0, level2 = 0;
3456
3457 for (level = 1; level <= max_level; level++) {
3458 if (r1->wm[level].enable)
3459 level1 = level;
3460 if (r2->wm[level].enable)
3461 level2 = level;
3462 }
3463
3464 if (level1 == level2) {
3465 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
3466 return r2;
3467 else
3468 return r1;
3469 } else if (level1 > level2) {
3470 return r1;
3471 } else {
3472 return r2;
3473 }
3474 }
3475
3476 /* dirty bits used to track which watermarks need changes */
3477 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3478 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3479 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3480 #define WM_DIRTY_FBC (1 << 24)
3481 #define WM_DIRTY_DDB (1 << 25)
3482
3483 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
3484 const struct ilk_wm_values *old,
3485 const struct ilk_wm_values *new)
3486 {
3487 unsigned int dirty = 0;
3488 enum pipe pipe;
3489 int wm_lp;
3490
3491 for_each_pipe(dev_priv, pipe) {
3492 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
3493 dirty |= WM_DIRTY_PIPE(pipe);
3494 /* Must disable LP1+ watermarks too */
3495 dirty |= WM_DIRTY_LP_ALL;
3496 }
3497 }
3498
3499 if (old->enable_fbc_wm != new->enable_fbc_wm) {
3500 dirty |= WM_DIRTY_FBC;
3501 /* Must disable LP1+ watermarks too */
3502 dirty |= WM_DIRTY_LP_ALL;
3503 }
3504
3505 if (old->partitioning != new->partitioning) {
3506 dirty |= WM_DIRTY_DDB;
3507 /* Must disable LP1+ watermarks too */
3508 dirty |= WM_DIRTY_LP_ALL;
3509 }
3510
3511 /* LP1+ watermarks already deemed dirty, no need to continue */
3512 if (dirty & WM_DIRTY_LP_ALL)
3513 return dirty;
3514
3515 /* Find the lowest numbered LP1+ watermark in need of an update... */
3516 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3517 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
3518 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
3519 break;
3520 }
3521
3522 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3523 for (; wm_lp <= 3; wm_lp++)
3524 dirty |= WM_DIRTY_LP(wm_lp);
3525
3526 return dirty;
3527 }
3528
3529 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
3530 unsigned int dirty)
3531 {
3532 struct ilk_wm_values *previous = &dev_priv->wm.hw;
3533 bool changed = false;
3534
3535 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
3536 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
3537 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
3538 changed = true;
3539 }
3540 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
3541 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
3542 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
3543 changed = true;
3544 }
3545 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
3546 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
3547 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
3548 changed = true;
3549 }
3550
3551 /*
3552 * Don't touch WM1S_LP_EN here.
3553 * Doing so could cause underruns.
3554 */
3555
3556 return changed;
3557 }
3558
3559 /*
3560 * The spec says we shouldn't write when we don't need, because every write
3561 * causes WMs to be re-evaluated, expending some power.
3562 */
3563 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
3564 struct ilk_wm_values *results)
3565 {
3566 struct ilk_wm_values *previous = &dev_priv->wm.hw;
3567 unsigned int dirty;
3568 u32 val;
3569
3570 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
3571 if (!dirty)
3572 return;
3573
3574 _ilk_disable_lp_wm(dev_priv, dirty);
3575
3576 if (dirty & WM_DIRTY_PIPE(PIPE_A))
3577 I915_WRITE(WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
3578 if (dirty & WM_DIRTY_PIPE(PIPE_B))
3579 I915_WRITE(WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
3580 if (dirty & WM_DIRTY_PIPE(PIPE_C))
3581 I915_WRITE(WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
3582
3583 if (dirty & WM_DIRTY_DDB) {
3584 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3585 val = I915_READ(WM_MISC);
3586 if (results->partitioning == INTEL_DDB_PART_1_2)
3587 val &= ~WM_MISC_DATA_PARTITION_5_6;
3588 else
3589 val |= WM_MISC_DATA_PARTITION_5_6;
3590 I915_WRITE(WM_MISC, val);
3591 } else {
3592 val = I915_READ(DISP_ARB_CTL2);
3593 if (results->partitioning == INTEL_DDB_PART_1_2)
3594 val &= ~DISP_DATA_PARTITION_5_6;
3595 else
3596 val |= DISP_DATA_PARTITION_5_6;
3597 I915_WRITE(DISP_ARB_CTL2, val);
3598 }
3599 }
3600
3601 if (dirty & WM_DIRTY_FBC) {
3602 val = I915_READ(DISP_ARB_CTL);
3603 if (results->enable_fbc_wm)
3604 val &= ~DISP_FBC_WM_DIS;
3605 else
3606 val |= DISP_FBC_WM_DIS;
3607 I915_WRITE(DISP_ARB_CTL, val);
3608 }
3609
3610 if (dirty & WM_DIRTY_LP(1) &&
3611 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
3612 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
3613
3614 if (INTEL_GEN(dev_priv) >= 7) {
3615 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
3616 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
3617 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
3618 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
3619 }
3620
3621 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
3622 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
3623 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
3624 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
3625 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
3626 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
3627
3628 dev_priv->wm.hw = *results;
3629 }
3630
3631 bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
3632 {
3633 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3634 }
3635
3636 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
3637 {
3638 int i;
3639 int max_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
3640 u8 enabled_slices_mask = 0;
3641
3642 for (i = 0; i < max_slices; i++) {
3643 if (I915_READ(DBUF_CTL_S(i)) & DBUF_POWER_STATE)
3644 enabled_slices_mask |= BIT(i);
3645 }
3646
3647 return enabled_slices_mask;
3648 }
3649
3650 /*
3651 * FIXME: We still don't have the proper code detect if we need to apply the WA,
3652 * so assume we'll always need it in order to avoid underruns.
3653 */
3654 static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
3655 {
3656 return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
3657 }
3658
3659 static bool
3660 intel_has_sagv(struct drm_i915_private *dev_priv)
3661 {
3662 return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
3663 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
3664 }
3665
3666 static void
3667 skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
3668 {
3669 if (INTEL_GEN(dev_priv) >= 12) {
3670 u32 val = 0;
3671 int ret;
3672
3673 ret = sandybridge_pcode_read(dev_priv,
3674 GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
3675 &val, NULL);
3676 if (!ret) {
3677 dev_priv->sagv_block_time_us = val;
3678 return;
3679 }
3680
3681 drm_dbg(&dev_priv->drm, "Couldn't read SAGV block time!\n");
3682 } else if (IS_GEN(dev_priv, 11)) {
3683 dev_priv->sagv_block_time_us = 10;
3684 return;
3685 } else if (IS_GEN(dev_priv, 10)) {
3686 dev_priv->sagv_block_time_us = 20;
3687 return;
3688 } else if (IS_GEN(dev_priv, 9)) {
3689 dev_priv->sagv_block_time_us = 30;
3690 return;
3691 } else {
3692 MISSING_CASE(INTEL_GEN(dev_priv));
3693 }
3694
3695 /* Default to an unusable block time */
3696 dev_priv->sagv_block_time_us = -1;
3697 }
3698
3699 /*
3700 * SAGV dynamically adjusts the system agent voltage and clock frequencies
3701 * depending on power and performance requirements. The display engine access
3702 * to system memory is blocked during the adjustment time. Because of the
3703 * blocking time, having this enabled can cause full system hangs and/or pipe
3704 * underruns if we don't meet all of the following requirements:
3705 *
3706 * - <= 1 pipe enabled
3707 * - All planes can enable watermarks for latencies >= SAGV engine block time
3708 * - We're not using an interlaced display configuration
3709 */
3710 static int
3711 intel_enable_sagv(struct drm_i915_private *dev_priv)
3712 {
3713 int ret;
3714
3715 if (!intel_has_sagv(dev_priv))
3716 return 0;
3717
3718 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
3719 return 0;
3720
3721 drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
3722 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3723 GEN9_SAGV_ENABLE);
3724
3725 /* We don't need to wait for SAGV when enabling */
3726
3727 /*
3728 * Some skl systems, pre-release machines in particular,
3729 * don't actually have SAGV.
3730 */
3731 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3732 drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
3733 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3734 return 0;
3735 } else if (ret < 0) {
3736 drm_err(&dev_priv->drm, "Failed to enable SAGV\n");
3737 return ret;
3738 }
3739
3740 dev_priv->sagv_status = I915_SAGV_ENABLED;
3741 return 0;
3742 }
3743
3744 static int
3745 intel_disable_sagv(struct drm_i915_private *dev_priv)
3746 {
3747 int ret;
3748
3749 if (!intel_has_sagv(dev_priv))
3750 return 0;
3751
3752 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
3753 return 0;
3754
3755 drm_dbg_kms(&dev_priv->drm, "Disabling SAGV\n");
3756 /* bspec says to keep retrying for at least 1 ms */
3757 ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3758 GEN9_SAGV_DISABLE,
3759 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
3760 1);
3761 /*
3762 * Some skl systems, pre-release machines in particular,
3763 * don't actually have SAGV.
3764 */
3765 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3766 drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
3767 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3768 return 0;
3769 } else if (ret < 0) {
3770 drm_err(&dev_priv->drm, "Failed to disable SAGV (%d)\n", ret);
3771 return ret;
3772 }
3773
3774 dev_priv->sagv_status = I915_SAGV_DISABLED;
3775 return 0;
3776 }
3777
3778 void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
3779 {
3780 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3781 const struct intel_bw_state *new_bw_state;
3782 const struct intel_bw_state *old_bw_state;
3783 u32 new_mask = 0;
3784
3785 /*
3786 * Just return if we can't control SAGV or don't have it.
3787 * This is different from situation when we have SAGV but just can't
3788 * afford it due to DBuf limitation - in case if SAGV is completely
3789 * disabled in a BIOS, we are not even allowed to send a PCode request,
3790 * as it will throw an error. So have to check it here.
3791 */
3792 if (!intel_has_sagv(dev_priv))
3793 return;
3794
3795 new_bw_state = intel_atomic_get_new_bw_state(state);
3796 if (!new_bw_state)
3797 return;
3798
3799 if (INTEL_GEN(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv, new_bw_state)) {
3800 intel_disable_sagv(dev_priv);
3801 return;
3802 }
3803
3804 old_bw_state = intel_atomic_get_old_bw_state(state);
3805 /*
3806 * Nothing to mask
3807 */
3808 if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
3809 return;
3810
3811 new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
3812
3813 /*
3814 * If new mask is zero - means there is nothing to mask,
3815 * we can only unmask, which should be done in unmask.
3816 */
3817 if (!new_mask)
3818 return;
3819
3820 /*
3821 * Restrict required qgv points before updating the configuration.
3822 * According to BSpec we can't mask and unmask qgv points at the same
3823 * time. Also masking should be done before updating the configuration
3824 * and unmasking afterwards.
3825 */
3826 icl_pcode_restrict_qgv_points(dev_priv, new_mask);
3827 }
3828
3829 void intel_sagv_post_plane_update(struct intel_atomic_state *state)
3830 {
3831 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3832 const struct intel_bw_state *new_bw_state;
3833 const struct intel_bw_state *old_bw_state;
3834 u32 new_mask = 0;
3835
3836 /*
3837 * Just return if we can't control SAGV or don't have it.
3838 * This is different from situation when we have SAGV but just can't
3839 * afford it due to DBuf limitation - in case if SAGV is completely
3840 * disabled in a BIOS, we are not even allowed to send a PCode request,
3841 * as it will throw an error. So have to check it here.
3842 */
3843 if (!intel_has_sagv(dev_priv))
3844 return;
3845
3846 new_bw_state = intel_atomic_get_new_bw_state(state);
3847 if (!new_bw_state)
3848 return;
3849
3850 if (INTEL_GEN(dev_priv) < 11 && intel_can_enable_sagv(dev_priv, new_bw_state)) {
3851 intel_enable_sagv(dev_priv);
3852 return;
3853 }
3854
3855 old_bw_state = intel_atomic_get_old_bw_state(state);
3856 /*
3857 * Nothing to unmask
3858 */
3859 if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
3860 return;
3861
3862 new_mask = new_bw_state->qgv_points_mask;
3863
3864 /*
3865 * Allow required qgv points after updating the configuration.
3866 * According to BSpec we can't mask and unmask qgv points at the same
3867 * time. Also masking should be done before updating the configuration
3868 * and unmasking afterwards.
3869 */
3870 icl_pcode_restrict_qgv_points(dev_priv, new_mask);
3871 }
3872
3873 static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
3874 {
3875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3877 enum plane_id plane_id;
3878
3879 if (!intel_has_sagv(dev_priv))
3880 return false;
3881
3882 if (!crtc_state->hw.active)
3883 return true;
3884
3885 if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
3886 return false;
3887
3888 for_each_plane_id_on_crtc(crtc, plane_id) {
3889 const struct skl_plane_wm *wm =
3890 &crtc_state->wm.skl.optimal.planes[plane_id];
3891 int level;
3892
3893 /* Skip this plane if it's not enabled */
3894 if (!wm->wm[0].plane_en)
3895 continue;
3896
3897 /* Find the highest enabled wm level for this plane */
3898 for (level = ilk_wm_max_level(dev_priv);
3899 !wm->wm[level].plane_en; --level)
3900 { }
3901
3902 /*
3903 * If any of the planes on this pipe don't enable wm levels that
3904 * incur memory latencies higher than sagv_block_time_us we
3905 * can't enable SAGV.
3906 */
3907 if (!wm->wm[level].can_sagv)
3908 return false;
3909 }
3910
3911 return true;
3912 }
3913
3914 static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
3915 {
3916 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3917 enum plane_id plane_id;
3918
3919 if (!crtc_state->hw.active)
3920 return true;
3921
3922 for_each_plane_id_on_crtc(crtc, plane_id) {
3923 const struct skl_ddb_entry *plane_alloc =
3924 &crtc_state->wm.skl.plane_ddb_y[plane_id];
3925 const struct skl_plane_wm *wm =
3926 &crtc_state->wm.skl.optimal.planes[plane_id];
3927
3928 if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
3929 return false;
3930 }
3931
3932 return true;
3933 }
3934
3935 static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
3936 {
3937 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3938 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3939
3940 if (INTEL_GEN(dev_priv) >= 12)
3941 return tgl_crtc_can_enable_sagv(crtc_state);
3942 else
3943 return skl_crtc_can_enable_sagv(crtc_state);
3944 }
3945
3946 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
3947 const struct intel_bw_state *bw_state)
3948 {
3949 if (INTEL_GEN(dev_priv) < 11 &&
3950 bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
3951 return false;
3952
3953 return bw_state->pipe_sagv_reject == 0;
3954 }
3955
3956 static int intel_compute_sagv_mask(struct intel_atomic_state *state)
3957 {
3958 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3959 int ret;
3960 struct intel_crtc *crtc;
3961 struct intel_crtc_state *new_crtc_state;
3962 struct intel_bw_state *new_bw_state = NULL;
3963 const struct intel_bw_state *old_bw_state = NULL;
3964 int i;
3965
3966 for_each_new_intel_crtc_in_state(state, crtc,
3967 new_crtc_state, i) {
3968 new_bw_state = intel_atomic_get_bw_state(state);
3969 if (IS_ERR(new_bw_state))
3970 return PTR_ERR(new_bw_state);
3971
3972 old_bw_state = intel_atomic_get_old_bw_state(state);
3973
3974 if (intel_crtc_can_enable_sagv(new_crtc_state))
3975 new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
3976 else
3977 new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
3978 }
3979
3980 if (!new_bw_state)
3981 return 0;
3982
3983 new_bw_state->active_pipes =
3984 intel_calc_active_pipes(state, old_bw_state->active_pipes);
3985
3986 if (new_bw_state->active_pipes != old_bw_state->active_pipes) {
3987 ret = intel_atomic_lock_global_state(&new_bw_state->base);
3988 if (ret)
3989 return ret;
3990 }
3991
3992 for_each_new_intel_crtc_in_state(state, crtc,
3993 new_crtc_state, i) {
3994 struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
3995
3996 /*
3997 * We store use_sagv_wm in the crtc state rather than relying on
3998 * that bw state since we have no convenient way to get at the
3999 * latter from the plane commit hooks (especially in the legacy
4000 * cursor case)
4001 */
4002 pipe_wm->use_sagv_wm = INTEL_GEN(dev_priv) >= 12 &&
4003 intel_can_enable_sagv(dev_priv, new_bw_state);
4004 }
4005
4006 if (intel_can_enable_sagv(dev_priv, new_bw_state) !=
4007 intel_can_enable_sagv(dev_priv, old_bw_state)) {
4008 ret = intel_atomic_serialize_global_state(&new_bw_state->base);
4009 if (ret)
4010 return ret;
4011 } else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
4012 ret = intel_atomic_lock_global_state(&new_bw_state->base);
4013 if (ret)
4014 return ret;
4015 }
4016
4017 return 0;
4018 }
4019
4020 /*
4021 * Calculate initial DBuf slice offset, based on slice size
4022 * and mask(i.e if slice size is 1024 and second slice is enabled
4023 * offset would be 1024)
4024 */
4025 static unsigned int
4026 icl_get_first_dbuf_slice_offset(u32 dbuf_slice_mask,
4027 u32 slice_size,
4028 u32 ddb_size)
4029 {
4030 unsigned int offset = 0;
4031
4032 if (!dbuf_slice_mask)
4033 return 0;
4034
4035 offset = (ffs(dbuf_slice_mask) - 1) * slice_size;
4036
4037 WARN_ON(offset >= ddb_size);
4038 return offset;
4039 }
4040
4041 u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
4042 {
4043 u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
4044 drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
4045
4046 if (INTEL_GEN(dev_priv) < 11)
4047 return ddb_size - 4; /* 4 blocks for bypass path allocation */
4048
4049 return ddb_size;
4050 }
4051
4052 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
4053 const struct skl_ddb_entry *entry)
4054 {
4055 u32 slice_mask = 0;
4056 u16 ddb_size = intel_get_ddb_size(dev_priv);
4057 u16 num_supported_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
4058 u16 slice_size = ddb_size / num_supported_slices;
4059 u16 start_slice;
4060 u16 end_slice;
4061
4062 if (!skl_ddb_entry_size(entry))
4063 return 0;
4064
4065 start_slice = entry->start / slice_size;
4066 end_slice = (entry->end - 1) / slice_size;
4067
4068 /*
4069 * Per plane DDB entry can in a really worst case be on multiple slices
4070 * but single entry is anyway contigious.
4071 */
4072 while (start_slice <= end_slice) {
4073 slice_mask |= BIT(start_slice);
4074 start_slice++;
4075 }
4076
4077 return slice_mask;
4078 }
4079
4080 static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
4081 u8 active_pipes);
4082
4083 static int
4084 skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
4085 const struct intel_crtc_state *crtc_state,
4086 const u64 total_data_rate,
4087 struct skl_ddb_entry *alloc, /* out */
4088 int *num_active /* out */)
4089 {
4090 struct drm_atomic_state *state = crtc_state->uapi.state;
4091 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4092 struct drm_crtc *for_crtc = crtc_state->uapi.crtc;
4093 const struct intel_crtc *crtc;
4094 u32 pipe_width = 0, total_width_in_range = 0, width_before_pipe_in_range = 0;
4095 enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
4096 struct intel_dbuf_state *new_dbuf_state =
4097 intel_atomic_get_new_dbuf_state(intel_state);
4098 const struct intel_dbuf_state *old_dbuf_state =
4099 intel_atomic_get_old_dbuf_state(intel_state);
4100 u8 active_pipes = new_dbuf_state->active_pipes;
4101 u16 ddb_size;
4102 u32 ddb_range_size;
4103 u32 i;
4104 u32 dbuf_slice_mask;
4105 u32 offset;
4106 u32 slice_size;
4107 u32 total_slice_mask;
4108 u32 start, end;
4109 int ret;
4110
4111 *num_active = hweight8(active_pipes);
4112
4113 if (!crtc_state->hw.active) {
4114 alloc->start = 0;
4115 alloc->end = 0;
4116 return 0;
4117 }
4118
4119 ddb_size = intel_get_ddb_size(dev_priv);
4120
4121 slice_size = ddb_size / INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
4122
4123 /*
4124 * If the state doesn't change the active CRTC's or there is no
4125 * modeset request, then there's no need to recalculate;
4126 * the existing pipe allocation limits should remain unchanged.
4127 * Note that we're safe from racing commits since any racing commit
4128 * that changes the active CRTC list or do modeset would need to
4129 * grab _all_ crtc locks, including the one we currently hold.
4130 */
4131 if (old_dbuf_state->active_pipes == new_dbuf_state->active_pipes &&
4132 !dev_priv->wm.distrust_bios_wm) {
4133 /*
4134 * alloc may be cleared by clear_intel_crtc_state,
4135 * copy from old state to be sure
4136 *
4137 * FIXME get rid of this mess
4138 */
4139 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
4140 return 0;
4141 }
4142
4143 /*
4144 * Get allowed DBuf slices for correspondent pipe and platform.
4145 */
4146 dbuf_slice_mask = skl_compute_dbuf_slices(crtc_state, active_pipes);
4147
4148 /*
4149 * Figure out at which DBuf slice we start, i.e if we start at Dbuf S2
4150 * and slice size is 1024, the offset would be 1024
4151 */
4152 offset = icl_get_first_dbuf_slice_offset(dbuf_slice_mask,
4153 slice_size, ddb_size);
4154
4155 /*
4156 * Figure out total size of allowed DBuf slices, which is basically
4157 * a number of allowed slices for that pipe multiplied by slice size.
4158 * Inside of this
4159 * range ddb entries are still allocated in proportion to display width.
4160 */
4161 ddb_range_size = hweight8(dbuf_slice_mask) * slice_size;
4162
4163 /*
4164 * Watermark/ddb requirement highly depends upon width of the
4165 * framebuffer, So instead of allocating DDB equally among pipes
4166 * distribute DDB based on resolution/width of the display.
4167 */
4168 total_slice_mask = dbuf_slice_mask;
4169 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
4170 const struct drm_display_mode *pipe_mode =
4171 &crtc_state->hw.pipe_mode;
4172 enum pipe pipe = crtc->pipe;
4173 int hdisplay, vdisplay;
4174 u32 pipe_dbuf_slice_mask;
4175
4176 if (!crtc_state->hw.active)
4177 continue;
4178
4179 pipe_dbuf_slice_mask = skl_compute_dbuf_slices(crtc_state,
4180 active_pipes);
4181
4182 /*
4183 * According to BSpec pipe can share one dbuf slice with another
4184 * pipes or pipe can use multiple dbufs, in both cases we
4185 * account for other pipes only if they have exactly same mask.
4186 * However we need to account how many slices we should enable
4187 * in total.
4188 */
4189 total_slice_mask |= pipe_dbuf_slice_mask;
4190
4191 /*
4192 * Do not account pipes using other slice sets
4193 * luckily as of current BSpec slice sets do not partially
4194 * intersect(pipes share either same one slice or same slice set
4195 * i.e no partial intersection), so it is enough to check for
4196 * equality for now.
4197 */
4198 if (dbuf_slice_mask != pipe_dbuf_slice_mask)
4199 continue;
4200
4201 drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay);
4202
4203 total_width_in_range += hdisplay;
4204
4205 if (pipe < for_pipe)
4206 width_before_pipe_in_range += hdisplay;
4207 else if (pipe == for_pipe)
4208 pipe_width = hdisplay;
4209 }
4210
4211 /*
4212 * FIXME: For now we always enable slice S1 as per
4213 * the Bspec display initialization sequence.
4214 */
4215 new_dbuf_state->enabled_slices = total_slice_mask | BIT(DBUF_S1);
4216
4217 if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) {
4218 ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
4219 if (ret)
4220 return ret;
4221 }
4222
4223 start = ddb_range_size * width_before_pipe_in_range / total_width_in_range;
4224 end = ddb_range_size *
4225 (width_before_pipe_in_range + pipe_width) / total_width_in_range;
4226
4227 alloc->start = offset + start;
4228 alloc->end = offset + end;
4229
4230 drm_dbg_kms(&dev_priv->drm,
4231 "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n",
4232 for_crtc->base.id, for_crtc->name,
4233 dbuf_slice_mask, alloc->start, alloc->end, active_pipes);
4234
4235 return 0;
4236 }
4237
4238 static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
4239 int width, const struct drm_format_info *format,
4240 u64 modifier, unsigned int rotation,
4241 u32 plane_pixel_rate, struct skl_wm_params *wp,
4242 int color_plane);
4243 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
4244 int level,
4245 unsigned int latency,
4246 const struct skl_wm_params *wp,
4247 const struct skl_wm_level *result_prev,
4248 struct skl_wm_level *result /* out */);
4249
4250 static unsigned int
4251 skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
4252 int num_active)
4253 {
4254 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4255 int level, max_level = ilk_wm_max_level(dev_priv);
4256 struct skl_wm_level wm = {};
4257 int ret, min_ddb_alloc = 0;
4258 struct skl_wm_params wp;
4259
4260 ret = skl_compute_wm_params(crtc_state, 256,
4261 drm_format_info(DRM_FORMAT_ARGB8888),
4262 DRM_FORMAT_MOD_LINEAR,
4263 DRM_MODE_ROTATE_0,
4264 crtc_state->pixel_rate, &wp, 0);
4265 drm_WARN_ON(&dev_priv->drm, ret);
4266
4267 for (level = 0; level <= max_level; level++) {
4268 unsigned int latency = dev_priv->wm.skl_latency[level];
4269
4270 skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
4271 if (wm.min_ddb_alloc == U16_MAX)
4272 break;
4273
4274 min_ddb_alloc = wm.min_ddb_alloc;
4275 }
4276
4277 return max(num_active == 1 ? 32 : 8, min_ddb_alloc);
4278 }
4279
4280 static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
4281 struct skl_ddb_entry *entry, u32 reg)
4282 {
4283
4284 entry->start = reg & DDB_ENTRY_MASK;
4285 entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
4286
4287 if (entry->end)
4288 entry->end += 1;
4289 }
4290
4291 static void
4292 skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
4293 const enum pipe pipe,
4294 const enum plane_id plane_id,
4295 struct skl_ddb_entry *ddb_y,
4296 struct skl_ddb_entry *ddb_uv)
4297 {
4298 u32 val, val2;
4299 u32 fourcc = 0;
4300
4301 /* Cursor doesn't support NV12/planar, so no extra calculation needed */
4302 if (plane_id == PLANE_CURSOR) {
4303 val = I915_READ(CUR_BUF_CFG(pipe));
4304 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4305 return;
4306 }
4307
4308 val = I915_READ(PLANE_CTL(pipe, plane_id));
4309
4310 /* No DDB allocated for disabled planes */
4311 if (val & PLANE_CTL_ENABLE)
4312 fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
4313 val & PLANE_CTL_ORDER_RGBX,
4314 val & PLANE_CTL_ALPHA_MASK);
4315
4316 if (INTEL_GEN(dev_priv) >= 11) {
4317 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
4318 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4319 } else {
4320 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
4321 val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
4322
4323 if (fourcc &&
4324 drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
4325 swap(val, val2);
4326
4327 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4328 skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
4329 }
4330 }
4331
4332 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
4333 struct skl_ddb_entry *ddb_y,
4334 struct skl_ddb_entry *ddb_uv)
4335 {
4336 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4337 enum intel_display_power_domain power_domain;
4338 enum pipe pipe = crtc->pipe;
4339 intel_wakeref_t wakeref;
4340 enum plane_id plane_id;
4341
4342 power_domain = POWER_DOMAIN_PIPE(pipe);
4343 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4344 if (!wakeref)
4345 return;
4346
4347 for_each_plane_id_on_crtc(crtc, plane_id)
4348 skl_ddb_get_hw_plane_state(dev_priv, pipe,
4349 plane_id,
4350 &ddb_y[plane_id],
4351 &ddb_uv[plane_id]);
4352
4353 intel_display_power_put(dev_priv, power_domain, wakeref);
4354 }
4355
4356 /*
4357 * Determines the downscale amount of a plane for the purposes of watermark calculations.
4358 * The bspec defines downscale amount as:
4359 *
4360 * """
4361 * Horizontal down scale amount = maximum[1, Horizontal source size /
4362 * Horizontal destination size]
4363 * Vertical down scale amount = maximum[1, Vertical source size /
4364 * Vertical destination size]
4365 * Total down scale amount = Horizontal down scale amount *
4366 * Vertical down scale amount
4367 * """
4368 *
4369 * Return value is provided in 16.16 fixed point form to retain fractional part.
4370 * Caller should take care of dividing & rounding off the value.
4371 */
4372 static uint_fixed_16_16_t
4373 skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
4374 const struct intel_plane_state *plane_state)
4375 {
4376 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4377 u32 src_w, src_h, dst_w, dst_h;
4378 uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
4379 uint_fixed_16_16_t downscale_h, downscale_w;
4380
4381 if (drm_WARN_ON(&dev_priv->drm,
4382 !intel_wm_plane_visible(crtc_state, plane_state)))
4383 return u32_to_fixed16(0);
4384
4385 /*
4386 * Src coordinates are already rotated by 270 degrees for
4387 * the 90/270 degree plane rotation cases (to match the
4388 * GTT mapping), hence no need to account for rotation here.
4389 *
4390 * n.b., src is 16.16 fixed point, dst is whole integer.
4391 */
4392 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4393 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4394 dst_w = drm_rect_width(&plane_state->uapi.dst);
4395 dst_h = drm_rect_height(&plane_state->uapi.dst);
4396
4397 fp_w_ratio = div_fixed16(src_w, dst_w);
4398 fp_h_ratio = div_fixed16(src_h, dst_h);
4399 downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
4400 downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
4401
4402 return mul_fixed16(downscale_w, downscale_h);
4403 }
4404
4405 struct dbuf_slice_conf_entry {
4406 u8 active_pipes;
4407 u8 dbuf_mask[I915_MAX_PIPES];
4408 };
4409
4410 /*
4411 * Table taken from Bspec 12716
4412 * Pipes do have some preferred DBuf slice affinity,
4413 * plus there are some hardcoded requirements on how
4414 * those should be distributed for multipipe scenarios.
4415 * For more DBuf slices algorithm can get even more messy
4416 * and less readable, so decided to use a table almost
4417 * as is from BSpec itself - that way it is at least easier
4418 * to compare, change and check.
4419 */
4420 static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] =
4421 /* Autogenerated with igt/tools/intel_dbuf_map tool: */
4422 {
4423 {
4424 .active_pipes = BIT(PIPE_A),
4425 .dbuf_mask = {
4426 [PIPE_A] = BIT(DBUF_S1),
4427 },
4428 },
4429 {
4430 .active_pipes = BIT(PIPE_B),
4431 .dbuf_mask = {
4432 [PIPE_B] = BIT(DBUF_S1),
4433 },
4434 },
4435 {
4436 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
4437 .dbuf_mask = {
4438 [PIPE_A] = BIT(DBUF_S1),
4439 [PIPE_B] = BIT(DBUF_S2),
4440 },
4441 },
4442 {
4443 .active_pipes = BIT(PIPE_C),
4444 .dbuf_mask = {
4445 [PIPE_C] = BIT(DBUF_S2),
4446 },
4447 },
4448 {
4449 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
4450 .dbuf_mask = {
4451 [PIPE_A] = BIT(DBUF_S1),
4452 [PIPE_C] = BIT(DBUF_S2),
4453 },
4454 },
4455 {
4456 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
4457 .dbuf_mask = {
4458 [PIPE_B] = BIT(DBUF_S1),
4459 [PIPE_C] = BIT(DBUF_S2),
4460 },
4461 },
4462 {
4463 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
4464 .dbuf_mask = {
4465 [PIPE_A] = BIT(DBUF_S1),
4466 [PIPE_B] = BIT(DBUF_S1),
4467 [PIPE_C] = BIT(DBUF_S2),
4468 },
4469 },
4470 {}
4471 };
4472
4473 /*
4474 * Table taken from Bspec 49255
4475 * Pipes do have some preferred DBuf slice affinity,
4476 * plus there are some hardcoded requirements on how
4477 * those should be distributed for multipipe scenarios.
4478 * For more DBuf slices algorithm can get even more messy
4479 * and less readable, so decided to use a table almost
4480 * as is from BSpec itself - that way it is at least easier
4481 * to compare, change and check.
4482 */
4483 static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =
4484 /* Autogenerated with igt/tools/intel_dbuf_map tool: */
4485 {
4486 {
4487 .active_pipes = BIT(PIPE_A),
4488 .dbuf_mask = {
4489 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4490 },
4491 },
4492 {
4493 .active_pipes = BIT(PIPE_B),
4494 .dbuf_mask = {
4495 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
4496 },
4497 },
4498 {
4499 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
4500 .dbuf_mask = {
4501 [PIPE_A] = BIT(DBUF_S2),
4502 [PIPE_B] = BIT(DBUF_S1),
4503 },
4504 },
4505 {
4506 .active_pipes = BIT(PIPE_C),
4507 .dbuf_mask = {
4508 [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1),
4509 },
4510 },
4511 {
4512 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
4513 .dbuf_mask = {
4514 [PIPE_A] = BIT(DBUF_S1),
4515 [PIPE_C] = BIT(DBUF_S2),
4516 },
4517 },
4518 {
4519 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
4520 .dbuf_mask = {
4521 [PIPE_B] = BIT(DBUF_S1),
4522 [PIPE_C] = BIT(DBUF_S2),
4523 },
4524 },
4525 {
4526 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
4527 .dbuf_mask = {
4528 [PIPE_A] = BIT(DBUF_S1),
4529 [PIPE_B] = BIT(DBUF_S1),
4530 [PIPE_C] = BIT(DBUF_S2),
4531 },
4532 },
4533 {
4534 .active_pipes = BIT(PIPE_D),
4535 .dbuf_mask = {
4536 [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1),
4537 },
4538 },
4539 {
4540 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
4541 .dbuf_mask = {
4542 [PIPE_A] = BIT(DBUF_S1),
4543 [PIPE_D] = BIT(DBUF_S2),
4544 },
4545 },
4546 {
4547 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
4548 .dbuf_mask = {
4549 [PIPE_B] = BIT(DBUF_S1),
4550 [PIPE_D] = BIT(DBUF_S2),
4551 },
4552 },
4553 {
4554 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
4555 .dbuf_mask = {
4556 [PIPE_A] = BIT(DBUF_S1),
4557 [PIPE_B] = BIT(DBUF_S1),
4558 [PIPE_D] = BIT(DBUF_S2),
4559 },
4560 },
4561 {
4562 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
4563 .dbuf_mask = {
4564 [PIPE_C] = BIT(DBUF_S1),
4565 [PIPE_D] = BIT(DBUF_S2),
4566 },
4567 },
4568 {
4569 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
4570 .dbuf_mask = {
4571 [PIPE_A] = BIT(DBUF_S1),
4572 [PIPE_C] = BIT(DBUF_S2),
4573 [PIPE_D] = BIT(DBUF_S2),
4574 },
4575 },
4576 {
4577 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4578 .dbuf_mask = {
4579 [PIPE_B] = BIT(DBUF_S1),
4580 [PIPE_C] = BIT(DBUF_S2),
4581 [PIPE_D] = BIT(DBUF_S2),
4582 },
4583 },
4584 {
4585 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4586 .dbuf_mask = {
4587 [PIPE_A] = BIT(DBUF_S1),
4588 [PIPE_B] = BIT(DBUF_S1),
4589 [PIPE_C] = BIT(DBUF_S2),
4590 [PIPE_D] = BIT(DBUF_S2),
4591 },
4592 },
4593 {}
4594 };
4595
4596 static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes,
4597 const struct dbuf_slice_conf_entry *dbuf_slices)
4598 {
4599 int i;
4600
4601 for (i = 0; i < dbuf_slices[i].active_pipes; i++) {
4602 if (dbuf_slices[i].active_pipes == active_pipes)
4603 return dbuf_slices[i].dbuf_mask[pipe];
4604 }
4605 return 0;
4606 }
4607
4608 /*
4609 * This function finds an entry with same enabled pipe configuration and
4610 * returns correspondent DBuf slice mask as stated in BSpec for particular
4611 * platform.
4612 */
4613 static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
4614 {
4615 /*
4616 * FIXME: For ICL this is still a bit unclear as prev BSpec revision
4617 * required calculating "pipe ratio" in order to determine
4618 * if one or two slices can be used for single pipe configurations
4619 * as additional constraint to the existing table.
4620 * However based on recent info, it should be not "pipe ratio"
4621 * but rather ratio between pixel_rate and cdclk with additional
4622 * constants, so for now we are using only table until this is
4623 * clarified. Also this is the reason why crtc_state param is
4624 * still here - we will need it once those additional constraints
4625 * pop up.
4626 */
4627 return compute_dbuf_slices(pipe, active_pipes, icl_allowed_dbufs);
4628 }
4629
4630 static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
4631 {
4632 return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs);
4633 }
4634
4635 static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
4636 u8 active_pipes)
4637 {
4638 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4639 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4640 enum pipe pipe = crtc->pipe;
4641
4642 if (IS_GEN(dev_priv, 12))
4643 return tgl_compute_dbuf_slices(pipe, active_pipes);
4644 else if (IS_GEN(dev_priv, 11))
4645 return icl_compute_dbuf_slices(pipe, active_pipes);
4646 /*
4647 * For anything else just return one slice yet.
4648 * Should be extended for other platforms.
4649 */
4650 return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
4651 }
4652
4653 static u64
4654 skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
4655 const struct intel_plane_state *plane_state,
4656 int color_plane)
4657 {
4658 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4659 const struct drm_framebuffer *fb = plane_state->hw.fb;
4660 u32 data_rate;
4661 u32 width = 0, height = 0;
4662 uint_fixed_16_16_t down_scale_amount;
4663 u64 rate;
4664
4665 if (!plane_state->uapi.visible)
4666 return 0;
4667
4668 if (plane->id == PLANE_CURSOR)
4669 return 0;
4670
4671 if (color_plane == 1 &&
4672 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
4673 return 0;
4674
4675 /*
4676 * Src coordinates are already rotated by 270 degrees for
4677 * the 90/270 degree plane rotation cases (to match the
4678 * GTT mapping), hence no need to account for rotation here.
4679 */
4680 width = drm_rect_width(&plane_state->uapi.src) >> 16;
4681 height = drm_rect_height(&plane_state->uapi.src) >> 16;
4682
4683 /* UV plane does 1/2 pixel sub-sampling */
4684 if (color_plane == 1) {
4685 width /= 2;
4686 height /= 2;
4687 }
4688
4689 data_rate = width * height;
4690
4691 down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
4692
4693 rate = mul_round_up_u32_fixed16(data_rate, down_scale_amount);
4694
4695 rate *= fb->format->cpp[color_plane];
4696 return rate;
4697 }
4698
4699 static u64
4700 skl_get_total_relative_data_rate(struct intel_atomic_state *state,
4701 struct intel_crtc *crtc)
4702 {
4703 struct intel_crtc_state *crtc_state =
4704 intel_atomic_get_new_crtc_state(state, crtc);
4705 const struct intel_plane_state *plane_state;
4706 struct intel_plane *plane;
4707 u64 total_data_rate = 0;
4708 enum plane_id plane_id;
4709 int i;
4710
4711 /* Calculate and cache data rate for each plane */
4712 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4713 if (plane->pipe != crtc->pipe)
4714 continue;
4715
4716 plane_id = plane->id;
4717
4718 /* packed/y */
4719 crtc_state->plane_data_rate[plane_id] =
4720 skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4721
4722 /* uv-plane */
4723 crtc_state->uv_plane_data_rate[plane_id] =
4724 skl_plane_relative_data_rate(crtc_state, plane_state, 1);
4725 }
4726
4727 for_each_plane_id_on_crtc(crtc, plane_id) {
4728 total_data_rate += crtc_state->plane_data_rate[plane_id];
4729 total_data_rate += crtc_state->uv_plane_data_rate[plane_id];
4730 }
4731
4732 return total_data_rate;
4733 }
4734
4735 static u64
4736 icl_get_total_relative_data_rate(struct intel_atomic_state *state,
4737 struct intel_crtc *crtc)
4738 {
4739 struct intel_crtc_state *crtc_state =
4740 intel_atomic_get_new_crtc_state(state, crtc);
4741 const struct intel_plane_state *plane_state;
4742 struct intel_plane *plane;
4743 u64 total_data_rate = 0;
4744 enum plane_id plane_id;
4745 int i;
4746
4747 /* Calculate and cache data rate for each plane */
4748 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4749 if (plane->pipe != crtc->pipe)
4750 continue;
4751
4752 plane_id = plane->id;
4753
4754 if (!plane_state->planar_linked_plane) {
4755 crtc_state->plane_data_rate[plane_id] =
4756 skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4757 } else {
4758 enum plane_id y_plane_id;
4759
4760 /*
4761 * The slave plane might not iterate in
4762 * intel_atomic_crtc_state_for_each_plane_state(),
4763 * and needs the master plane state which may be
4764 * NULL if we try get_new_plane_state(), so we
4765 * always calculate from the master.
4766 */
4767 if (plane_state->planar_slave)
4768 continue;
4769
4770 /* Y plane rate is calculated on the slave */
4771 y_plane_id = plane_state->planar_linked_plane->id;
4772 crtc_state->plane_data_rate[y_plane_id] =
4773 skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4774
4775 crtc_state->plane_data_rate[plane_id] =
4776 skl_plane_relative_data_rate(crtc_state, plane_state, 1);
4777 }
4778 }
4779
4780 for_each_plane_id_on_crtc(crtc, plane_id)
4781 total_data_rate += crtc_state->plane_data_rate[plane_id];
4782
4783 return total_data_rate;
4784 }
4785
4786 static const struct skl_wm_level *
4787 skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
4788 enum plane_id plane_id,
4789 int level)
4790 {
4791 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
4792 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
4793
4794 if (level == 0 && pipe_wm->use_sagv_wm)
4795 return &wm->sagv_wm0;
4796
4797 return &wm->wm[level];
4798 }
4799
4800 static int
4801 skl_allocate_pipe_ddb(struct intel_atomic_state *state,
4802 struct intel_crtc *crtc)
4803 {
4804 struct intel_crtc_state *crtc_state =
4805 intel_atomic_get_new_crtc_state(state, crtc);
4806 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4807 struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
4808 u16 alloc_size, start = 0;
4809 u16 total[I915_MAX_PLANES] = {};
4810 u16 uv_total[I915_MAX_PLANES] = {};
4811 u64 total_data_rate;
4812 enum plane_id plane_id;
4813 int num_active;
4814 u32 blocks;
4815 int level;
4816 int ret;
4817
4818 /* Clear the partitioning for disabled planes. */
4819 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
4820 memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
4821
4822 if (!crtc_state->hw.active) {
4823 struct intel_atomic_state *state =
4824 to_intel_atomic_state(crtc_state->uapi.state);
4825 struct intel_dbuf_state *new_dbuf_state =
4826 intel_atomic_get_new_dbuf_state(state);
4827 const struct intel_dbuf_state *old_dbuf_state =
4828 intel_atomic_get_old_dbuf_state(state);
4829
4830 /*
4831 * FIXME hack to make sure we compute this sensibly when
4832 * turning off all the pipes. Otherwise we leave it at
4833 * whatever we had previously, and then runtime PM will
4834 * mess it up by turning off all but S1. Remove this
4835 * once the dbuf state computation flow becomes sane.
4836 */
4837 if (new_dbuf_state->active_pipes == 0) {
4838 new_dbuf_state->enabled_slices = BIT(DBUF_S1);
4839
4840 if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) {
4841 ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
4842 if (ret)
4843 return ret;
4844 }
4845 }
4846
4847 alloc->start = alloc->end = 0;
4848 return 0;
4849 }
4850
4851 if (INTEL_GEN(dev_priv) >= 11)
4852 total_data_rate =
4853 icl_get_total_relative_data_rate(state, crtc);
4854 else
4855 total_data_rate =
4856 skl_get_total_relative_data_rate(state, crtc);
4857
4858 ret = skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
4859 total_data_rate,
4860 alloc, &num_active);
4861 if (ret)
4862 return ret;
4863
4864 alloc_size = skl_ddb_entry_size(alloc);
4865 if (alloc_size == 0)
4866 return 0;
4867
4868 /* Allocate fixed number of blocks for cursor. */
4869 total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
4870 alloc_size -= total[PLANE_CURSOR];
4871 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
4872 alloc->end - total[PLANE_CURSOR];
4873 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
4874
4875 if (total_data_rate == 0)
4876 return 0;
4877
4878 /*
4879 * Find the highest watermark level for which we can satisfy the block
4880 * requirement of active planes.
4881 */
4882 for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
4883 blocks = 0;
4884 for_each_plane_id_on_crtc(crtc, plane_id) {
4885 const struct skl_plane_wm *wm =
4886 &crtc_state->wm.skl.optimal.planes[plane_id];
4887
4888 if (plane_id == PLANE_CURSOR) {
4889 if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
4890 drm_WARN_ON(&dev_priv->drm,
4891 wm->wm[level].min_ddb_alloc != U16_MAX);
4892 blocks = U32_MAX;
4893 break;
4894 }
4895 continue;
4896 }
4897
4898 blocks += wm->wm[level].min_ddb_alloc;
4899 blocks += wm->uv_wm[level].min_ddb_alloc;
4900 }
4901
4902 if (blocks <= alloc_size) {
4903 alloc_size -= blocks;
4904 break;
4905 }
4906 }
4907
4908 if (level < 0) {
4909 drm_dbg_kms(&dev_priv->drm,
4910 "Requested display configuration exceeds system DDB limitations");
4911 drm_dbg_kms(&dev_priv->drm, "minimum required %d/%d\n",
4912 blocks, alloc_size);
4913 return -EINVAL;
4914 }
4915
4916 /*
4917 * Grant each plane the blocks it requires at the highest achievable
4918 * watermark level, plus an extra share of the leftover blocks
4919 * proportional to its relative data rate.
4920 */
4921 for_each_plane_id_on_crtc(crtc, plane_id) {
4922 const struct skl_plane_wm *wm =
4923 &crtc_state->wm.skl.optimal.planes[plane_id];
4924 u64 rate;
4925 u16 extra;
4926
4927 if (plane_id == PLANE_CURSOR)
4928 continue;
4929
4930 /*
4931 * We've accounted for all active planes; remaining planes are
4932 * all disabled.
4933 */
4934 if (total_data_rate == 0)
4935 break;
4936
4937 rate = crtc_state->plane_data_rate[plane_id];
4938 extra = min_t(u16, alloc_size,
4939 DIV64_U64_ROUND_UP(alloc_size * rate,
4940 total_data_rate));
4941 total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
4942 alloc_size -= extra;
4943 total_data_rate -= rate;
4944
4945 if (total_data_rate == 0)
4946 break;
4947
4948 rate = crtc_state->uv_plane_data_rate[plane_id];
4949 extra = min_t(u16, alloc_size,
4950 DIV64_U64_ROUND_UP(alloc_size * rate,
4951 total_data_rate));
4952 uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
4953 alloc_size -= extra;
4954 total_data_rate -= rate;
4955 }
4956 drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
4957
4958 /* Set the actual DDB start/end points for each plane */
4959 start = alloc->start;
4960 for_each_plane_id_on_crtc(crtc, plane_id) {
4961 struct skl_ddb_entry *plane_alloc =
4962 &crtc_state->wm.skl.plane_ddb_y[plane_id];
4963 struct skl_ddb_entry *uv_plane_alloc =
4964 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
4965
4966 if (plane_id == PLANE_CURSOR)
4967 continue;
4968
4969 /* Gen11+ uses a separate plane for UV watermarks */
4970 drm_WARN_ON(&dev_priv->drm,
4971 INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
4972
4973 /* Leave disabled planes at (0,0) */
4974 if (total[plane_id]) {
4975 plane_alloc->start = start;
4976 start += total[plane_id];
4977 plane_alloc->end = start;
4978 }
4979
4980 if (uv_total[plane_id]) {
4981 uv_plane_alloc->start = start;
4982 start += uv_total[plane_id];
4983 uv_plane_alloc->end = start;
4984 }
4985 }
4986
4987 /*
4988 * When we calculated watermark values we didn't know how high
4989 * of a level we'd actually be able to hit, so we just marked
4990 * all levels as "enabled." Go back now and disable the ones
4991 * that aren't actually possible.
4992 */
4993 for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
4994 for_each_plane_id_on_crtc(crtc, plane_id) {
4995 struct skl_plane_wm *wm =
4996 &crtc_state->wm.skl.optimal.planes[plane_id];
4997
4998 /*
4999 * We only disable the watermarks for each plane if
5000 * they exceed the ddb allocation of said plane. This
5001 * is done so that we don't end up touching cursor
5002 * watermarks needlessly when some other plane reduces
5003 * our max possible watermark level.
5004 *
5005 * Bspec has this to say about the PLANE_WM enable bit:
5006 * "All the watermarks at this level for all enabled
5007 * planes must be enabled before the level will be used."
5008 * So this is actually safe to do.
5009 */
5010 if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
5011 wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
5012 memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
5013
5014 /*
5015 * Wa_1408961008:icl, ehl
5016 * Underruns with WM1+ disabled
5017 */
5018 if (IS_GEN(dev_priv, 11) &&
5019 level == 1 && wm->wm[0].plane_en) {
5020 wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
5021 wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
5022 wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
5023 }
5024 }
5025 }
5026
5027 /*
5028 * Go back and disable the transition watermark if it turns out we
5029 * don't have enough DDB blocks for it.
5030 */
5031 for_each_plane_id_on_crtc(crtc, plane_id) {
5032 struct skl_plane_wm *wm =
5033 &crtc_state->wm.skl.optimal.planes[plane_id];
5034
5035 if (wm->trans_wm.plane_res_b >= total[plane_id])
5036 memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
5037 }
5038
5039 return 0;
5040 }
5041
5042 /*
5043 * The max latency should be 257 (max the punit can code is 255 and we add 2us
5044 * for the read latency) and cpp should always be <= 8, so that
5045 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
5046 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
5047 */
5048 static uint_fixed_16_16_t
5049 skl_wm_method1(const struct drm_i915_private *dev_priv, u32 pixel_rate,
5050 u8 cpp, u32 latency, u32 dbuf_block_size)
5051 {
5052 u32 wm_intermediate_val;
5053 uint_fixed_16_16_t ret;
5054
5055 if (latency == 0)
5056 return FP_16_16_MAX;
5057
5058 wm_intermediate_val = latency * pixel_rate * cpp;
5059 ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
5060
5061 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
5062 ret = add_fixed16_u32(ret, 1);
5063
5064 return ret;
5065 }
5066
5067 static uint_fixed_16_16_t
5068 skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
5069 uint_fixed_16_16_t plane_blocks_per_line)
5070 {
5071 u32 wm_intermediate_val;
5072 uint_fixed_16_16_t ret;
5073
5074 if (latency == 0)
5075 return FP_16_16_MAX;
5076
5077 wm_intermediate_val = latency * pixel_rate;
5078 wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
5079 pipe_htotal * 1000);
5080 ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line);
5081 return ret;
5082 }
5083
5084 static uint_fixed_16_16_t
5085 intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
5086 {
5087 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5088 u32 pixel_rate;
5089 u32 crtc_htotal;
5090 uint_fixed_16_16_t linetime_us;
5091
5092 if (!crtc_state->hw.active)
5093 return u32_to_fixed16(0);
5094
5095 pixel_rate = crtc_state->pixel_rate;
5096
5097 if (drm_WARN_ON(&dev_priv->drm, pixel_rate == 0))
5098 return u32_to_fixed16(0);
5099
5100 crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal;
5101 linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
5102
5103 return linetime_us;
5104 }
5105
5106 static int
5107 skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
5108 int width, const struct drm_format_info *format,
5109 u64 modifier, unsigned int rotation,
5110 u32 plane_pixel_rate, struct skl_wm_params *wp,
5111 int color_plane)
5112 {
5113 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5114 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5115 u32 interm_pbpl;
5116
5117 /* only planar format has two planes */
5118 if (color_plane == 1 &&
5119 !intel_format_info_is_yuv_semiplanar(format, modifier)) {
5120 drm_dbg_kms(&dev_priv->drm,
5121 "Non planar format have single plane\n");
5122 return -EINVAL;
5123 }
5124
5125 wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
5126 modifier == I915_FORMAT_MOD_Yf_TILED ||
5127 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
5128 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
5129 wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED;
5130 wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
5131 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
5132 wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier);
5133
5134 wp->width = width;
5135 if (color_plane == 1 && wp->is_planar)
5136 wp->width /= 2;
5137
5138 wp->cpp = format->cpp[color_plane];
5139 wp->plane_pixel_rate = plane_pixel_rate;
5140
5141 if (INTEL_GEN(dev_priv) >= 11 &&
5142 modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)
5143 wp->dbuf_block_size = 256;
5144 else
5145 wp->dbuf_block_size = 512;
5146
5147 if (drm_rotation_90_or_270(rotation)) {
5148 switch (wp->cpp) {
5149 case 1:
5150 wp->y_min_scanlines = 16;
5151 break;
5152 case 2:
5153 wp->y_min_scanlines = 8;
5154 break;
5155 case 4:
5156 wp->y_min_scanlines = 4;
5157 break;
5158 default:
5159 MISSING_CASE(wp->cpp);
5160 return -EINVAL;
5161 }
5162 } else {
5163 wp->y_min_scanlines = 4;
5164 }
5165
5166 if (skl_needs_memory_bw_wa(dev_priv))
5167 wp->y_min_scanlines *= 2;
5168
5169 wp->plane_bytes_per_line = wp->width * wp->cpp;
5170 if (wp->y_tiled) {
5171 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
5172 wp->y_min_scanlines,
5173 wp->dbuf_block_size);
5174
5175 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
5176 interm_pbpl++;
5177
5178 wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
5179 wp->y_min_scanlines);
5180 } else {
5181 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
5182 wp->dbuf_block_size);
5183
5184 if (!wp->x_tiled ||
5185 INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
5186 interm_pbpl++;
5187
5188 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
5189 }
5190
5191 wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,
5192 wp->plane_blocks_per_line);
5193
5194 wp->linetime_us = fixed16_to_u32_round_up(
5195 intel_get_linetime_us(crtc_state));
5196
5197 return 0;
5198 }
5199
5200 static int
5201 skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
5202 const struct intel_plane_state *plane_state,
5203 struct skl_wm_params *wp, int color_plane)
5204 {
5205 const struct drm_framebuffer *fb = plane_state->hw.fb;
5206 int width;
5207
5208 /*
5209 * Src coordinates are already rotated by 270 degrees for
5210 * the 90/270 degree plane rotation cases (to match the
5211 * GTT mapping), hence no need to account for rotation here.
5212 */
5213 width = drm_rect_width(&plane_state->uapi.src) >> 16;
5214
5215 return skl_compute_wm_params(crtc_state, width,
5216 fb->format, fb->modifier,
5217 plane_state->hw.rotation,
5218 intel_plane_pixel_rate(crtc_state, plane_state),
5219 wp, color_plane);
5220 }
5221
5222 static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
5223 {
5224 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
5225 return true;
5226
5227 /* The number of lines are ignored for the level 0 watermark. */
5228 return level > 0;
5229 }
5230
5231 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
5232 int level,
5233 unsigned int latency,
5234 const struct skl_wm_params *wp,
5235 const struct skl_wm_level *result_prev,
5236 struct skl_wm_level *result /* out */)
5237 {
5238 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5239 uint_fixed_16_16_t method1, method2;
5240 uint_fixed_16_16_t selected_result;
5241 u32 res_blocks, res_lines, min_ddb_alloc = 0;
5242
5243 if (latency == 0) {
5244 /* reject it */
5245 result->min_ddb_alloc = U16_MAX;
5246 return;
5247 }
5248
5249 /*
5250 * WaIncreaseLatencyIPCEnabled: kbl,cfl
5251 * Display WA #1141: kbl,cfl
5252 */
5253 if ((IS_KABYLAKE(dev_priv) ||
5254 IS_COFFEELAKE(dev_priv) ||
5255 IS_COMETLAKE(dev_priv)) &&
5256 dev_priv->ipc_enabled)
5257 latency += 4;
5258
5259 if (skl_needs_memory_bw_wa(dev_priv) && wp->x_tiled)
5260 latency += 15;
5261
5262 method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
5263 wp->cpp, latency, wp->dbuf_block_size);
5264 method2 = skl_wm_method2(wp->plane_pixel_rate,
5265 crtc_state->hw.pipe_mode.crtc_htotal,
5266 latency,
5267 wp->plane_blocks_per_line);
5268
5269 if (wp->y_tiled) {
5270 selected_result = max_fixed16(method2, wp->y_tile_minimum);
5271 } else {
5272 if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
5273 wp->dbuf_block_size < 1) &&
5274 (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
5275 selected_result = method2;
5276 } else if (latency >= wp->linetime_us) {
5277 if (IS_GEN(dev_priv, 9) &&
5278 !IS_GEMINILAKE(dev_priv))
5279 selected_result = min_fixed16(method1, method2);
5280 else
5281 selected_result = method2;
5282 } else {
5283 selected_result = method1;
5284 }
5285 }
5286
5287 res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
5288 res_lines = div_round_up_fixed16(selected_result,
5289 wp->plane_blocks_per_line);
5290
5291 if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
5292 /* Display WA #1125: skl,bxt,kbl */
5293 if (level == 0 && wp->rc_surface)
5294 res_blocks +=
5295 fixed16_to_u32_round_up(wp->y_tile_minimum);
5296
5297 /* Display WA #1126: skl,bxt,kbl */
5298 if (level >= 1 && level <= 7) {
5299 if (wp->y_tiled) {
5300 res_blocks +=
5301 fixed16_to_u32_round_up(wp->y_tile_minimum);
5302 res_lines += wp->y_min_scanlines;
5303 } else {
5304 res_blocks++;
5305 }
5306
5307 /*
5308 * Make sure result blocks for higher latency levels are
5309 * atleast as high as level below the current level.
5310 * Assumption in DDB algorithm optimization for special
5311 * cases. Also covers Display WA #1125 for RC.
5312 */
5313 if (result_prev->plane_res_b > res_blocks)
5314 res_blocks = result_prev->plane_res_b;
5315 }
5316 }
5317
5318 if (INTEL_GEN(dev_priv) >= 11) {
5319 if (wp->y_tiled) {
5320 int extra_lines;
5321
5322 if (res_lines % wp->y_min_scanlines == 0)
5323 extra_lines = wp->y_min_scanlines;
5324 else
5325 extra_lines = wp->y_min_scanlines * 2 -
5326 res_lines % wp->y_min_scanlines;
5327
5328 min_ddb_alloc = mul_round_up_u32_fixed16(res_lines + extra_lines,
5329 wp->plane_blocks_per_line);
5330 } else {
5331 min_ddb_alloc = res_blocks +
5332 DIV_ROUND_UP(res_blocks, 10);
5333 }
5334 }
5335
5336 if (!skl_wm_has_lines(dev_priv, level))
5337 res_lines = 0;
5338
5339 if (res_lines > 31) {
5340 /* reject it */
5341 result->min_ddb_alloc = U16_MAX;
5342 return;
5343 }
5344
5345 /*
5346 * If res_lines is valid, assume we can use this watermark level
5347 * for now. We'll come back and disable it after we calculate the
5348 * DDB allocation if it turns out we don't actually have enough
5349 * blocks to satisfy it.
5350 */
5351 result->plane_res_b = res_blocks;
5352 result->plane_res_l = res_lines;
5353 /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
5354 result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
5355 result->plane_en = true;
5356
5357 if (INTEL_GEN(dev_priv) < 12)
5358 result->can_sagv = latency >= dev_priv->sagv_block_time_us;
5359 }
5360
5361 static void
5362 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
5363 const struct skl_wm_params *wm_params,
5364 struct skl_wm_level *levels)
5365 {
5366 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5367 int level, max_level = ilk_wm_max_level(dev_priv);
5368 struct skl_wm_level *result_prev = &levels[0];
5369
5370 for (level = 0; level <= max_level; level++) {
5371 struct skl_wm_level *result = &levels[level];
5372 unsigned int latency = dev_priv->wm.skl_latency[level];
5373
5374 skl_compute_plane_wm(crtc_state, level, latency,
5375 wm_params, result_prev, result);
5376
5377 result_prev = result;
5378 }
5379 }
5380
5381 static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
5382 const struct skl_wm_params *wm_params,
5383 struct skl_plane_wm *plane_wm)
5384 {
5385 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5386 struct skl_wm_level *sagv_wm = &plane_wm->sagv_wm0;
5387 struct skl_wm_level *levels = plane_wm->wm;
5388 unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us;
5389
5390 skl_compute_plane_wm(crtc_state, 0, latency,
5391 wm_params, &levels[0],
5392 sagv_wm);
5393 }
5394
5395 static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
5396 const struct skl_wm_params *wp,
5397 struct skl_plane_wm *wm)
5398 {
5399 struct drm_device *dev = crtc_state->uapi.crtc->dev;
5400 const struct drm_i915_private *dev_priv = to_i915(dev);
5401 u16 trans_min, trans_amount, trans_y_tile_min;
5402 u16 wm0_sel_res_b, trans_offset_b, res_blocks;
5403
5404 /* Transition WM don't make any sense if ipc is disabled */
5405 if (!dev_priv->ipc_enabled)
5406 return;
5407
5408 /*
5409 * WaDisableTWM:skl,kbl,cfl,bxt
5410 * Transition WM are not recommended by HW team for GEN9
5411 */
5412 if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
5413 return;
5414
5415 if (INTEL_GEN(dev_priv) >= 11)
5416 trans_min = 4;
5417 else
5418 trans_min = 14;
5419
5420 /* Display WA #1140: glk,cnl */
5421 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
5422 trans_amount = 0;
5423 else
5424 trans_amount = 10; /* This is configurable amount */
5425
5426 trans_offset_b = trans_min + trans_amount;
5427
5428 /*
5429 * The spec asks for Selected Result Blocks for wm0 (the real value),
5430 * not Result Blocks (the integer value). Pay attention to the capital
5431 * letters. The value wm_l0->plane_res_b is actually Result Blocks, but
5432 * since Result Blocks is the ceiling of Selected Result Blocks plus 1,
5433 * and since we later will have to get the ceiling of the sum in the
5434 * transition watermarks calculation, we can just pretend Selected
5435 * Result Blocks is Result Blocks minus 1 and it should work for the
5436 * current platforms.
5437 */
5438 wm0_sel_res_b = wm->wm[0].plane_res_b - 1;
5439
5440 if (wp->y_tiled) {
5441 trans_y_tile_min =
5442 (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum);
5443 res_blocks = max(wm0_sel_res_b, trans_y_tile_min) +
5444 trans_offset_b;
5445 } else {
5446 res_blocks = wm0_sel_res_b + trans_offset_b;
5447 }
5448
5449 /*
5450 * Just assume we can enable the transition watermark. After
5451 * computing the DDB we'll come back and disable it if that
5452 * assumption turns out to be false.
5453 */
5454 wm->trans_wm.plane_res_b = res_blocks + 1;
5455 wm->trans_wm.plane_en = true;
5456 }
5457
5458 static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
5459 const struct intel_plane_state *plane_state,
5460 enum plane_id plane_id, int color_plane)
5461 {
5462 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5463 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5464 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
5465 struct skl_wm_params wm_params;
5466 int ret;
5467
5468 ret = skl_compute_plane_wm_params(crtc_state, plane_state,
5469 &wm_params, color_plane);
5470 if (ret)
5471 return ret;
5472
5473 skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
5474
5475 if (INTEL_GEN(dev_priv) >= 12)
5476 tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
5477
5478 skl_compute_transition_wm(crtc_state, &wm_params, wm);
5479
5480 return 0;
5481 }
5482
5483 static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
5484 const struct intel_plane_state *plane_state,
5485 enum plane_id plane_id)
5486 {
5487 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
5488 struct skl_wm_params wm_params;
5489 int ret;
5490
5491 wm->is_planar = true;
5492
5493 /* uv plane watermarks must also be validated for NV12/Planar */
5494 ret = skl_compute_plane_wm_params(crtc_state, plane_state,
5495 &wm_params, 1);
5496 if (ret)
5497 return ret;
5498
5499 skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
5500
5501 return 0;
5502 }
5503
5504 static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
5505 const struct intel_plane_state *plane_state)
5506 {
5507 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
5508 enum plane_id plane_id = plane->id;
5509 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
5510 const struct drm_framebuffer *fb = plane_state->hw.fb;
5511 int ret;
5512
5513 memset(wm, 0, sizeof(*wm));
5514
5515 if (!intel_wm_plane_visible(crtc_state, plane_state))
5516 return 0;
5517
5518 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5519 plane_id, 0);
5520 if (ret)
5521 return ret;
5522
5523 if (fb->format->is_yuv && fb->format->num_planes > 1) {
5524 ret = skl_build_plane_wm_uv(crtc_state, plane_state,
5525 plane_id);
5526 if (ret)
5527 return ret;
5528 }
5529
5530 return 0;
5531 }
5532
5533 static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
5534 const struct intel_plane_state *plane_state)
5535 {
5536 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
5537 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5538 enum plane_id plane_id = plane->id;
5539 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
5540 int ret;
5541
5542 memset(wm, 0, sizeof(*wm));
5543
5544 /* Watermarks calculated in master */
5545 if (plane_state->planar_slave)
5546 return 0;
5547
5548 if (plane_state->planar_linked_plane) {
5549 const struct drm_framebuffer *fb = plane_state->hw.fb;
5550 enum plane_id y_plane_id = plane_state->planar_linked_plane->id;
5551
5552 drm_WARN_ON(&dev_priv->drm,
5553 !intel_wm_plane_visible(crtc_state, plane_state));
5554 drm_WARN_ON(&dev_priv->drm, !fb->format->is_yuv ||
5555 fb->format->num_planes == 1);
5556
5557 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5558 y_plane_id, 0);
5559 if (ret)
5560 return ret;
5561
5562 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5563 plane_id, 1);
5564 if (ret)
5565 return ret;
5566 } else if (intel_wm_plane_visible(crtc_state, plane_state)) {
5567 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5568 plane_id, 0);
5569 if (ret)
5570 return ret;
5571 }
5572
5573 return 0;
5574 }
5575
5576 static int skl_build_pipe_wm(struct intel_atomic_state *state,
5577 struct intel_crtc *crtc)
5578 {
5579 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5580 struct intel_crtc_state *crtc_state =
5581 intel_atomic_get_new_crtc_state(state, crtc);
5582 const struct intel_plane_state *plane_state;
5583 struct intel_plane *plane;
5584 int ret, i;
5585
5586 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5587 /*
5588 * FIXME should perhaps check {old,new}_plane_crtc->hw.crtc
5589 * instead but we don't populate that correctly for NV12 Y
5590 * planes so for now hack this.
5591 */
5592 if (plane->pipe != crtc->pipe)
5593 continue;
5594
5595 if (INTEL_GEN(dev_priv) >= 11)
5596 ret = icl_build_plane_wm(crtc_state, plane_state);
5597 else
5598 ret = skl_build_plane_wm(crtc_state, plane_state);
5599 if (ret)
5600 return ret;
5601 }
5602
5603 crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw;
5604
5605 return 0;
5606 }
5607
5608 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
5609 i915_reg_t reg,
5610 const struct skl_ddb_entry *entry)
5611 {
5612 if (entry->end)
5613 intel_de_write_fw(dev_priv, reg,
5614 (entry->end - 1) << 16 | entry->start);
5615 else
5616 intel_de_write_fw(dev_priv, reg, 0);
5617 }
5618
5619 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
5620 i915_reg_t reg,
5621 const struct skl_wm_level *level)
5622 {
5623 u32 val = 0;
5624
5625 if (level->plane_en)
5626 val |= PLANE_WM_EN;
5627 if (level->ignore_lines)
5628 val |= PLANE_WM_IGNORE_LINES;
5629 val |= level->plane_res_b;
5630 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
5631
5632 intel_de_write_fw(dev_priv, reg, val);
5633 }
5634
5635 void skl_write_plane_wm(struct intel_plane *plane,
5636 const struct intel_crtc_state *crtc_state)
5637 {
5638 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5639 int level, max_level = ilk_wm_max_level(dev_priv);
5640 enum plane_id plane_id = plane->id;
5641 enum pipe pipe = plane->pipe;
5642 const struct skl_plane_wm *wm =
5643 &crtc_state->wm.skl.optimal.planes[plane_id];
5644 const struct skl_ddb_entry *ddb_y =
5645 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5646 const struct skl_ddb_entry *ddb_uv =
5647 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
5648
5649 for (level = 0; level <= max_level; level++) {
5650 const struct skl_wm_level *wm_level;
5651
5652 wm_level = skl_plane_wm_level(crtc_state, plane_id, level);
5653
5654 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
5655 wm_level);
5656 }
5657 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
5658 &wm->trans_wm);
5659
5660 if (INTEL_GEN(dev_priv) >= 11) {
5661 skl_ddb_entry_write(dev_priv,
5662 PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5663 return;
5664 }
5665
5666 if (wm->is_planar)
5667 swap(ddb_y, ddb_uv);
5668
5669 skl_ddb_entry_write(dev_priv,
5670 PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5671 skl_ddb_entry_write(dev_priv,
5672 PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
5673 }
5674
5675 void skl_write_cursor_wm(struct intel_plane *plane,
5676 const struct intel_crtc_state *crtc_state)
5677 {
5678 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5679 int level, max_level = ilk_wm_max_level(dev_priv);
5680 enum plane_id plane_id = plane->id;
5681 enum pipe pipe = plane->pipe;
5682 const struct skl_plane_wm *wm =
5683 &crtc_state->wm.skl.optimal.planes[plane_id];
5684 const struct skl_ddb_entry *ddb =
5685 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5686
5687 for (level = 0; level <= max_level; level++) {
5688 const struct skl_wm_level *wm_level;
5689
5690 wm_level = skl_plane_wm_level(crtc_state, plane_id, level);
5691
5692 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
5693 wm_level);
5694 }
5695 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5696
5697 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
5698 }
5699
5700 bool skl_wm_level_equals(const struct skl_wm_level *l1,
5701 const struct skl_wm_level *l2)
5702 {
5703 return l1->plane_en == l2->plane_en &&
5704 l1->ignore_lines == l2->ignore_lines &&
5705 l1->plane_res_l == l2->plane_res_l &&
5706 l1->plane_res_b == l2->plane_res_b;
5707 }
5708
5709 static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
5710 const struct skl_plane_wm *wm1,
5711 const struct skl_plane_wm *wm2)
5712 {
5713 int level, max_level = ilk_wm_max_level(dev_priv);
5714
5715 for (level = 0; level <= max_level; level++) {
5716 /*
5717 * We don't check uv_wm as the hardware doesn't actually
5718 * use it. It only gets used for calculating the required
5719 * ddb allocation.
5720 */
5721 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]))
5722 return false;
5723 }
5724
5725 return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm);
5726 }
5727
5728 static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
5729 const struct skl_ddb_entry *b)
5730 {
5731 return a->start < b->end && b->start < a->end;
5732 }
5733
5734 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
5735 const struct skl_ddb_entry *entries,
5736 int num_entries, int ignore_idx)
5737 {
5738 int i;
5739
5740 for (i = 0; i < num_entries; i++) {
5741 if (i != ignore_idx &&
5742 skl_ddb_entries_overlap(ddb, &entries[i]))
5743 return true;
5744 }
5745
5746 return false;
5747 }
5748
5749 static int
5750 skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
5751 struct intel_crtc_state *new_crtc_state)
5752 {
5753 struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->uapi.state);
5754 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5755 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5756 struct intel_plane *plane;
5757
5758 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5759 struct intel_plane_state *plane_state;
5760 enum plane_id plane_id = plane->id;
5761
5762 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
5763 &new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
5764 skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
5765 &new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
5766 continue;
5767
5768 plane_state = intel_atomic_get_plane_state(state, plane);
5769 if (IS_ERR(plane_state))
5770 return PTR_ERR(plane_state);
5771
5772 new_crtc_state->update_planes |= BIT(plane_id);
5773 }
5774
5775 return 0;
5776 }
5777
5778 static int
5779 skl_compute_ddb(struct intel_atomic_state *state)
5780 {
5781 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5782 const struct intel_dbuf_state *old_dbuf_state;
5783 const struct intel_dbuf_state *new_dbuf_state;
5784 const struct intel_crtc_state *old_crtc_state;
5785 struct intel_crtc_state *new_crtc_state;
5786 struct intel_crtc *crtc;
5787 int ret, i;
5788
5789 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5790 new_crtc_state, i) {
5791 ret = skl_allocate_pipe_ddb(state, crtc);
5792 if (ret)
5793 return ret;
5794
5795 ret = skl_ddb_add_affected_planes(old_crtc_state,
5796 new_crtc_state);
5797 if (ret)
5798 return ret;
5799 }
5800
5801 old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
5802 new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
5803
5804 if (new_dbuf_state &&
5805 new_dbuf_state->enabled_slices != old_dbuf_state->enabled_slices)
5806 drm_dbg_kms(&dev_priv->drm,
5807 "Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n",
5808 old_dbuf_state->enabled_slices,
5809 new_dbuf_state->enabled_slices,
5810 INTEL_INFO(dev_priv)->num_supported_dbuf_slices);
5811
5812 return 0;
5813 }
5814
5815 static char enast(bool enable)
5816 {
5817 return enable ? '*' : ' ';
5818 }
5819
5820 static void
5821 skl_print_wm_changes(struct intel_atomic_state *state)
5822 {
5823 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5824 const struct intel_crtc_state *old_crtc_state;
5825 const struct intel_crtc_state *new_crtc_state;
5826 struct intel_plane *plane;
5827 struct intel_crtc *crtc;
5828 int i;
5829
5830 if (!drm_debug_enabled(DRM_UT_KMS))
5831 return;
5832
5833 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5834 new_crtc_state, i) {
5835 const struct skl_pipe_wm *old_pipe_wm, *new_pipe_wm;
5836
5837 old_pipe_wm = &old_crtc_state->wm.skl.optimal;
5838 new_pipe_wm = &new_crtc_state->wm.skl.optimal;
5839
5840 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5841 enum plane_id plane_id = plane->id;
5842 const struct skl_ddb_entry *old, *new;
5843
5844 old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
5845 new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
5846
5847 if (skl_ddb_entry_equal(old, new))
5848 continue;
5849
5850 drm_dbg_kms(&dev_priv->drm,
5851 "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
5852 plane->base.base.id, plane->base.name,
5853 old->start, old->end, new->start, new->end,
5854 skl_ddb_entry_size(old), skl_ddb_entry_size(new));
5855 }
5856
5857 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5858 enum plane_id plane_id = plane->id;
5859 const struct skl_plane_wm *old_wm, *new_wm;
5860
5861 old_wm = &old_pipe_wm->planes[plane_id];
5862 new_wm = &new_pipe_wm->planes[plane_id];
5863
5864 if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
5865 continue;
5866
5867 drm_dbg_kms(&dev_priv->drm,
5868 "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm"
5869 " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm\n",
5870 plane->base.base.id, plane->base.name,
5871 enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en),
5872 enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en),
5873 enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en),
5874 enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en),
5875 enast(old_wm->trans_wm.plane_en),
5876 enast(old_wm->sagv_wm0.plane_en),
5877 enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en),
5878 enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en),
5879 enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en),
5880 enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),
5881 enast(new_wm->trans_wm.plane_en),
5882 enast(new_wm->sagv_wm0.plane_en));
5883
5884 drm_dbg_kms(&dev_priv->drm,
5885 "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
5886 " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
5887 plane->base.base.id, plane->base.name,
5888 enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
5889 enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
5890 enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
5891 enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
5892 enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].plane_res_l,
5893 enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].plane_res_l,
5894 enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,
5895 enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
5896 enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
5897 enast(old_wm->sagv_wm0.ignore_lines), old_wm->sagv_wm0.plane_res_l,
5898
5899 enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
5900 enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
5901 enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
5902 enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
5903 enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].plane_res_l,
5904 enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l,
5905 enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,
5906 enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
5907 enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l,
5908 enast(new_wm->sagv_wm0.ignore_lines), new_wm->sagv_wm0.plane_res_l);
5909
5910 drm_dbg_kms(&dev_priv->drm,
5911 "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
5912 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
5913 plane->base.base.id, plane->base.name,
5914 old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
5915 old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
5916 old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
5917 old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
5918 old_wm->trans_wm.plane_res_b,
5919 old_wm->sagv_wm0.plane_res_b,
5920 new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
5921 new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
5922 new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
5923 new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
5924 new_wm->trans_wm.plane_res_b,
5925 new_wm->sagv_wm0.plane_res_b);
5926
5927 drm_dbg_kms(&dev_priv->drm,
5928 "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
5929 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
5930 plane->base.base.id, plane->base.name,
5931 old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
5932 old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
5933 old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
5934 old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
5935 old_wm->trans_wm.min_ddb_alloc,
5936 old_wm->sagv_wm0.min_ddb_alloc,
5937 new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
5938 new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
5939 new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
5940 new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
5941 new_wm->trans_wm.min_ddb_alloc,
5942 new_wm->sagv_wm0.min_ddb_alloc);
5943 }
5944 }
5945 }
5946
5947 static int intel_add_affected_pipes(struct intel_atomic_state *state,
5948 u8 pipe_mask)
5949 {
5950 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5951 struct intel_crtc *crtc;
5952
5953 for_each_intel_crtc(&dev_priv->drm, crtc) {
5954 struct intel_crtc_state *crtc_state;
5955
5956 if ((pipe_mask & BIT(crtc->pipe)) == 0)
5957 continue;
5958
5959 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5960 if (IS_ERR(crtc_state))
5961 return PTR_ERR(crtc_state);
5962 }
5963
5964 return 0;
5965 }
5966
5967 static int
5968 skl_ddb_add_affected_pipes(struct intel_atomic_state *state)
5969 {
5970 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5971 struct intel_crtc_state *crtc_state;
5972 struct intel_crtc *crtc;
5973 int i, ret;
5974
5975 if (dev_priv->wm.distrust_bios_wm) {
5976 /*
5977 * skl_ddb_get_pipe_allocation_limits() currently requires
5978 * all active pipes to be included in the state so that
5979 * it can redistribute the dbuf among them, and it really
5980 * wants to recompute things when distrust_bios_wm is set
5981 * so we add all the pipes to the state.
5982 */
5983 ret = intel_add_affected_pipes(state, ~0);
5984 if (ret)
5985 return ret;
5986 }
5987
5988 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5989 struct intel_dbuf_state *new_dbuf_state;
5990 const struct intel_dbuf_state *old_dbuf_state;
5991
5992 new_dbuf_state = intel_atomic_get_dbuf_state(state);
5993 if (IS_ERR(new_dbuf_state))
5994 return PTR_ERR(new_dbuf_state);
5995
5996 old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
5997
5998 new_dbuf_state->active_pipes =
5999 intel_calc_active_pipes(state, old_dbuf_state->active_pipes);
6000
6001 if (old_dbuf_state->active_pipes == new_dbuf_state->active_pipes)
6002 break;
6003
6004 ret = intel_atomic_lock_global_state(&new_dbuf_state->base);
6005 if (ret)
6006 return ret;
6007
6008 /*
6009 * skl_ddb_get_pipe_allocation_limits() currently requires
6010 * all active pipes to be included in the state so that
6011 * it can redistribute the dbuf among them.
6012 */
6013 ret = intel_add_affected_pipes(state,
6014 new_dbuf_state->active_pipes);
6015 if (ret)
6016 return ret;
6017
6018 break;
6019 }
6020
6021 return 0;
6022 }
6023
6024 /*
6025 * To make sure the cursor watermark registers are always consistent
6026 * with our computed state the following scenario needs special
6027 * treatment:
6028 *
6029 * 1. enable cursor
6030 * 2. move cursor entirely offscreen
6031 * 3. disable cursor
6032 *
6033 * Step 2. does call .disable_plane() but does not zero the watermarks
6034 * (since we consider an offscreen cursor still active for the purposes
6035 * of watermarks). Step 3. would not normally call .disable_plane()
6036 * because the actual plane visibility isn't changing, and we don't
6037 * deallocate the cursor ddb until the pipe gets disabled. So we must
6038 * force step 3. to call .disable_plane() to update the watermark
6039 * registers properly.
6040 *
6041 * Other planes do not suffer from this issues as their watermarks are
6042 * calculated based on the actual plane visibility. The only time this
6043 * can trigger for the other planes is during the initial readout as the
6044 * default value of the watermarks registers is not zero.
6045 */
6046 static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
6047 struct intel_crtc *crtc)
6048 {
6049 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6050 const struct intel_crtc_state *old_crtc_state =
6051 intel_atomic_get_old_crtc_state(state, crtc);
6052 struct intel_crtc_state *new_crtc_state =
6053 intel_atomic_get_new_crtc_state(state, crtc);
6054 struct intel_plane *plane;
6055
6056 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6057 struct intel_plane_state *plane_state;
6058 enum plane_id plane_id = plane->id;
6059
6060 /*
6061 * Force a full wm update for every plane on modeset.
6062 * Required because the reset value of the wm registers
6063 * is non-zero, whereas we want all disabled planes to
6064 * have zero watermarks. So if we turn off the relevant
6065 * power well the hardware state will go out of sync
6066 * with the software state.
6067 */
6068 if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi) &&
6069 skl_plane_wm_equals(dev_priv,
6070 &old_crtc_state->wm.skl.optimal.planes[plane_id],
6071 &new_crtc_state->wm.skl.optimal.planes[plane_id]))
6072 continue;
6073
6074 plane_state = intel_atomic_get_plane_state(state, plane);
6075 if (IS_ERR(plane_state))
6076 return PTR_ERR(plane_state);
6077
6078 new_crtc_state->update_planes |= BIT(plane_id);
6079 }
6080
6081 return 0;
6082 }
6083
6084 static int
6085 skl_compute_wm(struct intel_atomic_state *state)
6086 {
6087 struct intel_crtc *crtc;
6088 struct intel_crtc_state *new_crtc_state;
6089 int ret, i;
6090
6091 ret = skl_ddb_add_affected_pipes(state);
6092 if (ret)
6093 return ret;
6094
6095 /*
6096 * Calculate WM's for all pipes that are part of this transaction.
6097 * Note that skl_ddb_add_affected_pipes may have added more CRTC's that
6098 * weren't otherwise being modified if pipe allocations had to change.
6099 */
6100 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6101 ret = skl_build_pipe_wm(state, crtc);
6102 if (ret)
6103 return ret;
6104 }
6105
6106 ret = skl_compute_ddb(state);
6107 if (ret)
6108 return ret;
6109
6110 ret = intel_compute_sagv_mask(state);
6111 if (ret)
6112 return ret;
6113
6114 /*
6115 * skl_compute_ddb() will have adjusted the final watermarks
6116 * based on how much ddb is available. Now we can actually
6117 * check if the final watermarks changed.
6118 */
6119 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6120 ret = skl_wm_add_affected_planes(state, crtc);
6121 if (ret)
6122 return ret;
6123 }
6124
6125 skl_print_wm_changes(state);
6126
6127 return 0;
6128 }
6129
6130 static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
6131 struct intel_wm_config *config)
6132 {
6133 struct intel_crtc *crtc;
6134
6135 /* Compute the currently _active_ config */
6136 for_each_intel_crtc(&dev_priv->drm, crtc) {
6137 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
6138
6139 if (!wm->pipe_enabled)
6140 continue;
6141
6142 config->sprites_enabled |= wm->sprites_enabled;
6143 config->sprites_scaled |= wm->sprites_scaled;
6144 config->num_pipes_active++;
6145 }
6146 }
6147
6148 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
6149 {
6150 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
6151 struct ilk_wm_maximums max;
6152 struct intel_wm_config config = {};
6153 struct ilk_wm_values results = {};
6154 enum intel_ddb_partitioning partitioning;
6155
6156 ilk_compute_wm_config(dev_priv, &config);
6157
6158 ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_1_2, &max);
6159 ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2);
6160
6161 /* 5/6 split only in single pipe config on IVB+ */
6162 if (INTEL_GEN(dev_priv) >= 7 &&
6163 config.num_pipes_active == 1 && config.sprites_enabled) {
6164 ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max);
6165 ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6);
6166
6167 best_lp_wm = ilk_find_best_result(dev_priv, &lp_wm_1_2, &lp_wm_5_6);
6168 } else {
6169 best_lp_wm = &lp_wm_1_2;
6170 }
6171
6172 partitioning = (best_lp_wm == &lp_wm_1_2) ?
6173 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
6174
6175 ilk_compute_wm_results(dev_priv, best_lp_wm, partitioning, &results);
6176
6177 ilk_write_wm_values(dev_priv, &results);
6178 }
6179
6180 static void ilk_initial_watermarks(struct intel_atomic_state *state,
6181 struct intel_crtc *crtc)
6182 {
6183 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6184 const struct intel_crtc_state *crtc_state =
6185 intel_atomic_get_new_crtc_state(state, crtc);
6186
6187 mutex_lock(&dev_priv->wm.wm_mutex);
6188 crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
6189 ilk_program_watermarks(dev_priv);
6190 mutex_unlock(&dev_priv->wm.wm_mutex);
6191 }
6192
6193 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
6194 struct intel_crtc *crtc)
6195 {
6196 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6197 const struct intel_crtc_state *crtc_state =
6198 intel_atomic_get_new_crtc_state(state, crtc);
6199
6200 if (!crtc_state->wm.need_postvbl_update)
6201 return;
6202
6203 mutex_lock(&dev_priv->wm.wm_mutex);
6204 crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
6205 ilk_program_watermarks(dev_priv);
6206 mutex_unlock(&dev_priv->wm.wm_mutex);
6207 }
6208
6209 static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
6210 {
6211 level->plane_en = val & PLANE_WM_EN;
6212 level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
6213 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
6214 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
6215 PLANE_WM_LINES_MASK;
6216 }
6217
6218 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
6219 struct skl_pipe_wm *out)
6220 {
6221 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6222 enum pipe pipe = crtc->pipe;
6223 int level, max_level;
6224 enum plane_id plane_id;
6225 u32 val;
6226
6227 max_level = ilk_wm_max_level(dev_priv);
6228
6229 for_each_plane_id_on_crtc(crtc, plane_id) {
6230 struct skl_plane_wm *wm = &out->planes[plane_id];
6231
6232 for (level = 0; level <= max_level; level++) {
6233 if (plane_id != PLANE_CURSOR)
6234 val = I915_READ(PLANE_WM(pipe, plane_id, level));
6235 else
6236 val = I915_READ(CUR_WM(pipe, level));
6237
6238 skl_wm_level_from_reg_val(val, &wm->wm[level]);
6239 }
6240
6241 if (INTEL_GEN(dev_priv) >= 12)
6242 wm->sagv_wm0 = wm->wm[0];
6243
6244 if (plane_id != PLANE_CURSOR)
6245 val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
6246 else
6247 val = I915_READ(CUR_WM_TRANS(pipe));
6248
6249 skl_wm_level_from_reg_val(val, &wm->trans_wm);
6250 }
6251
6252 if (!crtc->active)
6253 return;
6254 }
6255
6256 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
6257 {
6258 struct intel_crtc *crtc;
6259 struct intel_crtc_state *crtc_state;
6260
6261 for_each_intel_crtc(&dev_priv->drm, crtc) {
6262 crtc_state = to_intel_crtc_state(crtc->base.state);
6263
6264 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
6265 crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;
6266 }
6267
6268 if (dev_priv->active_pipes) {
6269 /* Fully recompute DDB on first atomic commit */
6270 dev_priv->wm.distrust_bios_wm = true;
6271 }
6272 }
6273
6274 static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
6275 {
6276 struct drm_device *dev = crtc->base.dev;
6277 struct drm_i915_private *dev_priv = to_i915(dev);
6278 struct ilk_wm_values *hw = &dev_priv->wm.hw;
6279 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
6280 struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
6281 enum pipe pipe = crtc->pipe;
6282
6283 hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe));
6284
6285 memset(active, 0, sizeof(*active));
6286
6287 active->pipe_enabled = crtc->active;
6288
6289 if (active->pipe_enabled) {
6290 u32 tmp = hw->wm_pipe[pipe];
6291
6292 /*
6293 * For active pipes LP0 watermark is marked as
6294 * enabled, and LP1+ watermaks as disabled since
6295 * we can't really reverse compute them in case
6296 * multiple pipes are active.
6297 */
6298 active->wm[0].enable = true;
6299 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
6300 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
6301 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
6302 } else {
6303 int level, max_level = ilk_wm_max_level(dev_priv);
6304
6305 /*
6306 * For inactive pipes, all watermark levels
6307 * should be marked as enabled but zeroed,
6308 * which is what we'd compute them to.
6309 */
6310 for (level = 0; level <= max_level; level++)
6311 active->wm[level].enable = true;
6312 }
6313
6314 crtc->wm.active.ilk = *active;
6315 }
6316
6317 #define _FW_WM(value, plane) \
6318 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
6319 #define _FW_WM_VLV(value, plane) \
6320 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
6321
6322 static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
6323 struct g4x_wm_values *wm)
6324 {
6325 u32 tmp;
6326
6327 tmp = I915_READ(DSPFW1);
6328 wm->sr.plane = _FW_WM(tmp, SR);
6329 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
6330 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
6331 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
6332
6333 tmp = I915_READ(DSPFW2);
6334 wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
6335 wm->sr.fbc = _FW_WM(tmp, FBC_SR);
6336 wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
6337 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
6338 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
6339 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
6340
6341 tmp = I915_READ(DSPFW3);
6342 wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
6343 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
6344 wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
6345 wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
6346 }
6347
6348 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
6349 struct vlv_wm_values *wm)
6350 {
6351 enum pipe pipe;
6352 u32 tmp;
6353
6354 for_each_pipe(dev_priv, pipe) {
6355 tmp = I915_READ(VLV_DDL(pipe));
6356
6357 wm->ddl[pipe].plane[PLANE_PRIMARY] =
6358 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6359 wm->ddl[pipe].plane[PLANE_CURSOR] =
6360 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6361 wm->ddl[pipe].plane[PLANE_SPRITE0] =
6362 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6363 wm->ddl[pipe].plane[PLANE_SPRITE1] =
6364 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6365 }
6366
6367 tmp = I915_READ(DSPFW1);
6368 wm->sr.plane = _FW_WM(tmp, SR);
6369 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
6370 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
6371 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
6372
6373 tmp = I915_READ(DSPFW2);
6374 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
6375 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
6376 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
6377
6378 tmp = I915_READ(DSPFW3);
6379 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
6380
6381 if (IS_CHERRYVIEW(dev_priv)) {
6382 tmp = I915_READ(DSPFW7_CHV);
6383 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
6384 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6385
6386 tmp = I915_READ(DSPFW8_CHV);
6387 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
6388 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
6389
6390 tmp = I915_READ(DSPFW9_CHV);
6391 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
6392 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
6393
6394 tmp = I915_READ(DSPHOWM);
6395 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
6396 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
6397 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
6398 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
6399 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
6400 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
6401 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
6402 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
6403 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
6404 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6405 } else {
6406 tmp = I915_READ(DSPFW7);
6407 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
6408 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6409
6410 tmp = I915_READ(DSPHOWM);
6411 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
6412 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
6413 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
6414 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
6415 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
6416 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
6417 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6418 }
6419 }
6420
6421 #undef _FW_WM
6422 #undef _FW_WM_VLV
6423
6424 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
6425 {
6426 struct g4x_wm_values *wm = &dev_priv->wm.g4x;
6427 struct intel_crtc *crtc;
6428
6429 g4x_read_wm_values(dev_priv, wm);
6430
6431 wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
6432
6433 for_each_intel_crtc(&dev_priv->drm, crtc) {
6434 struct intel_crtc_state *crtc_state =
6435 to_intel_crtc_state(crtc->base.state);
6436 struct g4x_wm_state *active = &crtc->wm.active.g4x;
6437 struct g4x_pipe_wm *raw;
6438 enum pipe pipe = crtc->pipe;
6439 enum plane_id plane_id;
6440 int level, max_level;
6441
6442 active->cxsr = wm->cxsr;
6443 active->hpll_en = wm->hpll_en;
6444 active->fbc_en = wm->fbc_en;
6445
6446 active->sr = wm->sr;
6447 active->hpll = wm->hpll;
6448
6449 for_each_plane_id_on_crtc(crtc, plane_id) {
6450 active->wm.plane[plane_id] =
6451 wm->pipe[pipe].plane[plane_id];
6452 }
6453
6454 if (wm->cxsr && wm->hpll_en)
6455 max_level = G4X_WM_LEVEL_HPLL;
6456 else if (wm->cxsr)
6457 max_level = G4X_WM_LEVEL_SR;
6458 else
6459 max_level = G4X_WM_LEVEL_NORMAL;
6460
6461 level = G4X_WM_LEVEL_NORMAL;
6462 raw = &crtc_state->wm.g4x.raw[level];
6463 for_each_plane_id_on_crtc(crtc, plane_id)
6464 raw->plane[plane_id] = active->wm.plane[plane_id];
6465
6466 if (++level > max_level)
6467 goto out;
6468
6469 raw = &crtc_state->wm.g4x.raw[level];
6470 raw->plane[PLANE_PRIMARY] = active->sr.plane;
6471 raw->plane[PLANE_CURSOR] = active->sr.cursor;
6472 raw->plane[PLANE_SPRITE0] = 0;
6473 raw->fbc = active->sr.fbc;
6474
6475 if (++level > max_level)
6476 goto out;
6477
6478 raw = &crtc_state->wm.g4x.raw[level];
6479 raw->plane[PLANE_PRIMARY] = active->hpll.plane;
6480 raw->plane[PLANE_CURSOR] = active->hpll.cursor;
6481 raw->plane[PLANE_SPRITE0] = 0;
6482 raw->fbc = active->hpll.fbc;
6483
6484 out:
6485 for_each_plane_id_on_crtc(crtc, plane_id)
6486 g4x_raw_plane_wm_set(crtc_state, level,
6487 plane_id, USHRT_MAX);
6488 g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
6489
6490 crtc_state->wm.g4x.optimal = *active;
6491 crtc_state->wm.g4x.intermediate = *active;
6492
6493 drm_dbg_kms(&dev_priv->drm,
6494 "Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
6495 pipe_name(pipe),
6496 wm->pipe[pipe].plane[PLANE_PRIMARY],
6497 wm->pipe[pipe].plane[PLANE_CURSOR],
6498 wm->pipe[pipe].plane[PLANE_SPRITE0]);
6499 }
6500
6501 drm_dbg_kms(&dev_priv->drm,
6502 "Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
6503 wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
6504 drm_dbg_kms(&dev_priv->drm,
6505 "Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
6506 wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
6507 drm_dbg_kms(&dev_priv->drm, "Initial SR=%s HPLL=%s FBC=%s\n",
6508 yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
6509 }
6510
6511 void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
6512 {
6513 struct intel_plane *plane;
6514 struct intel_crtc *crtc;
6515
6516 mutex_lock(&dev_priv->wm.wm_mutex);
6517
6518 for_each_intel_plane(&dev_priv->drm, plane) {
6519 struct intel_crtc *crtc =
6520 intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6521 struct intel_crtc_state *crtc_state =
6522 to_intel_crtc_state(crtc->base.state);
6523 struct intel_plane_state *plane_state =
6524 to_intel_plane_state(plane->base.state);
6525 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
6526 enum plane_id plane_id = plane->id;
6527 int level;
6528
6529 if (plane_state->uapi.visible)
6530 continue;
6531
6532 for (level = 0; level < 3; level++) {
6533 struct g4x_pipe_wm *raw =
6534 &crtc_state->wm.g4x.raw[level];
6535
6536 raw->plane[plane_id] = 0;
6537 wm_state->wm.plane[plane_id] = 0;
6538 }
6539
6540 if (plane_id == PLANE_PRIMARY) {
6541 for (level = 0; level < 3; level++) {
6542 struct g4x_pipe_wm *raw =
6543 &crtc_state->wm.g4x.raw[level];
6544 raw->fbc = 0;
6545 }
6546
6547 wm_state->sr.fbc = 0;
6548 wm_state->hpll.fbc = 0;
6549 wm_state->fbc_en = false;
6550 }
6551 }
6552
6553 for_each_intel_crtc(&dev_priv->drm, crtc) {
6554 struct intel_crtc_state *crtc_state =
6555 to_intel_crtc_state(crtc->base.state);
6556
6557 crtc_state->wm.g4x.intermediate =
6558 crtc_state->wm.g4x.optimal;
6559 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
6560 }
6561
6562 g4x_program_watermarks(dev_priv);
6563
6564 mutex_unlock(&dev_priv->wm.wm_mutex);
6565 }
6566
6567 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
6568 {
6569 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
6570 struct intel_crtc *crtc;
6571 u32 val;
6572
6573 vlv_read_wm_values(dev_priv, wm);
6574
6575 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
6576 wm->level = VLV_WM_LEVEL_PM2;
6577
6578 if (IS_CHERRYVIEW(dev_priv)) {
6579 vlv_punit_get(dev_priv);
6580
6581 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
6582 if (val & DSP_MAXFIFO_PM5_ENABLE)
6583 wm->level = VLV_WM_LEVEL_PM5;
6584
6585 /*
6586 * If DDR DVFS is disabled in the BIOS, Punit
6587 * will never ack the request. So if that happens
6588 * assume we don't have to enable/disable DDR DVFS
6589 * dynamically. To test that just set the REQ_ACK
6590 * bit to poke the Punit, but don't change the
6591 * HIGH/LOW bits so that we don't actually change
6592 * the current state.
6593 */
6594 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
6595 val |= FORCE_DDR_FREQ_REQ_ACK;
6596 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
6597
6598 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
6599 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
6600 drm_dbg_kms(&dev_priv->drm,
6601 "Punit not acking DDR DVFS request, "
6602 "assuming DDR DVFS is disabled\n");
6603 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
6604 } else {
6605 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
6606 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
6607 wm->level = VLV_WM_LEVEL_DDR_DVFS;
6608 }
6609
6610 vlv_punit_put(dev_priv);
6611 }
6612
6613 for_each_intel_crtc(&dev_priv->drm, crtc) {
6614 struct intel_crtc_state *crtc_state =
6615 to_intel_crtc_state(crtc->base.state);
6616 struct vlv_wm_state *active = &crtc->wm.active.vlv;
6617 const struct vlv_fifo_state *fifo_state =
6618 &crtc_state->wm.vlv.fifo_state;
6619 enum pipe pipe = crtc->pipe;
6620 enum plane_id plane_id;
6621 int level;
6622
6623 vlv_get_fifo_size(crtc_state);
6624
6625 active->num_levels = wm->level + 1;
6626 active->cxsr = wm->cxsr;
6627
6628 for (level = 0; level < active->num_levels; level++) {
6629 struct g4x_pipe_wm *raw =
6630 &crtc_state->wm.vlv.raw[level];
6631
6632 active->sr[level].plane = wm->sr.plane;
6633 active->sr[level].cursor = wm->sr.cursor;
6634
6635 for_each_plane_id_on_crtc(crtc, plane_id) {
6636 active->wm[level].plane[plane_id] =
6637 wm->pipe[pipe].plane[plane_id];
6638
6639 raw->plane[plane_id] =
6640 vlv_invert_wm_value(active->wm[level].plane[plane_id],
6641 fifo_state->plane[plane_id]);
6642 }
6643 }
6644
6645 for_each_plane_id_on_crtc(crtc, plane_id)
6646 vlv_raw_plane_wm_set(crtc_state, level,
6647 plane_id, USHRT_MAX);
6648 vlv_invalidate_wms(crtc, active, level);
6649
6650 crtc_state->wm.vlv.optimal = *active;
6651 crtc_state->wm.vlv.intermediate = *active;
6652
6653 drm_dbg_kms(&dev_priv->drm,
6654 "Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
6655 pipe_name(pipe),
6656 wm->pipe[pipe].plane[PLANE_PRIMARY],
6657 wm->pipe[pipe].plane[PLANE_CURSOR],
6658 wm->pipe[pipe].plane[PLANE_SPRITE0],
6659 wm->pipe[pipe].plane[PLANE_SPRITE1]);
6660 }
6661
6662 drm_dbg_kms(&dev_priv->drm,
6663 "Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
6664 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
6665 }
6666
6667 void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
6668 {
6669 struct intel_plane *plane;
6670 struct intel_crtc *crtc;
6671
6672 mutex_lock(&dev_priv->wm.wm_mutex);
6673
6674 for_each_intel_plane(&dev_priv->drm, plane) {
6675 struct intel_crtc *crtc =
6676 intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6677 struct intel_crtc_state *crtc_state =
6678 to_intel_crtc_state(crtc->base.state);
6679 struct intel_plane_state *plane_state =
6680 to_intel_plane_state(plane->base.state);
6681 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
6682 const struct vlv_fifo_state *fifo_state =
6683 &crtc_state->wm.vlv.fifo_state;
6684 enum plane_id plane_id = plane->id;
6685 int level;
6686
6687 if (plane_state->uapi.visible)
6688 continue;
6689
6690 for (level = 0; level < wm_state->num_levels; level++) {
6691 struct g4x_pipe_wm *raw =
6692 &crtc_state->wm.vlv.raw[level];
6693
6694 raw->plane[plane_id] = 0;
6695
6696 wm_state->wm[level].plane[plane_id] =
6697 vlv_invert_wm_value(raw->plane[plane_id],
6698 fifo_state->plane[plane_id]);
6699 }
6700 }
6701
6702 for_each_intel_crtc(&dev_priv->drm, crtc) {
6703 struct intel_crtc_state *crtc_state =
6704 to_intel_crtc_state(crtc->base.state);
6705
6706 crtc_state->wm.vlv.intermediate =
6707 crtc_state->wm.vlv.optimal;
6708 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
6709 }
6710
6711 vlv_program_watermarks(dev_priv);
6712
6713 mutex_unlock(&dev_priv->wm.wm_mutex);
6714 }
6715
6716 /*
6717 * FIXME should probably kill this and improve
6718 * the real watermark readout/sanitation instead
6719 */
6720 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6721 {
6722 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6723 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6724 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6725
6726 /*
6727 * Don't touch WM1S_LP_EN here.
6728 * Doing so could cause underruns.
6729 */
6730 }
6731
6732 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
6733 {
6734 struct ilk_wm_values *hw = &dev_priv->wm.hw;
6735 struct intel_crtc *crtc;
6736
6737 ilk_init_lp_watermarks(dev_priv);
6738
6739 for_each_intel_crtc(&dev_priv->drm, crtc)
6740 ilk_pipe_wm_get_hw_state(crtc);
6741
6742 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
6743 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
6744 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
6745
6746 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
6747 if (INTEL_GEN(dev_priv) >= 7) {
6748 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
6749 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
6750 }
6751
6752 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6753 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
6754 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
6755 else if (IS_IVYBRIDGE(dev_priv))
6756 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
6757 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
6758
6759 hw->enable_fbc_wm =
6760 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
6761 }
6762
6763 /**
6764 * intel_update_watermarks - update FIFO watermark values based on current modes
6765 * @crtc: the #intel_crtc on which to compute the WM
6766 *
6767 * Calculate watermark values for the various WM regs based on current mode
6768 * and plane configuration.
6769 *
6770 * There are several cases to deal with here:
6771 * - normal (i.e. non-self-refresh)
6772 * - self-refresh (SR) mode
6773 * - lines are large relative to FIFO size (buffer can hold up to 2)
6774 * - lines are small relative to FIFO size (buffer can hold more than 2
6775 * lines), so need to account for TLB latency
6776 *
6777 * The normal calculation is:
6778 * watermark = dotclock * bytes per pixel * latency
6779 * where latency is platform & configuration dependent (we assume pessimal
6780 * values here).
6781 *
6782 * The SR calculation is:
6783 * watermark = (trunc(latency/line time)+1) * surface width *
6784 * bytes per pixel
6785 * where
6786 * line time = htotal / dotclock
6787 * surface width = hdisplay for normal plane and 64 for cursor
6788 * and latency is assumed to be high, as above.
6789 *
6790 * The final value programmed to the register should always be rounded up,
6791 * and include an extra 2 entries to account for clock crossings.
6792 *
6793 * We don't use the sprite, so we can ignore that. And on Crestline we have
6794 * to set the non-SR watermarks to 8.
6795 */
6796 void intel_update_watermarks(struct intel_crtc *crtc)
6797 {
6798 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6799
6800 if (dev_priv->display.update_wm)
6801 dev_priv->display.update_wm(crtc);
6802 }
6803
6804 void intel_enable_ipc(struct drm_i915_private *dev_priv)
6805 {
6806 u32 val;
6807
6808 if (!HAS_IPC(dev_priv))
6809 return;
6810
6811 val = I915_READ(DISP_ARB_CTL2);
6812
6813 if (dev_priv->ipc_enabled)
6814 val |= DISP_IPC_ENABLE;
6815 else
6816 val &= ~DISP_IPC_ENABLE;
6817
6818 I915_WRITE(DISP_ARB_CTL2, val);
6819 }
6820
6821 static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv)
6822 {
6823 /* Display WA #0477 WaDisableIPC: skl */
6824 if (IS_SKYLAKE(dev_priv))
6825 return false;
6826
6827 /* Display WA #1141: SKL:all KBL:all CFL */
6828 if (IS_KABYLAKE(dev_priv) ||
6829 IS_COFFEELAKE(dev_priv) ||
6830 IS_COMETLAKE(dev_priv))
6831 return dev_priv->dram_info.symmetric_memory;
6832
6833 return true;
6834 }
6835
6836 void intel_init_ipc(struct drm_i915_private *dev_priv)
6837 {
6838 if (!HAS_IPC(dev_priv))
6839 return;
6840
6841 dev_priv->ipc_enabled = intel_can_enable_ipc(dev_priv);
6842
6843 intel_enable_ipc(dev_priv);
6844 }
6845
6846 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
6847 {
6848 /*
6849 * On Ibex Peak and Cougar Point, we need to disable clock
6850 * gating for the panel power sequencer or it will fail to
6851 * start up when no ports are active.
6852 */
6853 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6854 }
6855
6856 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
6857 {
6858 enum pipe pipe;
6859
6860 for_each_pipe(dev_priv, pipe) {
6861 I915_WRITE(DSPCNTR(pipe),
6862 I915_READ(DSPCNTR(pipe)) |
6863 DISPPLANE_TRICKLE_FEED_DISABLE);
6864
6865 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6866 POSTING_READ(DSPSURF(pipe));
6867 }
6868 }
6869
6870 static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
6871 {
6872 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6873
6874 /*
6875 * Required for FBC
6876 * WaFbcDisableDpfcClockGating:ilk
6877 */
6878 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6879 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6880 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6881
6882 I915_WRITE(PCH_3DCGDIS0,
6883 MARIUNIT_CLOCK_GATE_DISABLE |
6884 SVSMUNIT_CLOCK_GATE_DISABLE);
6885 I915_WRITE(PCH_3DCGDIS1,
6886 VFMUNIT_CLOCK_GATE_DISABLE);
6887
6888 /*
6889 * According to the spec the following bits should be set in
6890 * order to enable memory self-refresh
6891 * The bit 22/21 of 0x42004
6892 * The bit 5 of 0x42020
6893 * The bit 15 of 0x45000
6894 */
6895 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6896 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6897 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6898 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6899 I915_WRITE(DISP_ARB_CTL,
6900 (I915_READ(DISP_ARB_CTL) |
6901 DISP_FBC_WM_DIS));
6902
6903 /*
6904 * Based on the document from hardware guys the following bits
6905 * should be set unconditionally in order to enable FBC.
6906 * The bit 22 of 0x42000
6907 * The bit 22 of 0x42004
6908 * The bit 7,8,9 of 0x42020.
6909 */
6910 if (IS_IRONLAKE_M(dev_priv)) {
6911 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6912 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6913 I915_READ(ILK_DISPLAY_CHICKEN1) |
6914 ILK_FBCQ_DIS);
6915 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6916 I915_READ(ILK_DISPLAY_CHICKEN2) |
6917 ILK_DPARB_GATE);
6918 }
6919
6920 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6921
6922 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6923 I915_READ(ILK_DISPLAY_CHICKEN2) |
6924 ILK_ELPIN_409_SELECT);
6925
6926 g4x_disable_trickle_feed(dev_priv);
6927
6928 ibx_init_clock_gating(dev_priv);
6929 }
6930
6931 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
6932 {
6933 enum pipe pipe;
6934 u32 val;
6935
6936 /*
6937 * On Ibex Peak and Cougar Point, we need to disable clock
6938 * gating for the panel power sequencer or it will fail to
6939 * start up when no ports are active.
6940 */
6941 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6942 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6943 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6944 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6945 DPLS_EDP_PPS_FIX_DIS);
6946 /* The below fixes the weird display corruption, a few pixels shifted
6947 * downward, on (only) LVDS of some HP laptops with IVY.
6948 */
6949 for_each_pipe(dev_priv, pipe) {
6950 val = I915_READ(TRANS_CHICKEN2(pipe));
6951 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6952 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6953 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6954 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6955 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6956 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6957 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6958 }
6959 /* WADP0ClockGatingDisable */
6960 for_each_pipe(dev_priv, pipe) {
6961 I915_WRITE(TRANS_CHICKEN1(pipe),
6962 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6963 }
6964 }
6965
6966 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
6967 {
6968 u32 tmp;
6969
6970 tmp = I915_READ(MCH_SSKPD);
6971 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6972 drm_dbg_kms(&dev_priv->drm,
6973 "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6974 tmp);
6975 }
6976
6977 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
6978 {
6979 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6980
6981 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6982
6983 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6984 I915_READ(ILK_DISPLAY_CHICKEN2) |
6985 ILK_ELPIN_409_SELECT);
6986
6987 I915_WRITE(GEN6_UCGCTL1,
6988 I915_READ(GEN6_UCGCTL1) |
6989 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6990 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6991
6992 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6993 * gating disable must be set. Failure to set it results in
6994 * flickering pixels due to Z write ordering failures after
6995 * some amount of runtime in the Mesa "fire" demo, and Unigine
6996 * Sanctuary and Tropics, and apparently anything else with
6997 * alpha test or pixel discard.
6998 *
6999 * According to the spec, bit 11 (RCCUNIT) must also be set,
7000 * but we didn't debug actual testcases to find it out.
7001 *
7002 * WaDisableRCCUnitClockGating:snb
7003 * WaDisableRCPBUnitClockGating:snb
7004 */
7005 I915_WRITE(GEN6_UCGCTL2,
7006 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7007 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7008
7009 /*
7010 * According to the spec the following bits should be
7011 * set in order to enable memory self-refresh and fbc:
7012 * The bit21 and bit22 of 0x42000
7013 * The bit21 and bit22 of 0x42004
7014 * The bit5 and bit7 of 0x42020
7015 * The bit14 of 0x70180
7016 * The bit14 of 0x71180
7017 *
7018 * WaFbcAsynchFlipDisableFbcQueue:snb
7019 */
7020 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7021 I915_READ(ILK_DISPLAY_CHICKEN1) |
7022 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7023 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7024 I915_READ(ILK_DISPLAY_CHICKEN2) |
7025 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7026 I915_WRITE(ILK_DSPCLK_GATE_D,
7027 I915_READ(ILK_DSPCLK_GATE_D) |
7028 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7029 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7030
7031 g4x_disable_trickle_feed(dev_priv);
7032
7033 cpt_init_clock_gating(dev_priv);
7034
7035 gen6_check_mch_setup(dev_priv);
7036 }
7037
7038 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7039 {
7040 /*
7041 * TODO: this bit should only be enabled when really needed, then
7042 * disabled when not needed anymore in order to save power.
7043 */
7044 if (HAS_PCH_LPT_LP(dev_priv))
7045 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7046 I915_READ(SOUTH_DSPCLK_GATE_D) |
7047 PCH_LP_PARTITION_LEVEL_DISABLE);
7048
7049 /* WADPOClockGatingDisable:hsw */
7050 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7051 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7052 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7053 }
7054
7055 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7056 {
7057 if (HAS_PCH_LPT_LP(dev_priv)) {
7058 u32 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7059
7060 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7061 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7062 }
7063 }
7064
7065 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7066 int general_prio_credits,
7067 int high_prio_credits)
7068 {
7069 u32 misccpctl;
7070 u32 val;
7071
7072 /* WaTempDisableDOPClkGating:bdw */
7073 misccpctl = I915_READ(GEN7_MISCCPCTL);
7074 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7075
7076 val = I915_READ(GEN8_L3SQCREG1);
7077 val &= ~L3_PRIO_CREDITS_MASK;
7078 val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
7079 val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
7080 I915_WRITE(GEN8_L3SQCREG1, val);
7081
7082 /*
7083 * Wait at least 100 clocks before re-enabling clock gating.
7084 * See the definition of L3SQCREG1 in BSpec.
7085 */
7086 POSTING_READ(GEN8_L3SQCREG1);
7087 udelay(1);
7088 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7089 }
7090
7091 static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
7092 {
7093 /* Wa_1409120013:icl,ehl */
7094 I915_WRITE(ILK_DPFC_CHICKEN,
7095 ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
7096
7097 /* This is not an Wa. Enable to reduce Sampler power */
7098 I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
7099 I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
7100
7101 /*Wa_14010594013:icl, ehl */
7102 intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
7103 0, CNL_DELAY_PMRSP);
7104 }
7105
7106 static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
7107 {
7108 /* Wa_1409120013:tgl */
7109 I915_WRITE(ILK_DPFC_CHICKEN,
7110 ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
7111
7112 /* Wa_1409825376:tgl (pre-prod)*/
7113 if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
7114 I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
7115 TGL_VRH_GATING_DIS);
7116
7117 /* Wa_14011059788:tgl */
7118 intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
7119 0, DFR_DISABLE);
7120 }
7121
7122 static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
7123 {
7124 /* Wa_1409836686:dg1[a0] */
7125 if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
7126 I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
7127 DPT_GATING_DIS);
7128 }
7129
7130 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
7131 {
7132 if (!HAS_PCH_CNP(dev_priv))
7133 return;
7134
7135 /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
7136 I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
7137 CNP_PWM_CGE_GATING_DISABLE);
7138 }
7139
7140 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
7141 {
7142 u32 val;
7143 cnp_init_clock_gating(dev_priv);
7144
7145 /* This is not an Wa. Enable for better image quality */
7146 I915_WRITE(_3D_CHICKEN3,
7147 _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
7148
7149 /* WaEnableChickenDCPR:cnl */
7150 I915_WRITE(GEN8_CHICKEN_DCPR_1,
7151 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
7152
7153 /*
7154 * WaFbcWakeMemOn:cnl
7155 * Display WA #0859: cnl
7156 */
7157 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
7158 DISP_FBC_MEMORY_WAKE);
7159
7160 val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE);
7161 /* ReadHitWriteOnlyDisable:cnl */
7162 val |= RCCUNIT_CLKGATE_DIS;
7163 I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
7164
7165 /* Wa_2201832410:cnl */
7166 val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
7167 val |= GWUNIT_CLKGATE_DIS;
7168 I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
7169
7170 /* WaDisableVFclkgate:cnl */
7171 /* WaVFUnitClockGatingDisable:cnl */
7172 val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
7173 val |= VFUNIT_CLKGATE_DIS;
7174 I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val);
7175 }
7176
7177 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
7178 {
7179 cnp_init_clock_gating(dev_priv);
7180 gen9_init_clock_gating(dev_priv);
7181
7182 /* WAC6entrylatency:cfl */
7183 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7184 FBC_LLC_FULLY_OPEN);
7185
7186 /*
7187 * WaFbcTurnOffFbcWatermark:cfl
7188 * Display WA #0562: cfl
7189 */
7190 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
7191 DISP_FBC_WM_DIS);
7192
7193 /*
7194 * WaFbcNukeOnHostModify:cfl
7195 * Display WA #0873: cfl
7196 */
7197 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7198 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7199 }
7200
7201 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
7202 {
7203 gen9_init_clock_gating(dev_priv);
7204
7205 /* WAC6entrylatency:kbl */
7206 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7207 FBC_LLC_FULLY_OPEN);
7208
7209 /* WaDisableSDEUnitClockGating:kbl */
7210 if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0))
7211 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7212 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7213
7214 /* WaDisableGamClockGating:kbl */
7215 if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0))
7216 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7217 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7218
7219 /*
7220 * WaFbcTurnOffFbcWatermark:kbl
7221 * Display WA #0562: kbl
7222 */
7223 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
7224 DISP_FBC_WM_DIS);
7225
7226 /*
7227 * WaFbcNukeOnHostModify:kbl
7228 * Display WA #0873: kbl
7229 */
7230 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7231 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7232 }
7233
7234 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
7235 {
7236 gen9_init_clock_gating(dev_priv);
7237
7238 /* WaDisableDopClockGating:skl */
7239 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) &
7240 ~GEN7_DOP_CLOCK_GATE_ENABLE);
7241
7242 /* WAC6entrylatency:skl */
7243 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7244 FBC_LLC_FULLY_OPEN);
7245
7246 /*
7247 * WaFbcTurnOffFbcWatermark:skl
7248 * Display WA #0562: skl
7249 */
7250 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
7251 DISP_FBC_WM_DIS);
7252
7253 /*
7254 * WaFbcNukeOnHostModify:skl
7255 * Display WA #0873: skl
7256 */
7257 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7258 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7259
7260 /*
7261 * WaFbcHighMemBwCorruptionAvoidance:skl
7262 * Display WA #0883: skl
7263 */
7264 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7265 ILK_DPFC_DISABLE_DUMMY0);
7266 }
7267
7268 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
7269 {
7270 enum pipe pipe;
7271
7272 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
7273 I915_WRITE(CHICKEN_PIPESL_1(PIPE_A),
7274 I915_READ(CHICKEN_PIPESL_1(PIPE_A)) |
7275 HSW_FBCQ_DIS);
7276
7277 /* WaSwitchSolVfFArbitrationPriority:bdw */
7278 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7279
7280 /* WaPsrDPAMaskVBlankInSRD:bdw */
7281 I915_WRITE(CHICKEN_PAR1_1,
7282 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7283
7284 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7285 for_each_pipe(dev_priv, pipe) {
7286 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7287 I915_READ(CHICKEN_PIPESL_1(pipe)) |
7288 BDW_DPRS_MASK_VBLANK_SRD);
7289 }
7290
7291 /* WaVSRefCountFullforceMissDisable:bdw */
7292 /* WaDSRefCountFullforceMissDisable:bdw */
7293 I915_WRITE(GEN7_FF_THREAD_MODE,
7294 I915_READ(GEN7_FF_THREAD_MODE) &
7295 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7296
7297 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7298 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7299
7300 /* WaDisableSDEUnitClockGating:bdw */
7301 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7302 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7303
7304 /* WaProgramL3SqcReg1Default:bdw */
7305 gen8_set_l3sqc_credits(dev_priv, 30, 2);
7306
7307 /* WaKVMNotificationOnConfigChange:bdw */
7308 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7309 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7310
7311 lpt_init_clock_gating(dev_priv);
7312
7313 /* WaDisableDopClockGating:bdw
7314 *
7315 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
7316 * clock gating.
7317 */
7318 I915_WRITE(GEN6_UCGCTL1,
7319 I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
7320 }
7321
7322 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
7323 {
7324 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
7325 I915_WRITE(CHICKEN_PIPESL_1(PIPE_A),
7326 I915_READ(CHICKEN_PIPESL_1(PIPE_A)) |
7327 HSW_FBCQ_DIS);
7328
7329 /* This is required by WaCatErrorRejectionIssue:hsw */
7330 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7331 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7332 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7333
7334 /* WaSwitchSolVfFArbitrationPriority:hsw */
7335 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7336
7337 lpt_init_clock_gating(dev_priv);
7338 }
7339
7340 static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
7341 {
7342 u32 snpcr;
7343
7344 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7345
7346 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
7347 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7348 I915_READ(ILK_DISPLAY_CHICKEN1) |
7349 ILK_FBCQ_DIS);
7350
7351 /* WaDisableBackToBackFlipFix:ivb */
7352 I915_WRITE(IVB_CHICKEN3,
7353 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7354 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7355
7356 if (IS_IVB_GT1(dev_priv))
7357 I915_WRITE(GEN7_ROW_CHICKEN2,
7358 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7359 else {
7360 /* must write both registers */
7361 I915_WRITE(GEN7_ROW_CHICKEN2,
7362 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7363 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7364 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7365 }
7366
7367 /*
7368 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7369 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7370 */
7371 I915_WRITE(GEN6_UCGCTL2,
7372 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7373
7374 /* This is required by WaCatErrorRejectionIssue:ivb */
7375 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7376 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7377 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7378
7379 g4x_disable_trickle_feed(dev_priv);
7380
7381 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7382 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7383 snpcr |= GEN6_MBC_SNPCR_MED;
7384 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7385
7386 if (!HAS_PCH_NOP(dev_priv))
7387 cpt_init_clock_gating(dev_priv);
7388
7389 gen6_check_mch_setup(dev_priv);
7390 }
7391
7392 static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
7393 {
7394 /* WaDisableBackToBackFlipFix:vlv */
7395 I915_WRITE(IVB_CHICKEN3,
7396 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7397 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7398
7399 /* WaDisableDopClockGating:vlv */
7400 I915_WRITE(GEN7_ROW_CHICKEN2,
7401 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7402
7403 /* This is required by WaCatErrorRejectionIssue:vlv */
7404 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7405 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7406 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7407
7408 /*
7409 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7410 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7411 */
7412 I915_WRITE(GEN6_UCGCTL2,
7413 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7414
7415 /* WaDisableL3Bank2xClockGate:vlv
7416 * Disabling L3 clock gating- MMIO 940c[25] = 1
7417 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7418 I915_WRITE(GEN7_UCGCTL4,
7419 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7420
7421 /*
7422 * WaDisableVLVClockGating_VBIIssue:vlv
7423 * Disable clock gating on th GCFG unit to prevent a delay
7424 * in the reporting of vblank events.
7425 */
7426 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7427 }
7428
7429 static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
7430 {
7431 /* WaVSRefCountFullforceMissDisable:chv */
7432 /* WaDSRefCountFullforceMissDisable:chv */
7433 I915_WRITE(GEN7_FF_THREAD_MODE,
7434 I915_READ(GEN7_FF_THREAD_MODE) &
7435 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7436
7437 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7438 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7439 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7440
7441 /* WaDisableCSUnitClockGating:chv */
7442 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7443 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7444
7445 /* WaDisableSDEUnitClockGating:chv */
7446 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7447 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7448
7449 /*
7450 * WaProgramL3SqcReg1Default:chv
7451 * See gfxspecs/Related Documents/Performance Guide/
7452 * LSQC Setting Recommendations.
7453 */
7454 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7455 }
7456
7457 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7458 {
7459 u32 dspclk_gate;
7460
7461 I915_WRITE(RENCLK_GATE_D1, 0);
7462 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7463 GS_UNIT_CLOCK_GATE_DISABLE |
7464 CL_UNIT_CLOCK_GATE_DISABLE);
7465 I915_WRITE(RAMCLK_GATE_D, 0);
7466 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7467 OVRUNIT_CLOCK_GATE_DISABLE |
7468 OVCUNIT_CLOCK_GATE_DISABLE;
7469 if (IS_GM45(dev_priv))
7470 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7471 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7472
7473 g4x_disable_trickle_feed(dev_priv);
7474 }
7475
7476 static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
7477 {
7478 struct intel_uncore *uncore = &dev_priv->uncore;
7479
7480 intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7481 intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
7482 intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
7483 intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
7484 intel_uncore_write16(uncore, DEUC, 0);
7485 intel_uncore_write(uncore,
7486 MI_ARB_STATE,
7487 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7488 }
7489
7490 static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
7491 {
7492 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7493 I965_RCC_CLOCK_GATE_DISABLE |
7494 I965_RCPB_CLOCK_GATE_DISABLE |
7495 I965_ISC_CLOCK_GATE_DISABLE |
7496 I965_FBC_CLOCK_GATE_DISABLE);
7497 I915_WRITE(RENCLK_GATE_D2, 0);
7498 I915_WRITE(MI_ARB_STATE,
7499 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7500 }
7501
7502 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7503 {
7504 u32 dstate = I915_READ(D_STATE);
7505
7506 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7507 DSTATE_DOT_CLOCK_GATING;
7508 I915_WRITE(D_STATE, dstate);
7509
7510 if (IS_PINEVIEW(dev_priv))
7511 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7512
7513 /* IIR "flip pending" means done if this bit is set */
7514 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7515
7516 /* interrupts should cause a wake up from C3 */
7517 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7518
7519 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7520 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7521
7522 I915_WRITE(MI_ARB_STATE,
7523 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7524 }
7525
7526 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7527 {
7528 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7529
7530 /* interrupts should cause a wake up from C3 */
7531 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7532 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7533
7534 I915_WRITE(MEM_MODE,
7535 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7536
7537 /*
7538 * Have FBC ignore 3D activity since we use software
7539 * render tracking, and otherwise a pure 3D workload
7540 * (even if it just renders a single frame and then does
7541 * abosultely nothing) would not allow FBC to recompress
7542 * until a 2D blit occurs.
7543 */
7544 I915_WRITE(SCPD0,
7545 _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
7546 }
7547
7548 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7549 {
7550 I915_WRITE(MEM_MODE,
7551 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7552 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7553 }
7554
7555 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7556 {
7557 dev_priv->display.init_clock_gating(dev_priv);
7558 }
7559
7560 void intel_suspend_hw(struct drm_i915_private *dev_priv)
7561 {
7562 if (HAS_PCH_LPT(dev_priv))
7563 lpt_suspend_hw(dev_priv);
7564 }
7565
7566 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7567 {
7568 drm_dbg_kms(&dev_priv->drm,
7569 "No clock gating settings or workarounds applied.\n");
7570 }
7571
7572 /**
7573 * intel_init_clock_gating_hooks - setup the clock gating hooks
7574 * @dev_priv: device private
7575 *
7576 * Setup the hooks that configure which clocks of a given platform can be
7577 * gated and also apply various GT and display specific workarounds for these
7578 * platforms. Note that some GT specific workarounds are applied separately
7579 * when GPU contexts or batchbuffers start their execution.
7580 */
7581 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7582 {
7583 if (IS_DG1(dev_priv))
7584 dev_priv->display.init_clock_gating = dg1_init_clock_gating;
7585 else if (IS_GEN(dev_priv, 12))
7586 dev_priv->display.init_clock_gating = tgl_init_clock_gating;
7587 else if (IS_GEN(dev_priv, 11))
7588 dev_priv->display.init_clock_gating = icl_init_clock_gating;
7589 else if (IS_CANNONLAKE(dev_priv))
7590 dev_priv->display.init_clock_gating = cnl_init_clock_gating;
7591 else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
7592 dev_priv->display.init_clock_gating = cfl_init_clock_gating;
7593 else if (IS_SKYLAKE(dev_priv))
7594 dev_priv->display.init_clock_gating = skl_init_clock_gating;
7595 else if (IS_KABYLAKE(dev_priv))
7596 dev_priv->display.init_clock_gating = kbl_init_clock_gating;
7597 else if (IS_BROXTON(dev_priv))
7598 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7599 else if (IS_GEMINILAKE(dev_priv))
7600 dev_priv->display.init_clock_gating = glk_init_clock_gating;
7601 else if (IS_BROADWELL(dev_priv))
7602 dev_priv->display.init_clock_gating = bdw_init_clock_gating;
7603 else if (IS_CHERRYVIEW(dev_priv))
7604 dev_priv->display.init_clock_gating = chv_init_clock_gating;
7605 else if (IS_HASWELL(dev_priv))
7606 dev_priv->display.init_clock_gating = hsw_init_clock_gating;
7607 else if (IS_IVYBRIDGE(dev_priv))
7608 dev_priv->display.init_clock_gating = ivb_init_clock_gating;
7609 else if (IS_VALLEYVIEW(dev_priv))
7610 dev_priv->display.init_clock_gating = vlv_init_clock_gating;
7611 else if (IS_GEN(dev_priv, 6))
7612 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7613 else if (IS_GEN(dev_priv, 5))
7614 dev_priv->display.init_clock_gating = ilk_init_clock_gating;
7615 else if (IS_G4X(dev_priv))
7616 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7617 else if (IS_I965GM(dev_priv))
7618 dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
7619 else if (IS_I965G(dev_priv))
7620 dev_priv->display.init_clock_gating = i965g_init_clock_gating;
7621 else if (IS_GEN(dev_priv, 3))
7622 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7623 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7624 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7625 else if (IS_GEN(dev_priv, 2))
7626 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7627 else {
7628 MISSING_CASE(INTEL_DEVID(dev_priv));
7629 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7630 }
7631 }
7632
7633 /* Set up chip specific power management-related functions */
7634 void intel_init_pm(struct drm_i915_private *dev_priv)
7635 {
7636 /* For cxsr */
7637 if (IS_PINEVIEW(dev_priv))
7638 pnv_get_mem_freq(dev_priv);
7639 else if (IS_GEN(dev_priv, 5))
7640 ilk_get_mem_freq(dev_priv);
7641
7642 if (intel_has_sagv(dev_priv))
7643 skl_setup_sagv_block_time(dev_priv);
7644
7645 /* For FIFO watermark updates */
7646 if (INTEL_GEN(dev_priv) >= 9) {
7647 skl_setup_wm_latency(dev_priv);
7648 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7649 } else if (HAS_PCH_SPLIT(dev_priv)) {
7650 ilk_setup_wm_latency(dev_priv);
7651
7652 if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] &&
7653 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7654 (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] &&
7655 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7656 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7657 dev_priv->display.compute_intermediate_wm =
7658 ilk_compute_intermediate_wm;
7659 dev_priv->display.initial_watermarks =
7660 ilk_initial_watermarks;
7661 dev_priv->display.optimize_watermarks =
7662 ilk_optimize_watermarks;
7663 } else {
7664 drm_dbg_kms(&dev_priv->drm,
7665 "Failed to read display plane latency. "
7666 "Disable CxSR\n");
7667 }
7668 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7669 vlv_setup_wm_latency(dev_priv);
7670 dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
7671 dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
7672 dev_priv->display.initial_watermarks = vlv_initial_watermarks;
7673 dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
7674 dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
7675 } else if (IS_G4X(dev_priv)) {
7676 g4x_setup_wm_latency(dev_priv);
7677 dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
7678 dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
7679 dev_priv->display.initial_watermarks = g4x_initial_watermarks;
7680 dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
7681 } else if (IS_PINEVIEW(dev_priv)) {
7682 if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
7683 dev_priv->is_ddr3,
7684 dev_priv->fsb_freq,
7685 dev_priv->mem_freq)) {
7686 drm_info(&dev_priv->drm,
7687 "failed to find known CxSR latency "
7688 "(found ddr%s fsb freq %d, mem freq %d), "
7689 "disabling CxSR\n",
7690 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7691 dev_priv->fsb_freq, dev_priv->mem_freq);
7692 /* Disable CxSR and never update its watermark again */
7693 intel_set_memory_cxsr(dev_priv, false);
7694 dev_priv->display.update_wm = NULL;
7695 } else
7696 dev_priv->display.update_wm = pnv_update_wm;
7697 } else if (IS_GEN(dev_priv, 4)) {
7698 dev_priv->display.update_wm = i965_update_wm;
7699 } else if (IS_GEN(dev_priv, 3)) {
7700 dev_priv->display.update_wm = i9xx_update_wm;
7701 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7702 } else if (IS_GEN(dev_priv, 2)) {
7703 if (INTEL_NUM_PIPES(dev_priv) == 1) {
7704 dev_priv->display.update_wm = i845_update_wm;
7705 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7706 } else {
7707 dev_priv->display.update_wm = i9xx_update_wm;
7708 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7709 }
7710 } else {
7711 drm_err(&dev_priv->drm,
7712 "unexpected fall-through in %s\n", __func__);
7713 }
7714 }
7715
7716 void intel_pm_setup(struct drm_i915_private *dev_priv)
7717 {
7718 dev_priv->runtime_pm.suspended = false;
7719 atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
7720 }
7721
7722 static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj)
7723 {
7724 struct intel_dbuf_state *dbuf_state;
7725
7726 dbuf_state = kmemdup(obj->state, sizeof(*dbuf_state), GFP_KERNEL);
7727 if (!dbuf_state)
7728 return NULL;
7729
7730 return &dbuf_state->base;
7731 }
7732
7733 static void intel_dbuf_destroy_state(struct intel_global_obj *obj,
7734 struct intel_global_state *state)
7735 {
7736 kfree(state);
7737 }
7738
7739 static const struct intel_global_state_funcs intel_dbuf_funcs = {
7740 .atomic_duplicate_state = intel_dbuf_duplicate_state,
7741 .atomic_destroy_state = intel_dbuf_destroy_state,
7742 };
7743
7744 struct intel_dbuf_state *
7745 intel_atomic_get_dbuf_state(struct intel_atomic_state *state)
7746 {
7747 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7748 struct intel_global_state *dbuf_state;
7749
7750 dbuf_state = intel_atomic_get_global_obj_state(state, &dev_priv->dbuf.obj);
7751 if (IS_ERR(dbuf_state))
7752 return ERR_CAST(dbuf_state);
7753
7754 return to_intel_dbuf_state(dbuf_state);
7755 }
7756
7757 int intel_dbuf_init(struct drm_i915_private *dev_priv)
7758 {
7759 struct intel_dbuf_state *dbuf_state;
7760
7761 dbuf_state = kzalloc(sizeof(*dbuf_state), GFP_KERNEL);
7762 if (!dbuf_state)
7763 return -ENOMEM;
7764
7765 intel_atomic_global_obj_init(dev_priv, &dev_priv->dbuf.obj,
7766 &dbuf_state->base, &intel_dbuf_funcs);
7767
7768 return 0;
7769 }
7770
7771 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
7772 {
7773 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7774 const struct intel_dbuf_state *new_dbuf_state =
7775 intel_atomic_get_new_dbuf_state(state);
7776 const struct intel_dbuf_state *old_dbuf_state =
7777 intel_atomic_get_old_dbuf_state(state);
7778
7779 if (!new_dbuf_state ||
7780 new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
7781 return;
7782
7783 WARN_ON(!new_dbuf_state->base.changed);
7784
7785 gen9_dbuf_slices_update(dev_priv,
7786 old_dbuf_state->enabled_slices |
7787 new_dbuf_state->enabled_slices);
7788 }
7789
7790 void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
7791 {
7792 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7793 const struct intel_dbuf_state *new_dbuf_state =
7794 intel_atomic_get_new_dbuf_state(state);
7795 const struct intel_dbuf_state *old_dbuf_state =
7796 intel_atomic_get_old_dbuf_state(state);
7797
7798 if (!new_dbuf_state ||
7799 new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
7800 return;
7801
7802 WARN_ON(!new_dbuf_state->base.changed);
7803
7804 gen9_dbuf_slices_update(dev_priv,
7805 new_dbuf_state->enabled_slices);
7806 }
Linux with added FPC-III support