1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2018-2020 Intel Corporation
9 #include <drm/drm_device.h>
11 #include "kmb_plane.h"
14 #define KMB_MAX_WIDTH 1920 /*Max width in pixels */
15 #define KMB_MAX_HEIGHT 1080 /*Max height in pixels */
16 #define KMB_MIN_WIDTH 1920 /*Max width in pixels */
17 #define KMB_MIN_HEIGHT 1080 /*Max height in pixels */
18 #define KMB_LCD_DEFAULT_CLK 200000000
19 #define KMB_SYS_CLK_MHZ 500
21 #define ICAM_MMIO 0x3b100000
22 #define ICAM_LCD_OFFSET 0x1080
23 #define ICAM_MMIO_SIZE 0x2000
32 struct kmb_drm_private
{
33 struct drm_device drm
;
34 struct kmb_dsi
*kmb_dsi
;
35 void __iomem
*lcd_mmio
;
36 struct kmb_clock kmb_clk
;
38 struct kmb_plane
*plane
;
39 struct drm_atomic_state
*state
;
43 struct layer_status plane_status
[KMB_MAX_PLANES
];
49 static inline struct kmb_drm_private
*to_kmb(const struct drm_device
*dev
)
51 return container_of(dev
, struct kmb_drm_private
, drm
);
54 static inline struct kmb_drm_private
*crtc_to_kmb_priv(const struct drm_crtc
*x
)
56 return container_of(x
, struct kmb_drm_private
, crtc
);
59 static inline void kmb_write_lcd(struct kmb_drm_private
*dev_p
,
60 unsigned int reg
, u32 value
)
62 writel(value
, (dev_p
->lcd_mmio
+ reg
));
65 static inline u32
kmb_read_lcd(struct kmb_drm_private
*dev_p
, unsigned int reg
)
67 return readl(dev_p
->lcd_mmio
+ reg
);
70 static inline void kmb_set_bitmask_lcd(struct kmb_drm_private
*dev_p
,
71 unsigned int reg
, u32 mask
)
73 u32 reg_val
= kmb_read_lcd(dev_p
, reg
);
75 kmb_write_lcd(dev_p
, reg
, (reg_val
| mask
));
78 static inline void kmb_clr_bitmask_lcd(struct kmb_drm_private
*dev_p
,
79 unsigned int reg
, u32 mask
)
81 u32 reg_val
= kmb_read_lcd(dev_p
, reg
);
83 kmb_write_lcd(dev_p
, reg
, (reg_val
& (~mask
)));
86 int kmb_setup_crtc(struct drm_device
*dev
);
87 void kmb_set_scanout(struct kmb_drm_private
*lcd
);
88 #endif /* __KMB_DRV_H__ */