drivers/gpu/drm/kmb/kmb_plane.h

   1 /* SPDX-License-Identifier: GPL-2.0-only
   2  *
   3  * Copyright © 2018-2020 Intel Corporation
   4  */
   5
   6 #ifndef __KMB_PLANE_H__
   7 #define __KMB_PLANE_H__
   8
   9 #include <drm/drm_fourcc.h>
  10 #include <drm/drm_plane.h>
  11
  12 #define LCD_INT_VL0_ERR ((LAYER0_DMA_FIFO_UNDERFLOW) | \
  13                         (LAYER0_DMA_FIFO_OVERFLOW) | \
  14                         (LAYER0_DMA_CB_FIFO_OVERFLOW) | \
  15                         (LAYER0_DMA_CB_FIFO_UNDERFLOW) | \
  16                         (LAYER0_DMA_CR_FIFO_OVERFLOW) | \
  17                         (LAYER0_DMA_CR_FIFO_UNDERFLOW))
  18
  19 #define LCD_INT_VL1_ERR ((LAYER1_DMA_FIFO_UNDERFLOW) | \
  20                         (LAYER1_DMA_FIFO_OVERFLOW) | \
  21                         (LAYER1_DMA_CB_FIFO_OVERFLOW) | \
  22                         (LAYER1_DMA_CB_FIFO_UNDERFLOW) | \
  23                         (LAYER1_DMA_CR_FIFO_OVERFLOW) | \
  24                         (LAYER1_DMA_CR_FIFO_UNDERFLOW))
  25
  26 #define LCD_INT_GL0_ERR (LAYER2_DMA_FIFO_OVERFLOW | LAYER2_DMA_FIFO_UNDERFLOW)
  27 #define LCD_INT_GL1_ERR (LAYER3_DMA_FIFO_OVERFLOW | LAYER3_DMA_FIFO_UNDERFLOW)
  28 #define LCD_INT_VL0 (LAYER0_DMA_DONE | LAYER0_DMA_IDLE | LCD_INT_VL0_ERR)
  29 #define LCD_INT_VL1 (LAYER1_DMA_DONE | LAYER1_DMA_IDLE | LCD_INT_VL1_ERR)
  30 #define LCD_INT_GL0 (LAYER2_DMA_DONE | LAYER2_DMA_IDLE | LCD_INT_GL0_ERR)
  31 #define LCD_INT_GL1 (LAYER3_DMA_DONE | LAYER3_DMA_IDLE | LCD_INT_GL1_ERR)
  32 #define LCD_INT_DMA_ERR (LCD_INT_VL0_ERR | LCD_INT_VL1_ERR \
  33                 | LCD_INT_GL0_ERR | LCD_INT_GL1_ERR)
  34
  35 #define POSSIBLE_CRTCS 1
  36 #define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane)
  37
  38 enum layer_id {
  39         LAYER_0,
  40         LAYER_1,
  41         LAYER_2,
  42         LAYER_3,
  43         /* KMB_MAX_PLANES */
  44 };
  45
  46 #define KMB_MAX_PLANES 1
  47
  48 enum sub_plane_id {
  49         Y_PLANE,
  50         U_PLANE,
  51         V_PLANE,
  52         MAX_SUB_PLANES,
  53 };
  54
  55 struct kmb_plane {
  56         struct drm_plane base_plane;
  57         unsigned char id;
  58 };
  59
  60 struct layer_status {
  61         bool disable;
  62         u32 ctrl;
  63 };
  64
  65 struct kmb_plane *kmb_plane_init(struct drm_device *drm);
  66 void kmb_plane_destroy(struct drm_plane *plane);
  67 #endif /* __KMB_PLANE_H__ */