drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #ifndef _DPU_HW_PINGPONG_H
   6 #define _DPU_HW_PINGPONG_H
   7
   8 #include "dpu_hw_catalog.h"
   9 #include "dpu_hw_mdss.h"
  10 #include "dpu_hw_util.h"
  11 #include "dpu_hw_blk.h"
  12
  13 #define DITHER_MATRIX_SZ 16
  14
  15 struct dpu_hw_pingpong;
  16
  17 struct dpu_hw_tear_check {
  18         /*
  19          * This is ratio of MDP VSYNC clk freq(Hz) to
  20          * refresh rate divided by no of lines
  21          */
  22         u32 vsync_count;
  23         u32 sync_cfg_height;
  24         u32 vsync_init_val;
  25         u32 sync_threshold_start;
  26         u32 sync_threshold_continue;
  27         u32 start_pos;
  28         u32 rd_ptr_irq;
  29         u8 hw_vsync_mode;
  30 };
  31
  32 struct dpu_hw_pp_vsync_info {
  33         u32 rd_ptr_init_val;    /* value of rd pointer at vsync edge */
  34         u32 rd_ptr_frame_count; /* num frames sent since enabling interface */
  35         u32 rd_ptr_line_count;  /* current line on panel (rd ptr) */
  36         u32 wr_ptr_line_count;  /* current line within pp fifo (wr ptr) */
  37 };
  38
  39 /**
  40  * struct dpu_hw_dither_cfg - dither feature structure
  41  * @flags: for customizing operations
  42  * @temporal_en: temperal dither enable
  43  * @c0_bitdepth: c0 component bit depth
  44  * @c1_bitdepth: c1 component bit depth
  45  * @c2_bitdepth: c2 component bit depth
  46  * @c3_bitdepth: c2 component bit depth
  47  * @matrix: dither strength matrix
  48  */
  49 struct dpu_hw_dither_cfg {
  50         u64 flags;
  51         u32 temporal_en;
  52         u32 c0_bitdepth;
  53         u32 c1_bitdepth;
  54         u32 c2_bitdepth;
  55         u32 c3_bitdepth;
  56         u32 matrix[DITHER_MATRIX_SZ];
  57 };
  58
  59 /**
  60  *
  61  * struct dpu_hw_pingpong_ops : Interface to the pingpong Hw driver functions
  62  *  Assumption is these functions will be called after clocks are enabled
  63  *  @setup_tearcheck : program tear check values
  64  *  @enable_tearcheck : enables tear check
  65  *  @get_vsync_info : retries timing info of the panel
  66  *  @setup_dither : function to program the dither hw block
  67  *  @get_line_count: obtain current vertical line counter
  68  */
  69 struct dpu_hw_pingpong_ops {
  70         /**
  71          * enables vysnc generation and sets up init value of
  72          * read pointer and programs the tear check cofiguration
  73          */
  74         int (*setup_tearcheck)(struct dpu_hw_pingpong *pp,
  75                         struct dpu_hw_tear_check *cfg);
  76
  77         /**
  78          * enables tear check block
  79          */
  80         int (*enable_tearcheck)(struct dpu_hw_pingpong *pp,
  81                         bool enable);
  82
  83         /**
  84          * read, modify, write to either set or clear listening to external TE
  85          * @Return: 1 if TE was originally connected, 0 if not, or -ERROR
  86          */
  87         int (*connect_external_te)(struct dpu_hw_pingpong *pp,
  88                         bool enable_external_te);
  89
  90         /**
  91          * provides the programmed and current
  92          * line_count
  93          */
  94         int (*get_vsync_info)(struct dpu_hw_pingpong *pp,
  95                         struct dpu_hw_pp_vsync_info  *info);
  96
  97         /**
  98          * poll until write pointer transmission starts
  99          * @Return: 0 on success, -ETIMEDOUT on timeout
 100          */
 101         int (*poll_timeout_wr_ptr)(struct dpu_hw_pingpong *pp, u32 timeout_us);
 102
 103         /**
 104          * Obtain current vertical line counter
 105          */
 106         u32 (*get_line_count)(struct dpu_hw_pingpong *pp);
 107
 108         /**
 109          * Setup dither matix for pingpong block
 110          */
 111         void (*setup_dither)(struct dpu_hw_pingpong *pp,
 112                         struct dpu_hw_dither_cfg *cfg);
 113 };
 114
 115 struct dpu_hw_pingpong {
 116         struct dpu_hw_blk base;
 117         struct dpu_hw_blk_reg_map hw;
 118
 119         /* pingpong */
 120         enum dpu_pingpong idx;
 121         const struct dpu_pingpong_cfg *caps;
 122         struct dpu_hw_blk *merge_3d;
 123
 124         /* ops */
 125         struct dpu_hw_pingpong_ops ops;
 126 };
 127
 128 /**
 129  * to_dpu_hw_pingpong - convert base object dpu_hw_base to container
 130  * @hw: Pointer to base hardware block
 131  * return: Pointer to hardware block container
 132  */
 133 static inline struct dpu_hw_pingpong *to_dpu_hw_pingpong(struct dpu_hw_blk *hw)
 134 {
 135         return container_of(hw, struct dpu_hw_pingpong, base);
 136 }
 137
 138 /**
 139  * dpu_hw_pingpong_init - initializes the pingpong driver for the passed
 140  *      pingpong idx.
 141  * @idx:  Pingpong index for which driver object is required
 142  * @addr: Mapped register io address of MDP
 143  * @m:    Pointer to mdss catalog data
 144  * Returns: Error code or allocated dpu_hw_pingpong context
 145  */
 146 struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
 147                 void __iomem *addr,
 148                 const struct dpu_mdss_cfg *m);
 149
 150 /**
 151  * dpu_hw_pingpong_destroy - destroys pingpong driver context
 152  *      should be called to free the context
 153  * @pp:   Pointer to PP driver context returned by dpu_hw_pingpong_init
 154  */
 155 void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp);
 156
 157 #endif /*_DPU_HW_PINGPONG_H */