Merge tag 'io_uring-5.11-2021-01-16' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / gpu / drm / msm / dsi / pll / dsi_pll.h
blob3405982a092c4653b44b083a7481b1109f2ab9a6
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
4 */
6 #ifndef __DSI_PLL_H__
7 #define __DSI_PLL_H__
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
12 #include "dsi.h"
14 #define NUM_DSI_CLOCKS_MAX 6
15 #define MAX_DSI_PLL_EN_SEQS 10
17 struct msm_dsi_pll {
18 enum msm_dsi_phy_type type;
20 struct clk_hw clk_hw;
21 bool pll_on;
22 bool state_saved;
24 unsigned long min_rate;
25 unsigned long max_rate;
26 u32 en_seq_cnt;
28 int (*enable_seqs[MAX_DSI_PLL_EN_SEQS])(struct msm_dsi_pll *pll);
29 void (*disable_seq)(struct msm_dsi_pll *pll);
30 int (*get_provider)(struct msm_dsi_pll *pll,
31 struct clk **byte_clk_provider,
32 struct clk **pixel_clk_provider);
33 void (*destroy)(struct msm_dsi_pll *pll);
34 void (*save_state)(struct msm_dsi_pll *pll);
35 int (*restore_state)(struct msm_dsi_pll *pll);
36 int (*set_usecase)(struct msm_dsi_pll *pll,
37 enum msm_dsi_phy_usecase uc);
40 #define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)
42 static inline void pll_write(void __iomem *reg, u32 data)
44 msm_writel(data, reg);
47 static inline u32 pll_read(const void __iomem *reg)
49 return msm_readl(reg);
52 static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us)
54 pll_write(reg, data);
55 udelay(delay_us);
58 static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns)
60 pll_write((reg), data);
61 ndelay(delay_ns);
65 * DSI PLL Helper functions
68 /* clock callbacks */
69 long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
70 unsigned long rate, unsigned long *parent_rate);
71 int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
72 void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
73 /* misc */
74 void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
75 struct clk **clks, u32 num_clks);
78 * Initialization for Each PLL Type
80 #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
81 struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
82 enum msm_dsi_phy_type type, int id);
83 #else
84 static inline struct msm_dsi_pll *msm_dsi_pll_28nm_init(
85 struct platform_device *pdev, enum msm_dsi_phy_type type, int id)
87 return ERR_PTR(-ENODEV);
89 #endif
90 #ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY
91 struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
92 int id);
93 #else
94 static inline struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(
95 struct platform_device *pdev, int id)
97 return ERR_PTR(-ENODEV);
99 #endif
101 #ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
102 struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id);
103 #else
104 static inline struct msm_dsi_pll *
105 msm_dsi_pll_14nm_init(struct platform_device *pdev, int id)
107 return ERR_PTR(-ENODEV);
109 #endif
110 #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
111 struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id);
112 #else
113 static inline struct msm_dsi_pll *
114 msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
116 return ERR_PTR(-ENODEV);
118 #endif
119 #ifdef CONFIG_DRM_MSM_DSI_7NM_PHY
120 struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id);
121 #else
122 static inline struct msm_dsi_pll *
123 msm_dsi_pll_7nm_init(struct platform_device *pdev, int id)
125 return ERR_PTR(-ENODEV);
127 #endif
129 #endif /* __DSI_PLL_H__ */