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Merge tag 'io_uring-5.11-2021-01-16' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / gpu / drm / msm / dsi / pll / dsi_pll_14nm.c
blobf847376d501e7c20e87c5c2607f7b73bbc56d3aa
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8
9 #include "dsi_pll.h"
10 #include "dsi.xml.h"
11
12 /*
13 * DSI PLL 14nm - clock diagram (eg: DSI0):
14 *
15 * dsi0n1_postdiv_clk
16 * |
17 * |
18 * +----+ | +----+
19 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
20 * +----+ | +----+
21 * | dsi0n1_postdivby2_clk
22 * | +----+ |
23 * o---| /2 |--o--|\
24 * | +----+ | \ +----+
25 * | | |--| n2 |-- dsi0pll
26 * o--------------| / +----+
27 * |/
28 */
29
30 #define POLL_MAX_READS 15
31 #define POLL_TIMEOUT_US 1000
32
33 #define NUM_PROVIDED_CLKS 2
34
35 #define VCO_REF_CLK_RATE 19200000
36 #define VCO_MIN_RATE 1300000000UL
37 #define VCO_MAX_RATE 2600000000UL
38
39 #define DSI_BYTE_PLL_CLK 0
40 #define DSI_PIXEL_PLL_CLK 1
41
42 #define DSI_PLL_DEFAULT_VCO_POSTDIV 1
43
44 struct dsi_pll_input {
45 u32 fref; /* reference clk */
46 u32 fdata; /* bit clock rate */
47 u32 dsiclk_sel; /* Mux configuration (see diagram) */
48 u32 ssc_en; /* SSC enable/disable */
49 u32 ldo_en;
50
51 /* fixed params */
52 u32 refclk_dbler_en;
53 u32 vco_measure_time;
54 u32 kvco_measure_time;
55 u32 bandgap_timer;
56 u32 pll_wakeup_timer;
57 u32 plllock_cnt;
58 u32 plllock_rng;
59 u32 ssc_center;
60 u32 ssc_adj_period;
61 u32 ssc_spread;
62 u32 ssc_freq;
63 u32 pll_ie_trim;
64 u32 pll_ip_trim;
65 u32 pll_iptat_trim;
66 u32 pll_cpcset_cur;
67 u32 pll_cpmset_cur;
68
69 u32 pll_icpmset;
70 u32 pll_icpcset;
71
72 u32 pll_icpmset_p;
73 u32 pll_icpmset_m;
74
75 u32 pll_icpcset_p;
76 u32 pll_icpcset_m;
77
78 u32 pll_lpf_res1;
79 u32 pll_lpf_cap1;
80 u32 pll_lpf_cap2;
81 u32 pll_c3ctrl;
82 u32 pll_r3ctrl;
83 };
84
85 struct dsi_pll_output {
86 u32 pll_txclk_en;
87 u32 dec_start;
88 u32 div_frac_start;
89 u32 ssc_period;
90 u32 ssc_step_size;
91 u32 plllock_cmp;
92 u32 pll_vco_div_ref;
93 u32 pll_vco_count;
94 u32 pll_kvco_div_ref;
95 u32 pll_kvco_count;
96 u32 pll_misc1;
97 u32 pll_lpf2_postdiv;
98 u32 pll_resetsm_cntrl;
99 u32 pll_resetsm_cntrl2;
100 u32 pll_resetsm_cntrl5;
101 u32 pll_kvco_code;
102
103 u32 cmn_clk_cfg0;
104 u32 cmn_clk_cfg1;
105 u32 cmn_ldo_cntrl;
106
107 u32 pll_postdiv;
108 u32 fcvo;
109 };
110
111 struct pll_14nm_cached_state {
112 unsigned long vco_rate;
113 u8 n2postdiv;
114 u8 n1postdiv;
115 };
116
117 struct dsi_pll_14nm {
118 struct msm_dsi_pll base;
119
120 int id;
121 struct platform_device *pdev;
122
123 void __iomem *phy_cmn_mmio;
124 void __iomem *mmio;
125
126 int vco_delay;
127
128 struct dsi_pll_input in;
129 struct dsi_pll_output out;
130
131 /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
132 spinlock_t postdiv_lock;
133
134 u64 vco_current_rate;
135 u64 vco_ref_clk_rate;
136
137 /* private clocks: */
138 struct clk_hw *hws[NUM_DSI_CLOCKS_MAX];
139 u32 num_hws;
140
141 /* clock-provider: */
142 struct clk_hw_onecell_data *hw_data;
143
144 struct pll_14nm_cached_state cached_state;
145
146 enum msm_dsi_phy_usecase uc;
147 struct dsi_pll_14nm *slave;
148 };
149
150 #define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, base)
151
152 /*
153 * Private struct for N1/N2 post-divider clocks. These clocks are similar to
154 * the generic clk_divider class of clocks. The only difference is that it
155 * also sets the slave DSI PLL's post-dividers if in Dual DSI mode
156 */
157 struct dsi_pll_14nm_postdiv {
158 struct clk_hw hw;
159
160 /* divider params */
161 u8 shift;
162 u8 width;
163 u8 flags; /* same flags as used by clk_divider struct */
164
165 struct dsi_pll_14nm *pll;
166 };
167
168 #define to_pll_14nm_postdiv(_hw) container_of(_hw, struct dsi_pll_14nm_postdiv, hw)
169
170 /*
171 * Global list of private DSI PLL struct pointers. We need this for Dual DSI
172 * mode, where the master PLL's clk_ops needs access the slave's private data
173 */
174 static struct dsi_pll_14nm *pll_14nm_list[DSI_MAX];
175
176 static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
177 u32 nb_tries, u32 timeout_us)
178 {
179 bool pll_locked = false;
180 void __iomem *base = pll_14nm->mmio;
181 u32 tries, val;
182
183 tries = nb_tries;
184 while (tries--) {
185 val = pll_read(base +
186 REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
187 pll_locked = !!(val & BIT(5));
188
189 if (pll_locked)
190 break;
191
192 udelay(timeout_us);
193 }
194
195 if (!pll_locked) {
196 tries = nb_tries;
197 while (tries--) {
198 val = pll_read(base +
199 REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
200 pll_locked = !!(val & BIT(0));
201
202 if (pll_locked)
203 break;
204
205 udelay(timeout_us);
206 }
207 }
208
209 DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* ");
210
211 return pll_locked;
212 }
213
214 static void dsi_pll_14nm_input_init(struct dsi_pll_14nm *pll)
215 {
216 pll->in.fref = pll->vco_ref_clk_rate;
217 pll->in.fdata = 0;
218 pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */
219 pll->in.ldo_en = 0; /* disabled for now */
220
221 /* fixed input */
222 pll->in.refclk_dbler_en = 0;
223 pll->in.vco_measure_time = 5;
224 pll->in.kvco_measure_time = 5;
225 pll->in.bandgap_timer = 4;
226 pll->in.pll_wakeup_timer = 5;
227 pll->in.plllock_cnt = 1;
228 pll->in.plllock_rng = 0;
229
230 /*
231 * SSC is enabled by default. We might need DT props for configuring
232 * some SSC params like PPM and center/down spread etc.
233 */
234 pll->in.ssc_en = 1;
235 pll->in.ssc_center = 0; /* down spread by default */
236 pll->in.ssc_spread = 5; /* PPM / 1000 */
237 pll->in.ssc_freq = 31500; /* default recommended */
238 pll->in.ssc_adj_period = 37;
239
240 pll->in.pll_ie_trim = 4;
241 pll->in.pll_ip_trim = 4;
242 pll->in.pll_cpcset_cur = 1;
243 pll->in.pll_cpmset_cur = 1;
244 pll->in.pll_icpmset = 4;
245 pll->in.pll_icpcset = 4;
246 pll->in.pll_icpmset_p = 0;
247 pll->in.pll_icpmset_m = 0;
248 pll->in.pll_icpcset_p = 0;
249 pll->in.pll_icpcset_m = 0;
250 pll->in.pll_lpf_res1 = 3;
251 pll->in.pll_lpf_cap1 = 11;
252 pll->in.pll_lpf_cap2 = 1;
253 pll->in.pll_iptat_trim = 7;
254 pll->in.pll_c3ctrl = 2;
255 pll->in.pll_r3ctrl = 1;
256 }
257
258 #define CEIL(x, y) (((x) + ((y) - 1)) / (y))
259
260 static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll)
261 {
262 u32 period, ssc_period;
263 u32 ref, rem;
264 u64 step_size;
265
266 DBG("vco=%lld ref=%lld", pll->vco_current_rate, pll->vco_ref_clk_rate);
267
268 ssc_period = pll->in.ssc_freq / 500;
269 period = (u32)pll->vco_ref_clk_rate / 1000;
270 ssc_period = CEIL(period, ssc_period);
271 ssc_period -= 1;
272 pll->out.ssc_period = ssc_period;
273
274 DBG("ssc freq=%d spread=%d period=%d", pll->in.ssc_freq,
275 pll->in.ssc_spread, pll->out.ssc_period);
276
277 step_size = (u32)pll->vco_current_rate;
278 ref = pll->vco_ref_clk_rate;
279 ref /= 1000;
280 step_size = div_u64(step_size, ref);
281 step_size <<= 20;
282 step_size = div_u64(step_size, 1000);
283 step_size *= pll->in.ssc_spread;
284 step_size = div_u64(step_size, 1000);
285 step_size *= (pll->in.ssc_adj_period + 1);
286
287 rem = 0;
288 step_size = div_u64_rem(step_size, ssc_period + 1, &rem);
289 if (rem)
290 step_size++;
291
292 DBG("step_size=%lld", step_size);
293
294 step_size &= 0x0ffff; /* take lower 16 bits */
295
296 pll->out.ssc_step_size = step_size;
297 }
298
299 static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll)
300 {
301 struct dsi_pll_input *pin = &pll->in;
302 struct dsi_pll_output *pout = &pll->out;
303 u64 multiplier = BIT(20);
304 u64 dec_start_multiple, dec_start, pll_comp_val;
305 u32 duration, div_frac_start;
306 u64 vco_clk_rate = pll->vco_current_rate;
307 u64 fref = pll->vco_ref_clk_rate;
308
309 DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref);
310
311 dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref);
312 div_u64_rem(dec_start_multiple, multiplier, &div_frac_start);
313
314 dec_start = div_u64(dec_start_multiple, multiplier);
315
316 pout->dec_start = (u32)dec_start;
317 pout->div_frac_start = div_frac_start;
318
319 if (pin->plllock_cnt == 0)
320 duration = 1024;
321 else if (pin->plllock_cnt == 1)
322 duration = 256;
323 else if (pin->plllock_cnt == 2)
324 duration = 128;
325 else
326 duration = 32;
327
328 pll_comp_val = duration * dec_start_multiple;
329 pll_comp_val = div_u64(pll_comp_val, multiplier);
330 do_div(pll_comp_val, 10);
331
332 pout->plllock_cmp = (u32)pll_comp_val;
333
334 pout->pll_txclk_en = 1;
335 pout->cmn_ldo_cntrl = 0x3c;
336 }
337
338 static u32 pll_14nm_kvco_slop(u32 vrate)
339 {
340 u32 slop = 0;
341
342 if (vrate > VCO_MIN_RATE && vrate <= 1800000000UL)
343 slop = 600;
344 else if (vrate > 1800000000UL && vrate < 2300000000UL)
345 slop = 400;
346 else if (vrate > 2300000000UL && vrate < VCO_MAX_RATE)
347 slop = 280;
348
349 return slop;
350 }
351
352 static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll)
353 {
354 struct dsi_pll_input *pin = &pll->in;
355 struct dsi_pll_output *pout = &pll->out;
356 u64 vco_clk_rate = pll->vco_current_rate;
357 u64 fref = pll->vco_ref_clk_rate;
358 u64 data;
359 u32 cnt;
360
361 data = fref * pin->vco_measure_time;
362 do_div(data, 1000000);
363 data &= 0x03ff; /* 10 bits */
364 data -= 2;
365 pout->pll_vco_div_ref = data;
366
367 data = div_u64(vco_clk_rate, 1000000); /* unit is Mhz */
368 data *= pin->vco_measure_time;
369 do_div(data, 10);
370 pout->pll_vco_count = data;
371
372 data = fref * pin->kvco_measure_time;
373 do_div(data, 1000000);
374 data &= 0x03ff; /* 10 bits */
375 data -= 1;
376 pout->pll_kvco_div_ref = data;
377
378 cnt = pll_14nm_kvco_slop(vco_clk_rate);
379 cnt *= 2;
380 cnt /= 100;
381 cnt *= pin->kvco_measure_time;
382 pout->pll_kvco_count = cnt;
383
384 pout->pll_misc1 = 16;
385 pout->pll_resetsm_cntrl = 48;
386 pout->pll_resetsm_cntrl2 = pin->bandgap_timer << 3;
387 pout->pll_resetsm_cntrl5 = pin->pll_wakeup_timer;
388 pout->pll_kvco_code = 0;
389 }
390
391 static void pll_db_commit_ssc(struct dsi_pll_14nm *pll)
392 {
393 void __iomem *base = pll->mmio;
394 struct dsi_pll_input *pin = &pll->in;
395 struct dsi_pll_output *pout = &pll->out;
396 u8 data;
397
398 data = pin->ssc_adj_period;
399 data &= 0x0ff;
400 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data);
401 data = (pin->ssc_adj_period >> 8);
402 data &= 0x03;
403 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data);
404
405 data = pout->ssc_period;
406 data &= 0x0ff;
407 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data);
408 data = (pout->ssc_period >> 8);
409 data &= 0x0ff;
410 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data);
411
412 data = pout->ssc_step_size;
413 data &= 0x0ff;
414 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data);
415 data = (pout->ssc_step_size >> 8);
416 data &= 0x0ff;
417 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data);
418
419 data = (pin->ssc_center & 0x01);
420 data <<= 1;
421 data |= 0x01; /* enable */
422 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data);
423
424 wmb(); /* make sure register committed */
425 }
426
427 static void pll_db_commit_common(struct dsi_pll_14nm *pll,
428 struct dsi_pll_input *pin,
429 struct dsi_pll_output *pout)
430 {
431 void __iomem *base = pll->mmio;
432 u8 data;
433
434 /* confgiure the non frequency dependent pll registers */
435 data = 0;
436 pll_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data);
437
438 data = pout->pll_txclk_en;
439 pll_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data);
440
441 data = pout->pll_resetsm_cntrl;
442 pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data);
443 data = pout->pll_resetsm_cntrl2;
444 pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data);
445 data = pout->pll_resetsm_cntrl5;
446 pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data);
447
448 data = pout->pll_vco_div_ref & 0xff;
449 pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data);
450 data = (pout->pll_vco_div_ref >> 8) & 0x3;
451 pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data);
452
453 data = pout->pll_kvco_div_ref & 0xff;
454 pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data);
455 data = (pout->pll_kvco_div_ref >> 8) & 0x3;
456 pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data);
457
458 data = pout->pll_misc1;
459 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data);
460
461 data = pin->pll_ie_trim;
462 pll_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data);
463
464 data = pin->pll_ip_trim;
465 pll_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data);
466
467 data = pin->pll_cpmset_cur << 3 | pin->pll_cpcset_cur;
468 pll_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data);
469
470 data = pin->pll_icpcset_p << 3 | pin->pll_icpcset_m;
471 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data);
472
473 data = pin->pll_icpmset_p << 3 | pin->pll_icpcset_m;
474 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data);
475
476 data = pin->pll_icpmset << 3 | pin->pll_icpcset;
477 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data);
478
479 data = pin->pll_lpf_cap2 << 4 | pin->pll_lpf_cap1;
480 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data);
481
482 data = pin->pll_iptat_trim;
483 pll_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data);
484
485 data = pin->pll_c3ctrl | pin->pll_r3ctrl << 4;
486 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data);
487 }
488
489 static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
490 {
491 void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
492
493 /* de assert pll start and apply pll sw reset */
494
495 /* stop pll */
496 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
497
498 /* pll sw reset */
499 pll_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10);
500 wmb(); /* make sure register committed */
501
502 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0);
503 wmb(); /* make sure register committed */
504 }
505
506 static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
507 struct dsi_pll_input *pin,
508 struct dsi_pll_output *pout)
509 {
510 void __iomem *base = pll->mmio;
511 void __iomem *cmn_base = pll->phy_cmn_mmio;
512 u8 data;
513
514 DBG("DSI%d PLL", pll->id);
515
516 data = pout->cmn_ldo_cntrl;
517 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
518
519 pll_db_commit_common(pll, pin, pout);
520
521 pll_14nm_software_reset(pll);
522
523 data = pin->dsiclk_sel; /* set dsiclk_sel = 1 */
524 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data);
525
526 data = 0xff; /* data, clk, pll normal operation */
527 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data);
528
529 /* configure the frequency dependent pll registers */
530 data = pout->dec_start;
531 pll_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data);
532
533 data = pout->div_frac_start & 0xff;
534 pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data);
535 data = (pout->div_frac_start >> 8) & 0xff;
536 pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data);
537 data = (pout->div_frac_start >> 16) & 0xf;
538 pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data);
539
540 data = pout->plllock_cmp & 0xff;
541 pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data);
542
543 data = (pout->plllock_cmp >> 8) & 0xff;
544 pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data);
545
546 data = (pout->plllock_cmp >> 16) & 0x3;
547 pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data);
548
549 data = pin->plllock_cnt << 1 | pin->plllock_rng << 3;
550 pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data);
551
552 data = pout->pll_vco_count & 0xff;
553 pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data);
554 data = (pout->pll_vco_count >> 8) & 0xff;
555 pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data);
556
557 data = pout->pll_kvco_count & 0xff;
558 pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data);
559 data = (pout->pll_kvco_count >> 8) & 0x3;
560 pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data);
561
562 data = (pout->pll_postdiv - 1) << 4 | pin->pll_lpf_res1;
563 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data);
564
565 if (pin->ssc_en)
566 pll_db_commit_ssc(pll);
567
568 wmb(); /* make sure register committed */
569 }
570
571 /*
572 * VCO clock Callbacks
573 */
574 static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
575 unsigned long parent_rate)
576 {
577 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
578 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
579 struct dsi_pll_input *pin = &pll_14nm->in;
580 struct dsi_pll_output *pout = &pll_14nm->out;
581
582 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->id, rate,
583 parent_rate);
584
585 pll_14nm->vco_current_rate = rate;
586 pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
587
588 dsi_pll_14nm_input_init(pll_14nm);
589
590 /*
591 * This configures the post divider internal to the VCO. It's
592 * fixed to divide by 1 for now.
593 *
594 * tx_band = pll_postdiv.
595 * 0: divided by 1
596 * 1: divided by 2
597 * 2: divided by 4
598 * 3: divided by 8
599 */
600 pout->pll_postdiv = DSI_PLL_DEFAULT_VCO_POSTDIV;
601
602 pll_14nm_dec_frac_calc(pll_14nm);
603
604 if (pin->ssc_en)
605 pll_14nm_ssc_calc(pll_14nm);
606
607 pll_14nm_calc_vco_count(pll_14nm);
608
609 /* commit the slave DSI PLL registers if we're master. Note that we
610 * don't lock the slave PLL. We just ensure that the PLL/PHY registers
611 * of the master and slave are identical
612 */
613 if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
614 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
615
616 pll_db_commit_14nm(pll_14nm_slave, pin, pout);
617 }
618
619 pll_db_commit_14nm(pll_14nm, pin, pout);
620
621 return 0;
622 }
623
624 static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
625 unsigned long parent_rate)
626 {
627 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
628 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
629 void __iomem *base = pll_14nm->mmio;
630 u64 vco_rate, multiplier = BIT(20);
631 u32 div_frac_start;
632 u32 dec_start;
633 u64 ref_clk = parent_rate;
634
635 dec_start = pll_read(base + REG_DSI_14nm_PHY_PLL_DEC_START);
636 dec_start &= 0x0ff;
637
638 DBG("dec_start = %x", dec_start);
639
640 div_frac_start = (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
641 & 0xf) << 16;
642 div_frac_start |= (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
643 & 0xff) << 8;
644 div_frac_start |= pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
645 & 0xff;
646
647 DBG("div_frac_start = %x", div_frac_start);
648
649 vco_rate = ref_clk * dec_start;
650
651 vco_rate += ((ref_clk * div_frac_start) / multiplier);
652
653 /*
654 * Recalculating the rate from dec_start and frac_start doesn't end up
655 * the rate we originally set. Convert the freq to KHz, round it up and
656 * convert it back to MHz.
657 */
658 vco_rate = DIV_ROUND_UP_ULL(vco_rate, 1000) * 1000;
659
660 DBG("returning vco rate = %lu", (unsigned long)vco_rate);
661
662 return (unsigned long)vco_rate;
663 }
664
665 static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {
666 .round_rate = msm_dsi_pll_helper_clk_round_rate,
667 .set_rate = dsi_pll_14nm_vco_set_rate,
668 .recalc_rate = dsi_pll_14nm_vco_recalc_rate,
669 .prepare = msm_dsi_pll_helper_clk_prepare,
670 .unprepare = msm_dsi_pll_helper_clk_unprepare,
671 };
672
673 /*
674 * N1 and N2 post-divider clock callbacks
675 */
676 #define div_mask(width) ((1 << (width)) - 1)
677 static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
678 unsigned long parent_rate)
679 {
680 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
681 struct dsi_pll_14nm *pll_14nm = postdiv->pll;
682 void __iomem *base = pll_14nm->phy_cmn_mmio;
683 u8 shift = postdiv->shift;
684 u8 width = postdiv->width;
685 u32 val;
686
687 DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, parent_rate);
688
689 val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
690 val &= div_mask(width);
691
692 return divider_recalc_rate(hw, parent_rate, val, NULL,
693 postdiv->flags, width);
694 }
695
696 static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw,
697 unsigned long rate,
698 unsigned long *prate)
699 {
700 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
701 struct dsi_pll_14nm *pll_14nm = postdiv->pll;
702
703 DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, rate);
704
705 return divider_round_rate(hw, rate, prate, NULL,
706 postdiv->width,
707 postdiv->flags);
708 }
709
710 static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
711 unsigned long parent_rate)
712 {
713 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
714 struct dsi_pll_14nm *pll_14nm = postdiv->pll;
715 void __iomem *base = pll_14nm->phy_cmn_mmio;
716 spinlock_t *lock = &pll_14nm->postdiv_lock;
717 u8 shift = postdiv->shift;
718 u8 width = postdiv->width;
719 unsigned int value;
720 unsigned long flags = 0;
721 u32 val;
722
723 DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->id, rate,
724 parent_rate);
725
726 value = divider_get_val(rate, parent_rate, NULL, postdiv->width,
727 postdiv->flags);
728
729 spin_lock_irqsave(lock, flags);
730
731 val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
732 val &= ~(div_mask(width) << shift);
733
734 val |= value << shift;
735 pll_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
736
737 /* If we're master in dual DSI mode, then the slave PLL's post-dividers
738 * follow the master's post dividers
739 */
740 if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
741 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
742 void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
743
744 pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
745 }
746
747 spin_unlock_irqrestore(lock, flags);
748
749 return 0;
750 }
751
752 static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = {
753 .recalc_rate = dsi_pll_14nm_postdiv_recalc_rate,
754 .round_rate = dsi_pll_14nm_postdiv_round_rate,
755 .set_rate = dsi_pll_14nm_postdiv_set_rate,
756 };
757
758 /*
759 * PLL Callbacks
760 */
761
762 static int dsi_pll_14nm_enable_seq(struct msm_dsi_pll *pll)
763 {
764 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
765 void __iomem *base = pll_14nm->mmio;
766 void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
767 bool locked;
768
769 DBG("");
770
771 pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
772 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
773
774 locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
775 POLL_TIMEOUT_US);
776
777 if (unlikely(!locked))
778 DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n");
779 else
780 DBG("DSI PLL lock success");
781
782 return locked ? 0 : -EINVAL;
783 }
784
785 static void dsi_pll_14nm_disable_seq(struct msm_dsi_pll *pll)
786 {
787 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
788 void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
789
790 DBG("");
791
792 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
793 }
794
795 static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll)
796 {
797 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
798 struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
799 void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
800 u32 data;
801
802 data = pll_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
803
804 cached_state->n1postdiv = data & 0xf;
805 cached_state->n2postdiv = (data >> 4) & 0xf;
806
807 DBG("DSI%d PLL save state %x %x", pll_14nm->id,
808 cached_state->n1postdiv, cached_state->n2postdiv);
809
810 cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
811 }
812
813 static int dsi_pll_14nm_restore_state(struct msm_dsi_pll *pll)
814 {
815 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
816 struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
817 void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
818 u32 data;
819 int ret;
820
821 ret = dsi_pll_14nm_vco_set_rate(&pll->clk_hw,
822 cached_state->vco_rate, 0);
823 if (ret) {
824 DRM_DEV_ERROR(&pll_14nm->pdev->dev,
825 "restore vco rate failed. ret=%d\n", ret);
826 return ret;
827 }
828
829 data = cached_state->n1postdiv | (cached_state->n2postdiv << 4);
830
831 DBG("DSI%d PLL restore state %x %x", pll_14nm->id,
832 cached_state->n1postdiv, cached_state->n2postdiv);
833
834 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
835
836 /* also restore post-dividers for slave DSI PLL */
837 if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
838 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
839 void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
840
841 pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
842 }
843
844 return 0;
845 }
846
847 static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll,
848 enum msm_dsi_phy_usecase uc)
849 {
850 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
851 void __iomem *base = pll_14nm->mmio;
852 u32 clkbuflr_en, bandgap = 0;
853
854 switch (uc) {
855 case MSM_DSI_PHY_STANDALONE:
856 clkbuflr_en = 0x1;
857 break;
858 case MSM_DSI_PHY_MASTER:
859 clkbuflr_en = 0x3;
860 pll_14nm->slave = pll_14nm_list[(pll_14nm->id + 1) % DSI_MAX];
861 break;
862 case MSM_DSI_PHY_SLAVE:
863 clkbuflr_en = 0x0;
864 bandgap = 0x3;
865 break;
866 default:
867 return -EINVAL;
868 }
869
870 pll_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en);
871 if (bandgap)
872 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);
873
874 pll_14nm->uc = uc;
875
876 return 0;
877 }
878
879 static int dsi_pll_14nm_get_provider(struct msm_dsi_pll *pll,
880 struct clk **byte_clk_provider,
881 struct clk **pixel_clk_provider)
882 {
883 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
884 struct clk_hw_onecell_data *hw_data = pll_14nm->hw_data;
885
886 if (byte_clk_provider)
887 *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk;
888 if (pixel_clk_provider)
889 *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk;
890
891 return 0;
892 }
893
894 static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll)
895 {
896 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
897 struct platform_device *pdev = pll_14nm->pdev;
898 int num_hws = pll_14nm->num_hws;
899
900 of_clk_del_provider(pdev->dev.of_node);
901
902 while (num_hws--)
903 clk_hw_unregister(pll_14nm->hws[num_hws]);
904 }
905
906 static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
907 const char *name,
908 const char *parent_name,
909 unsigned long flags,
910 u8 shift)
911 {
912 struct dsi_pll_14nm_postdiv *pll_postdiv;
913 struct device *dev = &pll_14nm->pdev->dev;
914 struct clk_init_data postdiv_init = {
915 .parent_names = (const char *[]) { parent_name },
916 .num_parents = 1,
917 .name = name,
918 .flags = flags,
919 .ops = &clk_ops_dsi_pll_14nm_postdiv,
920 };
921 int ret;
922
923 pll_postdiv = devm_kzalloc(dev, sizeof(*pll_postdiv), GFP_KERNEL);
924 if (!pll_postdiv)
925 return ERR_PTR(-ENOMEM);
926
927 pll_postdiv->pll = pll_14nm;
928 pll_postdiv->shift = shift;
929 /* both N1 and N2 postdividers are 4 bits wide */
930 pll_postdiv->width = 4;
931 /* range of each divider is from 1 to 15 */
932 pll_postdiv->flags = CLK_DIVIDER_ONE_BASED;
933 pll_postdiv->hw.init = &postdiv_init;
934
935 ret = clk_hw_register(dev, &pll_postdiv->hw);
936 if (ret)
937 return ERR_PTR(ret);
938
939 return &pll_postdiv->hw;
940 }
941
942 static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
943 {
944 char clk_name[32], parent[32], vco_name[32];
945 struct clk_init_data vco_init = {
946 .parent_names = (const char *[]){ "xo" },
947 .num_parents = 1,
948 .name = vco_name,
949 .flags = CLK_IGNORE_UNUSED,
950 .ops = &clk_ops_dsi_pll_14nm_vco,
951 };
952 struct device *dev = &pll_14nm->pdev->dev;
953 struct clk_hw **hws = pll_14nm->hws;
954 struct clk_hw_onecell_data *hw_data;
955 struct clk_hw *hw;
956 int num = 0;
957 int ret;
958
959 DBG("DSI%d", pll_14nm->id);
960
961 hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
962 NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
963 GFP_KERNEL);
964 if (!hw_data)
965 return -ENOMEM;
966
967 snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
968 pll_14nm->base.clk_hw.init = &vco_init;
969
970 ret = clk_hw_register(dev, &pll_14nm->base.clk_hw);
971 if (ret)
972 return ret;
973
974 hws[num++] = &pll_14nm->base.clk_hw;
975
976 snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
977 snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->id);
978
979 /* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */
980 hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent,
981 CLK_SET_RATE_PARENT, 0);
982 if (IS_ERR(hw))
983 return PTR_ERR(hw);
984
985 hws[num++] = hw;
986
987 snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->id);
988 snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
989
990 /* DSI Byte clock = VCO_CLK / N1 / 8 */
991 hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
992 CLK_SET_RATE_PARENT, 1, 8);
993 if (IS_ERR(hw))
994 return PTR_ERR(hw);
995
996 hws[num++] = hw;
997 hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
998
999 snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
1000 snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
1001
1002 /*
1003 * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider
1004 * on the way. Don't let it set parent.
1005 */
1006 hw = clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2);
1007 if (IS_ERR(hw))
1008 return PTR_ERR(hw);
1009
1010 hws[num++] = hw;
1011
1012 snprintf(clk_name, 32, "dsi%dpll", pll_14nm->id);
1013 snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
1014
1015 /* DSI pixel clock = VCO_CLK / N1 / 2 / N2
1016 * This is the output of N2 post-divider, bits 4-7 in
1017 * REG_DSI_14nm_PHY_CMN_CLK_CFG0. Don't let it set parent.
1018 */
1019 hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, 0, 4);
1020 if (IS_ERR(hw))
1021 return PTR_ERR(hw);
1022
1023 hws[num++] = hw;
1024 hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
1025
1026 pll_14nm->num_hws = num;
1027
1028 hw_data->num = NUM_PROVIDED_CLKS;
1029 pll_14nm->hw_data = hw_data;
1030
1031 ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
1032 pll_14nm->hw_data);
1033 if (ret) {
1034 DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
1035 return ret;
1036 }
1037
1038 return 0;
1039 }
1040
1041 struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id)
1042 {
1043 struct dsi_pll_14nm *pll_14nm;
1044 struct msm_dsi_pll *pll;
1045 int ret;
1046
1047 if (!pdev)
1048 return ERR_PTR(-ENODEV);
1049
1050 pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL);
1051 if (!pll_14nm)
1052 return ERR_PTR(-ENOMEM);
1053
1054 DBG("PLL%d", id);
1055
1056 pll_14nm->pdev = pdev;
1057 pll_14nm->id = id;
1058 pll_14nm_list[id] = pll_14nm;
1059
1060 pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
1061 if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {
1062 DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");
1063 return ERR_PTR(-ENOMEM);
1064 }
1065
1066 pll_14nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
1067 if (IS_ERR_OR_NULL(pll_14nm->mmio)) {
1068 DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");
1069 return ERR_PTR(-ENOMEM);
1070 }
1071
1072 spin_lock_init(&pll_14nm->postdiv_lock);
1073
1074 pll = &pll_14nm->base;
1075 pll->min_rate = VCO_MIN_RATE;
1076 pll->max_rate = VCO_MAX_RATE;
1077 pll->get_provider = dsi_pll_14nm_get_provider;
1078 pll->destroy = dsi_pll_14nm_destroy;
1079 pll->disable_seq = dsi_pll_14nm_disable_seq;
1080 pll->save_state = dsi_pll_14nm_save_state;
1081 pll->restore_state = dsi_pll_14nm_restore_state;
1082 pll->set_usecase = dsi_pll_14nm_set_usecase;
1083
1084 pll_14nm->vco_delay = 1;
1085
1086 pll->en_seq_cnt = 1;
1087 pll->enable_seqs[0] = dsi_pll_14nm_enable_seq;
1088
1089 ret = pll_14nm_register(pll_14nm);
1090 if (ret) {
1091 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
1092 return ERR_PTR(ret);
1093 }
1094
1095 return pll;
1096 }
Linux with added FPC-III support