?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'io_uring-5.11-2021-01-16' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / gpu / drm / msm / dsi / pll / dsi_pll_7nm.c
blob93bf142e4a4e6ad0c4048ce3d2c3f9674f9460c4
1 /*
2 * SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/iopoll.h>
9
10 #include "dsi_pll.h"
11 #include "dsi.xml.h"
12
13 /*
14 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
15 *
16 * dsi0_pll_out_div_clk dsi0_pll_bit_clk
17 * | |
18 * | |
19 * +---------+ | +----------+ | +----+
20 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
21 * +---------+ | +----------+ | +----+
22 * | |
23 * | | dsi0_pll_by_2_bit_clk
24 * | | |
25 * | | +----+ | |\ dsi0_pclk_mux
26 * | |--| /2 |--o--| \ |
27 * | | +----+ | \ | +---------+
28 * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk
29 * |------------------------------| / +---------+
30 * | +-----+ | /
31 * -----------| /4? |--o----------|/
32 * +-----+ | |
33 * | |dsiclk_sel
34 * |
35 * dsi0_pll_post_out_div_clk
36 */
37
38 #define DSI_BYTE_PLL_CLK 0
39 #define DSI_PIXEL_PLL_CLK 1
40 #define NUM_PROVIDED_CLKS 2
41
42 #define VCO_REF_CLK_RATE 19200000
43
44 struct dsi_pll_regs {
45 u32 pll_prop_gain_rate;
46 u32 pll_lockdet_rate;
47 u32 decimal_div_start;
48 u32 frac_div_start_low;
49 u32 frac_div_start_mid;
50 u32 frac_div_start_high;
51 u32 pll_clock_inverters;
52 u32 ssc_stepsize_low;
53 u32 ssc_stepsize_high;
54 u32 ssc_div_per_low;
55 u32 ssc_div_per_high;
56 u32 ssc_adjper_low;
57 u32 ssc_adjper_high;
58 u32 ssc_control;
59 };
60
61 struct dsi_pll_config {
62 u32 ref_freq;
63 bool div_override;
64 u32 output_div;
65 bool ignore_frac;
66 bool disable_prescaler;
67 bool enable_ssc;
68 bool ssc_center;
69 u32 dec_bits;
70 u32 frac_bits;
71 u32 lock_timer;
72 u32 ssc_freq;
73 u32 ssc_offset;
74 u32 ssc_adj_per;
75 u32 thresh_cycles;
76 u32 refclk_cycles;
77 };
78
79 struct pll_7nm_cached_state {
80 unsigned long vco_rate;
81 u8 bit_clk_div;
82 u8 pix_clk_div;
83 u8 pll_out_div;
84 u8 pll_mux;
85 };
86
87 struct dsi_pll_7nm {
88 struct msm_dsi_pll base;
89
90 int id;
91 struct platform_device *pdev;
92
93 void __iomem *phy_cmn_mmio;
94 void __iomem *mmio;
95
96 u64 vco_ref_clk_rate;
97 u64 vco_current_rate;
98
99 /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
100 spinlock_t postdiv_lock;
101
102 int vco_delay;
103 struct dsi_pll_config pll_configuration;
104 struct dsi_pll_regs reg_setup;
105
106 /* private clocks: */
107 struct clk_hw *out_div_clk_hw;
108 struct clk_hw *bit_clk_hw;
109 struct clk_hw *byte_clk_hw;
110 struct clk_hw *by_2_bit_clk_hw;
111 struct clk_hw *post_out_div_clk_hw;
112 struct clk_hw *pclk_mux_hw;
113 struct clk_hw *out_dsiclk_hw;
114
115 /* clock-provider: */
116 struct clk_hw_onecell_data *hw_data;
117
118 struct pll_7nm_cached_state cached_state;
119
120 enum msm_dsi_phy_usecase uc;
121 struct dsi_pll_7nm *slave;
122 };
123
124 #define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, base)
125
126 /*
127 * Global list of private DSI PLL struct pointers. We need this for Dual DSI
128 * mode, where the master PLL's clk_ops needs access the slave's private data
129 */
130 static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX];
131
132 static void dsi_pll_setup_config(struct dsi_pll_7nm *pll)
133 {
134 struct dsi_pll_config *config = &pll->pll_configuration;
135
136 config->ref_freq = pll->vco_ref_clk_rate;
137 config->output_div = 1;
138 config->dec_bits = 8;
139 config->frac_bits = 18;
140 config->lock_timer = 64;
141 config->ssc_freq = 31500;
142 config->ssc_offset = 4800;
143 config->ssc_adj_per = 2;
144 config->thresh_cycles = 32;
145 config->refclk_cycles = 256;
146
147 config->div_override = false;
148 config->ignore_frac = false;
149 config->disable_prescaler = false;
150
151 /* TODO: ssc enable */
152 config->enable_ssc = false;
153 config->ssc_center = 0;
154 }
155
156 static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll)
157 {
158 struct dsi_pll_config *config = &pll->pll_configuration;
159 struct dsi_pll_regs *regs = &pll->reg_setup;
160 u64 fref = pll->vco_ref_clk_rate;
161 u64 pll_freq;
162 u64 divider;
163 u64 dec, dec_multiple;
164 u32 frac;
165 u64 multiplier;
166
167 pll_freq = pll->vco_current_rate;
168
169 if (config->disable_prescaler)
170 divider = fref;
171 else
172 divider = fref * 2;
173
174 multiplier = 1 << config->frac_bits;
175 dec_multiple = div_u64(pll_freq * multiplier, divider);
176 div_u64_rem(dec_multiple, multiplier, &frac);
177
178 dec = div_u64(dec_multiple, multiplier);
179
180 if (pll->base.type != MSM_DSI_PHY_7NM_V4_1)
181 regs->pll_clock_inverters = 0x28;
182 else if (pll_freq <= 1000000000ULL)
183 regs->pll_clock_inverters = 0xa0;
184 else if (pll_freq <= 2500000000ULL)
185 regs->pll_clock_inverters = 0x20;
186 else if (pll_freq <= 3020000000ULL)
187 regs->pll_clock_inverters = 0x00;
188 else
189 regs->pll_clock_inverters = 0x40;
190
191 regs->pll_lockdet_rate = config->lock_timer;
192 regs->decimal_div_start = dec;
193 regs->frac_div_start_low = (frac & 0xff);
194 regs->frac_div_start_mid = (frac & 0xff00) >> 8;
195 regs->frac_div_start_high = (frac & 0x30000) >> 16;
196 }
197
198 #define SSC_CENTER BIT(0)
199 #define SSC_EN BIT(1)
200
201 static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll)
202 {
203 struct dsi_pll_config *config = &pll->pll_configuration;
204 struct dsi_pll_regs *regs = &pll->reg_setup;
205 u32 ssc_per;
206 u32 ssc_mod;
207 u64 ssc_step_size;
208 u64 frac;
209
210 if (!config->enable_ssc) {
211 DBG("SSC not enabled\n");
212 return;
213 }
214
215 ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1;
216 ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
217 ssc_per -= ssc_mod;
218
219 frac = regs->frac_div_start_low |
220 (regs->frac_div_start_mid << 8) |
221 (regs->frac_div_start_high << 16);
222 ssc_step_size = regs->decimal_div_start;
223 ssc_step_size *= (1 << config->frac_bits);
224 ssc_step_size += frac;
225 ssc_step_size *= config->ssc_offset;
226 ssc_step_size *= (config->ssc_adj_per + 1);
227 ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
228 ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
229
230 regs->ssc_div_per_low = ssc_per & 0xFF;
231 regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8;
232 regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF);
233 regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8);
234 regs->ssc_adjper_low = config->ssc_adj_per & 0xFF;
235 regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8;
236
237 regs->ssc_control = config->ssc_center ? SSC_CENTER : 0;
238
239 pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
240 regs->decimal_div_start, frac, config->frac_bits);
241 pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
242 ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
243 }
244
245 static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll)
246 {
247 void __iomem *base = pll->mmio;
248 struct dsi_pll_regs *regs = &pll->reg_setup;
249
250 if (pll->pll_configuration.enable_ssc) {
251 pr_debug("SSC is enabled\n");
252
253 pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
254 regs->ssc_stepsize_low);
255 pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
256 regs->ssc_stepsize_high);
257 pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1,
258 regs->ssc_div_per_low);
259 pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
260 regs->ssc_div_per_high);
261 pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1,
262 regs->ssc_adjper_low);
263 pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1,
264 regs->ssc_adjper_high);
265 pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL,
266 SSC_EN | regs->ssc_control);
267 }
268 }
269
270 static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
271 {
272 void __iomem *base = pll->mmio;
273 u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
274
275 if (pll->base.type == MSM_DSI_PHY_7NM_V4_1) {
276 if (pll->vco_current_rate >= 3100000000ULL)
277 analog_controls_five_1 = 0x03;
278
279 if (pll->vco_current_rate < 1520000000ULL)
280 vco_config_1 = 0x08;
281 else if (pll->vco_current_rate < 2990000000ULL)
282 vco_config_1 = 0x01;
283 }
284
285 pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
286 analog_controls_five_1);
287 pll_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
288 pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01);
289 pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
290 pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
291 pll_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00);
292 pll_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
293 pll_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
294 pll_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba);
295 pll_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
296 pll_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00);
297 pll_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00);
298 pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
299 pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a);
300 pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0);
301 pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84);
302 pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82);
303 pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c);
304 pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
305 pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29);
306 pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
307 pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
308 pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
309 pll->base.type == MSM_DSI_PHY_7NM_V4_1 ? 0x3f : 0x22);
310
311 if (pll->base.type == MSM_DSI_PHY_7NM_V4_1) {
312 pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
313 if (pll->slave)
314 pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
315 }
316 }
317
318 static void dsi_pll_commit(struct dsi_pll_7nm *pll)
319 {
320 void __iomem *base = pll->mmio;
321 struct dsi_pll_regs *reg = &pll->reg_setup;
322
323 pll_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
324 pll_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, reg->decimal_div_start);
325 pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, reg->frac_div_start_low);
326 pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, reg->frac_div_start_mid);
327 pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high);
328 pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40);
329 pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
330 pll_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */
331 pll_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, reg->pll_clock_inverters);
332 }
333
334 static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
335 unsigned long parent_rate)
336 {
337 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
338 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
339
340 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->id, rate,
341 parent_rate);
342
343 pll_7nm->vco_current_rate = rate;
344 pll_7nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
345
346 dsi_pll_setup_config(pll_7nm);
347
348 dsi_pll_calc_dec_frac(pll_7nm);
349
350 dsi_pll_calc_ssc(pll_7nm);
351
352 dsi_pll_commit(pll_7nm);
353
354 dsi_pll_config_hzindep_reg(pll_7nm);
355
356 dsi_pll_ssc_commit(pll_7nm);
357
358 /* flush, ensure all register writes are done*/
359 wmb();
360
361 return 0;
362 }
363
364 static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
365 {
366 int rc;
367 u32 status = 0;
368 u32 const delay_us = 100;
369 u32 const timeout_us = 5000;
370
371 rc = readl_poll_timeout_atomic(pll->mmio +
372 REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE,
373 status,
374 ((status & BIT(0)) > 0),
375 delay_us,
376 timeout_us);
377 if (rc)
378 pr_err("DSI PLL(%d) lock failed, status=0x%08x\n",
379 pll->id, status);
380
381 return rc;
382 }
383
384 static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
385 {
386 u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0);
387
388 pll_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
389 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5));
390 ndelay(250);
391 }
392
393 static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
394 {
395 u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0);
396
397 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5));
398 pll_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
399 ndelay(250);
400 }
401
402 static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
403 {
404 u32 data;
405
406 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
407 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5));
408 }
409
410 static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
411 {
412 u32 data;
413
414 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
415
416 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
417 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
418 data | BIT(5) | BIT(4));
419 }
420
421 static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
422 {
423 /*
424 * Reset the PHY digital domain. This would be needed when
425 * coming out of a CX or analog rail power collapse while
426 * ensuring that the pads maintain LP00 or LP11 state
427 */
428 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
429 wmb(); /* Ensure that the reset is deasserted */
430 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
431 wmb(); /* Ensure that the reset is deasserted */
432 }
433
434 static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
435 {
436 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
437 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
438 int rc;
439
440 dsi_pll_enable_pll_bias(pll_7nm);
441 if (pll_7nm->slave)
442 dsi_pll_enable_pll_bias(pll_7nm->slave);
443
444 /* Start PLL */
445 pll_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01);
446
447 /*
448 * ensure all PLL configurations are written prior to checking
449 * for PLL lock.
450 */
451 wmb();
452
453 /* Check for PLL lock */
454 rc = dsi_pll_7nm_lock_status(pll_7nm);
455 if (rc) {
456 pr_err("PLL(%d) lock failed\n", pll_7nm->id);
457 goto error;
458 }
459
460 pll->pll_on = true;
461
462 /*
463 * assert power on reset for PHY digital in case the PLL is
464 * enabled after CX of analog domain power collapse. This needs
465 * to be done before enabling the global clk.
466 */
467 dsi_pll_phy_dig_reset(pll_7nm);
468 if (pll_7nm->slave)
469 dsi_pll_phy_dig_reset(pll_7nm->slave);
470
471 dsi_pll_enable_global_clk(pll_7nm);
472 if (pll_7nm->slave)
473 dsi_pll_enable_global_clk(pll_7nm->slave);
474
475 error:
476 return rc;
477 }
478
479 static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll)
480 {
481 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
482 dsi_pll_disable_pll_bias(pll);
483 }
484
485 static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw)
486 {
487 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
488 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
489
490 /*
491 * To avoid any stray glitches while abruptly powering down the PLL
492 * make sure to gate the clock using the clock enable bit before
493 * powering down the PLL
494 */
495 dsi_pll_disable_global_clk(pll_7nm);
496 pll_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0);
497 dsi_pll_disable_sub(pll_7nm);
498 if (pll_7nm->slave) {
499 dsi_pll_disable_global_clk(pll_7nm->slave);
500 dsi_pll_disable_sub(pll_7nm->slave);
501 }
502 /* flush, ensure all register writes are done */
503 wmb();
504 pll->pll_on = false;
505 }
506
507 static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
508 unsigned long parent_rate)
509 {
510 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
511 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
512 void __iomem *base = pll_7nm->mmio;
513 u64 ref_clk = pll_7nm->vco_ref_clk_rate;
514 u64 vco_rate = 0x0;
515 u64 multiplier;
516 u32 frac;
517 u32 dec;
518 u64 pll_freq, tmp64;
519
520 dec = pll_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
521 dec &= 0xff;
522
523 frac = pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
524 frac |= ((pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) &
525 0xff) << 8);
526 frac |= ((pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
527 0x3) << 16);
528
529 /*
530 * TODO:
531 * 1. Assumes prescaler is disabled
532 * 2. Multiplier is 2^18. it should be 2^(num_of_frac_bits)
533 */
534 multiplier = 1 << 18;
535 pll_freq = dec * (ref_clk * 2);
536 tmp64 = (ref_clk * 2 * frac);
537 pll_freq += div_u64(tmp64, multiplier);
538
539 vco_rate = pll_freq;
540
541 DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
542 pll_7nm->id, (unsigned long)vco_rate, dec, frac);
543
544 return (unsigned long)vco_rate;
545 }
546
547 static const struct clk_ops clk_ops_dsi_pll_7nm_vco = {
548 .round_rate = msm_dsi_pll_helper_clk_round_rate,
549 .set_rate = dsi_pll_7nm_vco_set_rate,
550 .recalc_rate = dsi_pll_7nm_vco_recalc_rate,
551 .prepare = dsi_pll_7nm_vco_prepare,
552 .unprepare = dsi_pll_7nm_vco_unprepare,
553 };
554
555 /*
556 * PLL Callbacks
557 */
558
559 static void dsi_pll_7nm_save_state(struct msm_dsi_pll *pll)
560 {
561 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
562 struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
563 void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
564 u32 cmn_clk_cfg0, cmn_clk_cfg1;
565
566 cached->pll_out_div = pll_read(pll_7nm->mmio +
567 REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
568 cached->pll_out_div &= 0x3;
569
570 cmn_clk_cfg0 = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
571 cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
572 cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
573
574 cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
575 cached->pll_mux = cmn_clk_cfg1 & 0x3;
576
577 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
578 pll_7nm->id, cached->pll_out_div, cached->bit_clk_div,
579 cached->pix_clk_div, cached->pll_mux);
580 }
581
582 static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll)
583 {
584 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
585 struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
586 void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
587 u32 val;
588 int ret;
589
590 val = pll_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
591 val &= ~0x3;
592 val |= cached->pll_out_div;
593 pll_write(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val);
594
595 pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
596 cached->bit_clk_div | (cached->pix_clk_div << 4));
597
598 val = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
599 val &= ~0x3;
600 val |= cached->pll_mux;
601 pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
602
603 ret = dsi_pll_7nm_vco_set_rate(&pll->clk_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
604 if (ret) {
605 DRM_DEV_ERROR(&pll_7nm->pdev->dev,
606 "restore vco rate failed. ret=%d\n", ret);
607 return ret;
608 }
609
610 DBG("DSI PLL%d", pll_7nm->id);
611
612 return 0;
613 }
614
615 static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll,
616 enum msm_dsi_phy_usecase uc)
617 {
618 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
619 void __iomem *base = pll_7nm->phy_cmn_mmio;
620 u32 data = 0x0; /* internal PLL */
621
622 DBG("DSI PLL%d", pll_7nm->id);
623
624 switch (uc) {
625 case MSM_DSI_PHY_STANDALONE:
626 break;
627 case MSM_DSI_PHY_MASTER:
628 pll_7nm->slave = pll_7nm_list[(pll_7nm->id + 1) % DSI_MAX];
629 break;
630 case MSM_DSI_PHY_SLAVE:
631 data = 0x1; /* external PLL */
632 break;
633 default:
634 return -EINVAL;
635 }
636
637 /* set PLL src */
638 pll_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2));
639
640 pll_7nm->uc = uc;
641
642 return 0;
643 }
644
645 static int dsi_pll_7nm_get_provider(struct msm_dsi_pll *pll,
646 struct clk **byte_clk_provider,
647 struct clk **pixel_clk_provider)
648 {
649 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
650 struct clk_hw_onecell_data *hw_data = pll_7nm->hw_data;
651
652 DBG("DSI PLL%d", pll_7nm->id);
653
654 if (byte_clk_provider)
655 *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk;
656 if (pixel_clk_provider)
657 *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk;
658
659 return 0;
660 }
661
662 static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll)
663 {
664 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
665 struct device *dev = &pll_7nm->pdev->dev;
666
667 DBG("DSI PLL%d", pll_7nm->id);
668 of_clk_del_provider(dev->of_node);
669
670 clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw);
671 clk_hw_unregister_mux(pll_7nm->pclk_mux_hw);
672 clk_hw_unregister_fixed_factor(pll_7nm->post_out_div_clk_hw);
673 clk_hw_unregister_fixed_factor(pll_7nm->by_2_bit_clk_hw);
674 clk_hw_unregister_fixed_factor(pll_7nm->byte_clk_hw);
675 clk_hw_unregister_divider(pll_7nm->bit_clk_hw);
676 clk_hw_unregister_divider(pll_7nm->out_div_clk_hw);
677 clk_hw_unregister(&pll_7nm->base.clk_hw);
678 }
679
680 /*
681 * The post dividers and mux clocks are created using the standard divider and
682 * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
683 * state to follow the master PLL's divider/mux state. Therefore, we don't
684 * require special clock ops that also configure the slave PLL registers
685 */
686 static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm)
687 {
688 char clk_name[32], parent[32], vco_name[32];
689 char parent2[32], parent3[32], parent4[32];
690 struct clk_init_data vco_init = {
691 .parent_names = (const char *[]){ "bi_tcxo" },
692 .num_parents = 1,
693 .name = vco_name,
694 .flags = CLK_IGNORE_UNUSED,
695 .ops = &clk_ops_dsi_pll_7nm_vco,
696 };
697 struct device *dev = &pll_7nm->pdev->dev;
698 struct clk_hw_onecell_data *hw_data;
699 struct clk_hw *hw;
700 int ret;
701
702 DBG("DSI%d", pll_7nm->id);
703
704 hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
705 NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
706 GFP_KERNEL);
707 if (!hw_data)
708 return -ENOMEM;
709
710 snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id);
711 pll_7nm->base.clk_hw.init = &vco_init;
712
713 ret = clk_hw_register(dev, &pll_7nm->base.clk_hw);
714 if (ret)
715 return ret;
716
717 snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
718 snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->id);
719
720 hw = clk_hw_register_divider(dev, clk_name,
721 parent, CLK_SET_RATE_PARENT,
722 pll_7nm->mmio +
723 REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,
724 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
725 if (IS_ERR(hw)) {
726 ret = PTR_ERR(hw);
727 goto err_base_clk_hw;
728 }
729
730 pll_7nm->out_div_clk_hw = hw;
731
732 snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
733 snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
734
735 /* BIT CLK: DIV_CTRL_3_0 */
736 hw = clk_hw_register_divider(dev, clk_name, parent,
737 CLK_SET_RATE_PARENT,
738 pll_7nm->phy_cmn_mmio +
739 REG_DSI_7nm_PHY_CMN_CLK_CFG0,
740 0, 4, CLK_DIVIDER_ONE_BASED,
741 &pll_7nm->postdiv_lock);
742 if (IS_ERR(hw)) {
743 ret = PTR_ERR(hw);
744 goto err_out_div_clk_hw;
745 }
746
747 pll_7nm->bit_clk_hw = hw;
748
749 snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->id);
750 snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
751
752 /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
753 hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
754 CLK_SET_RATE_PARENT, 1, 8);
755 if (IS_ERR(hw)) {
756 ret = PTR_ERR(hw);
757 goto err_bit_clk_hw;
758 }
759
760 pll_7nm->byte_clk_hw = hw;
761 hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
762
763 snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id);
764 snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
765
766 hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
767 0, 1, 2);
768 if (IS_ERR(hw)) {
769 ret = PTR_ERR(hw);
770 goto err_byte_clk_hw;
771 }
772
773 pll_7nm->by_2_bit_clk_hw = hw;
774
775 snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id);
776 snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
777
778 hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
779 0, 1, 4);
780 if (IS_ERR(hw)) {
781 ret = PTR_ERR(hw);
782 goto err_by_2_bit_clk_hw;
783 }
784
785 pll_7nm->post_out_div_clk_hw = hw;
786
787 snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->id);
788 snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
789 snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id);
790 snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
791 snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id);
792
793 hw = clk_hw_register_mux(dev, clk_name,
794 ((const char *[]){
795 parent, parent2, parent3, parent4
796 }), 4, 0, pll_7nm->phy_cmn_mmio +
797 REG_DSI_7nm_PHY_CMN_CLK_CFG1,
798 0, 2, 0, NULL);
799 if (IS_ERR(hw)) {
800 ret = PTR_ERR(hw);
801 goto err_post_out_div_clk_hw;
802 }
803
804 pll_7nm->pclk_mux_hw = hw;
805
806 snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->id);
807 snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->id);
808
809 /* PIX CLK DIV : DIV_CTRL_7_4*/
810 hw = clk_hw_register_divider(dev, clk_name, parent,
811 0, pll_7nm->phy_cmn_mmio +
812 REG_DSI_7nm_PHY_CMN_CLK_CFG0,
813 4, 4, CLK_DIVIDER_ONE_BASED,
814 &pll_7nm->postdiv_lock);
815 if (IS_ERR(hw)) {
816 ret = PTR_ERR(hw);
817 goto err_pclk_mux_hw;
818 }
819
820 pll_7nm->out_dsiclk_hw = hw;
821 hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
822
823 hw_data->num = NUM_PROVIDED_CLKS;
824 pll_7nm->hw_data = hw_data;
825
826 ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
827 pll_7nm->hw_data);
828 if (ret) {
829 DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
830 goto err_dsiclk_hw;
831 }
832
833 return 0;
834
835 err_dsiclk_hw:
836 clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw);
837 err_pclk_mux_hw:
838 clk_hw_unregister_mux(pll_7nm->pclk_mux_hw);
839 err_post_out_div_clk_hw:
840 clk_hw_unregister_fixed_factor(pll_7nm->post_out_div_clk_hw);
841 err_by_2_bit_clk_hw:
842 clk_hw_unregister_fixed_factor(pll_7nm->by_2_bit_clk_hw);
843 err_byte_clk_hw:
844 clk_hw_unregister_fixed_factor(pll_7nm->byte_clk_hw);
845 err_bit_clk_hw:
846 clk_hw_unregister_divider(pll_7nm->bit_clk_hw);
847 err_out_div_clk_hw:
848 clk_hw_unregister_divider(pll_7nm->out_div_clk_hw);
849 err_base_clk_hw:
850 clk_hw_unregister(&pll_7nm->base.clk_hw);
851
852 return ret;
853 }
854
855 struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id)
856 {
857 struct dsi_pll_7nm *pll_7nm;
858 struct msm_dsi_pll *pll;
859 int ret;
860
861 pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL);
862 if (!pll_7nm)
863 return ERR_PTR(-ENOMEM);
864
865 DBG("DSI PLL%d", id);
866
867 pll_7nm->pdev = pdev;
868 pll_7nm->id = id;
869 pll_7nm_list[id] = pll_7nm;
870
871 pll_7nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
872 if (IS_ERR_OR_NULL(pll_7nm->phy_cmn_mmio)) {
873 DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");
874 return ERR_PTR(-ENOMEM);
875 }
876
877 pll_7nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
878 if (IS_ERR_OR_NULL(pll_7nm->mmio)) {
879 DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");
880 return ERR_PTR(-ENOMEM);
881 }
882
883 spin_lock_init(&pll_7nm->postdiv_lock);
884
885 pll = &pll_7nm->base;
886 pll->min_rate = 1000000000UL;
887 pll->max_rate = 3500000000UL;
888 if (pll->type == MSM_DSI_PHY_7NM_V4_1) {
889 pll->min_rate = 600000000UL;
890 pll->max_rate = (unsigned long)5000000000ULL;
891 /* workaround for max rate overflowing on 32-bit builds: */
892 pll->max_rate = max(pll->max_rate, 0xffffffffUL);
893 }
894 pll->get_provider = dsi_pll_7nm_get_provider;
895 pll->destroy = dsi_pll_7nm_destroy;
896 pll->save_state = dsi_pll_7nm_save_state;
897 pll->restore_state = dsi_pll_7nm_restore_state;
898 pll->set_usecase = dsi_pll_7nm_set_usecase;
899
900 pll_7nm->vco_delay = 1;
901
902 ret = pll_7nm_register(pll_7nm);
903 if (ret) {
904 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
905 return ERR_PTR(ret);
906 }
907
908 /* TODO: Remove this when we have proper display handover support */
909 msm_dsi_pll_save_state(pll);
910
911 return pll;
912 }
Linux with added FPC-III support