drivers/gpu/drm/nouveau/dispnv50/base.c

   1 /*
   2  * Copyright 2018 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "base.h"
  23
  24 #include <nvif/class.h>
  25
  26 int
  27 nv50_base_new(struct nouveau_drm *drm, int head, struct nv50_wndw **pwndw)
  28 {
  29         struct {
  30                 s32 oclass;
  31                 int version;
  32                 int (*new)(struct nouveau_drm *, int, s32, struct nv50_wndw **);
  33         } bases[] = {
  34                 { GK110_DISP_BASE_CHANNEL_DMA, 0, base917c_new },
  35                 { GK104_DISP_BASE_CHANNEL_DMA, 0, base917c_new },
  36                 { GF110_DISP_BASE_CHANNEL_DMA, 0, base907c_new },
  37                 { GT214_DISP_BASE_CHANNEL_DMA, 0, base827c_new },
  38                 { GT200_DISP_BASE_CHANNEL_DMA, 0, base827c_new },
  39                 {   G82_DISP_BASE_CHANNEL_DMA, 0, base827c_new },
  40                 {  NV50_DISP_BASE_CHANNEL_DMA, 0, base507c_new },
  41                 {}
  42         };
  43         struct nv50_disp *disp = nv50_disp(drm->dev);
  44         int cid;
  45
  46         cid = nvif_mclass(&disp->disp->object, bases);
  47         if (cid < 0) {
  48                 NV_ERROR(drm, "No supported base class\n");
  49                 return cid;
  50         }
  51
  52         return bases[cid].new(drm, head, bases[cid].oclass, pwndw);
  53 }