drivers/media/dvb-frontends/drxd_firm.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * drxd_firm.h
   4  *
   5  * Copyright (C) 2006-2007 Micronas
   6  */
   7
   8 #ifndef _DRXD_FIRM_H_
   9 #define _DRXD_FIRM_H_
  10
  11 #include <linux/types.h>
  12 #include "drxd_map_firm.h"
  13
  14 #define VERSION_MAJOR 1
  15 #define VERSION_MINOR 4
  16 #define VERSION_PATCH 23
  17
  18 #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
  19
  20 #define DRXD_MAX_RETRIES (1000)
  21 #define HI_I2C_DELAY     84
  22 #define HI_I2C_BRIDGE_DELAY   750
  23
  24 #define EQ_TD_TPS_PWR_UNKNOWN          0x00C0   /* Unknown configurations */
  25 #define EQ_TD_TPS_PWR_QPSK             0x016a
  26 #define EQ_TD_TPS_PWR_QAM16_ALPHAN     0x0195
  27 #define EQ_TD_TPS_PWR_QAM16_ALPHA1     0x0195
  28 #define EQ_TD_TPS_PWR_QAM16_ALPHA2     0x011E
  29 #define EQ_TD_TPS_PWR_QAM16_ALPHA4     0x01CE
  30 #define EQ_TD_TPS_PWR_QAM64_ALPHAN     0x019F
  31 #define EQ_TD_TPS_PWR_QAM64_ALPHA1     0x019F
  32 #define EQ_TD_TPS_PWR_QAM64_ALPHA2     0x00F8
  33 #define EQ_TD_TPS_PWR_QAM64_ALPHA4     0x014D
  34
  35 #define DRXD_DEF_AG_PWD_CONSUMER 0x000E
  36 #define DRXD_DEF_AG_PWD_PRO 0x0000
  37 #define DRXD_DEF_AG_AGC_SIO 0x0000
  38
  39 #define DRXD_FE_CTRL_MAX 1023
  40
  41 #define DRXD_OSCDEV_DO_SCAN  (16)
  42
  43 #define DRXD_OSCDEV_DONT_SCAN  (0)
  44
  45 #define DRXD_OSCDEV_STEP  (275)
  46
  47 #define DRXD_SCAN_TIMEOUT    (650)
  48
  49 #define DRXD_BANDWIDTH_8MHZ_IN_HZ  (0x8B8249L)
  50 #define DRXD_BANDWIDTH_7MHZ_IN_HZ  (0x7A1200L)
  51 #define DRXD_BANDWIDTH_6MHZ_IN_HZ  (0x68A1B6L)
  52
  53 #define IRLEN_COARSE_8K       (10)
  54 #define IRLEN_FINE_8K         (10)
  55 #define IRLEN_COARSE_2K       (7)
  56 #define IRLEN_FINE_2K         (9)
  57 #define DIFF_INVALID          (511)
  58 #define DIFF_TARGET           (4)
  59 #define DIFF_MARGIN           (1)
  60
  61 extern u8 DRXD_InitAtomicRead[];
  62 extern u8 DRXD_HiI2cPatch_1[];
  63 extern u8 DRXD_HiI2cPatch_3[];
  64
  65 extern u8 DRXD_InitSC[];
  66
  67 extern u8 DRXD_ResetCEFR[];
  68 extern u8 DRXD_InitFEA2_1[];
  69 extern u8 DRXD_InitFEA2_2[];
  70 extern u8 DRXD_InitCPA2[];
  71 extern u8 DRXD_InitCEA2[];
  72 extern u8 DRXD_InitEQA2[];
  73 extern u8 DRXD_InitECA2[];
  74 extern u8 DRXD_ResetECA2[];
  75 extern u8 DRXD_ResetECRAM[];
  76
  77 extern u8 DRXD_A2_microcode[];
  78 extern u32 DRXD_A2_microcode_length;
  79
  80 extern u8 DRXD_InitFEB1_1[];
  81 extern u8 DRXD_InitFEB1_2[];
  82 extern u8 DRXD_InitCPB1[];
  83 extern u8 DRXD_InitCEB1[];
  84 extern u8 DRXD_InitEQB1[];
  85 extern u8 DRXD_InitECB1[];
  86
  87 extern u8 DRXD_InitDiversityFront[];
  88 extern u8 DRXD_InitDiversityEnd[];
  89 extern u8 DRXD_DisableDiversity[];
  90 extern u8 DRXD_StartDiversityFront[];
  91 extern u8 DRXD_StartDiversityEnd[];
  92
  93 extern u8 DRXD_DiversityDelay8MHZ[];
  94 extern u8 DRXD_DiversityDelay6MHZ[];
  95
  96 extern u8 DRXD_B1_microcode[];
  97 extern u32 DRXD_B1_microcode_length;
  98
  99 #endif