drivers/media/pci/smipcie/smipcie.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * SMI PCIe driver for DVBSky cards.
   4  *
   5  * Copyright (C) 2014 Max nibble <nibble.max@gmail.com>
   6  */
   7
   8 #ifndef _SMI_PCIE_H_
   9 #define _SMI_PCIE_H_
  10
  11 #include <linux/i2c.h>
  12 #include <linux/i2c-algo-bit.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/pci.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/slab.h>
  20 #include <media/rc-core.h>
  21
  22 #include <media/demux.h>
  23 #include <media/dmxdev.h>
  24 #include <media/dvb_demux.h>
  25 #include <media/dvb_frontend.h>
  26 #include <media/dvb_net.h>
  27 #include <media/dvbdev.h>
  28
  29 /* -------- Register Base -------- */
  30 #define    MSI_CONTROL_REG_BASE                 0x0800
  31 #define    SYSTEM_CONTROL_REG_BASE              0x0880
  32 #define    PCIE_EP_DEBUG_REG_BASE               0x08C0
  33 #define    IR_CONTROL_REG_BASE                  0x0900
  34 #define    I2C_A_CONTROL_REG_BASE               0x0940
  35 #define    I2C_B_CONTROL_REG_BASE               0x0980
  36 #define    ATV_PORTA_CONTROL_REG_BASE           0x09C0
  37 #define    DTV_PORTA_CONTROL_REG_BASE           0x0A00
  38 #define    AES_PORTA_CONTROL_REG_BASE           0x0A80
  39 #define    DMA_PORTA_CONTROL_REG_BASE           0x0AC0
  40 #define    ATV_PORTB_CONTROL_REG_BASE           0x0B00
  41 #define    DTV_PORTB_CONTROL_REG_BASE           0x0B40
  42 #define    AES_PORTB_CONTROL_REG_BASE           0x0BC0
  43 #define    DMA_PORTB_CONTROL_REG_BASE           0x0C00
  44 #define    UART_A_REGISTER_BASE                 0x0C40
  45 #define    UART_B_REGISTER_BASE                 0x0C80
  46 #define    GPS_CONTROL_REG_BASE                 0x0CC0
  47 #define    DMA_PORTC_CONTROL_REG_BASE           0x0D00
  48 #define    DMA_PORTD_CONTROL_REG_BASE           0x0D00
  49 #define    AES_RANDOM_DATA_BASE                 0x0D80
  50 #define    AES_KEY_IN_BASE                      0x0D90
  51 #define    RANDOM_DATA_LIB_BASE                 0x0E00
  52 #define    IR_DATA_BUFFER_BASE                  0x0F00
  53 #define    PORTA_TS_BUFFER_BASE                 0x1000
  54 #define    PORTA_I2S_BUFFER_BASE                0x1400
  55 #define    PORTB_TS_BUFFER_BASE                 0x1800
  56 #define    PORTB_I2S_BUFFER_BASE                0x1C00
  57
  58 /* -------- MSI control and state register -------- */
  59 #define MSI_DELAY_TIMER             (MSI_CONTROL_REG_BASE + 0x00)
  60 #define MSI_INT_STATUS              (MSI_CONTROL_REG_BASE + 0x08)
  61 #define MSI_INT_STATUS_CLR          (MSI_CONTROL_REG_BASE + 0x0C)
  62 #define MSI_INT_STATUS_SET          (MSI_CONTROL_REG_BASE + 0x10)
  63 #define MSI_INT_ENA                 (MSI_CONTROL_REG_BASE + 0x14)
  64 #define MSI_INT_ENA_CLR             (MSI_CONTROL_REG_BASE + 0x18)
  65 #define MSI_INT_ENA_SET             (MSI_CONTROL_REG_BASE + 0x1C)
  66 #define MSI_SOFT_RESET              (MSI_CONTROL_REG_BASE + 0x20)
  67 #define MSI_CFG_SRC0                (MSI_CONTROL_REG_BASE + 0x24)
  68
  69 /* -------- Hybird Controller System Control register -------- */
  70 #define MUX_MODE_CTRL         (SYSTEM_CONTROL_REG_BASE + 0x00)
  71         #define rbPaMSMask        0x07
  72         #define rbPaMSDtvNoGpio   0x00 /*[2:0], DTV Simple mode */
  73         #define rbPaMSDtv4bitGpio 0x01 /*[2:0], DTV TS2 Serial mode)*/
  74         #define rbPaMSDtv7bitGpio 0x02 /*[2:0], DTV TS0 Serial mode*/
  75         #define rbPaMS8bitGpio    0x03 /*[2:0], GPIO mode selected;(8bit GPIO)*/
  76         #define rbPaMSAtv         0x04 /*[2:0], 3'b1xx: ATV mode select*/
  77         #define rbPbMSMask        0x38
  78         #define rbPbMSDtvNoGpio   0x00 /*[5:3], DTV Simple mode */
  79         #define rbPbMSDtv4bitGpio 0x08 /*[5:3], DTV TS2 Serial mode*/
  80         #define rbPbMSDtv7bitGpio 0x10 /*[5:3], DTV TS0 Serial mode*/
  81         #define rbPbMS8bitGpio    0x18 /*[5:3], GPIO mode selected;(8bit GPIO)*/
  82         #define rbPbMSAtv         0x20 /*[5:3], 3'b1xx: ATV mode select*/
  83         #define rbPaAESEN         0x40 /*[6], port A AES enable bit*/
  84         #define rbPbAESEN         0x80 /*[7], port B AES enable bit*/
  85
  86 #define INTERNAL_RST                (SYSTEM_CONTROL_REG_BASE + 0x04)
  87 #define PERIPHERAL_CTRL             (SYSTEM_CONTROL_REG_BASE + 0x08)
  88 #define GPIO_0to7_CTRL              (SYSTEM_CONTROL_REG_BASE + 0x0C)
  89 #define GPIO_8to15_CTRL             (SYSTEM_CONTROL_REG_BASE + 0x10)
  90 #define GPIO_16to24_CTRL            (SYSTEM_CONTROL_REG_BASE + 0x14)
  91 #define GPIO_INT_SRC_CFG            (SYSTEM_CONTROL_REG_BASE + 0x18)
  92 #define SYS_BUF_STATUS              (SYSTEM_CONTROL_REG_BASE + 0x1C)
  93 #define PCIE_IP_REG_ACS             (SYSTEM_CONTROL_REG_BASE + 0x20)
  94 #define PCIE_IP_REG_ACS_ADDR        (SYSTEM_CONTROL_REG_BASE + 0x24)
  95 #define PCIE_IP_REG_ACS_DATA        (SYSTEM_CONTROL_REG_BASE + 0x28)
  96
  97 /* -------- IR Control register -------- */
  98 #define   IR_Init_Reg         (IR_CONTROL_REG_BASE + 0x00)
  99 #define   IR_Idle_Cnt_Low     (IR_CONTROL_REG_BASE + 0x04)
 100 #define   IR_Idle_Cnt_High    (IR_CONTROL_REG_BASE + 0x05)
 101 #define   IR_Unit_Cnt_Low     (IR_CONTROL_REG_BASE + 0x06)
 102 #define   IR_Unit_Cnt_High    (IR_CONTROL_REG_BASE + 0x07)
 103 #define   IR_Data_Cnt         (IR_CONTROL_REG_BASE + 0x08)
 104 #define   rbIRen            0x80
 105 #define   rbIRhighidle      0x10
 106 #define   rbIRlowidle       0x00
 107 #define   rbIRVld           0x04
 108
 109 /* -------- I2C A control and state register -------- */
 110 #define I2C_A_CTL_STATUS                 (I2C_A_CONTROL_REG_BASE + 0x00)
 111 #define I2C_A_ADDR                       (I2C_A_CONTROL_REG_BASE + 0x04)
 112 #define I2C_A_SW_CTL                     (I2C_A_CONTROL_REG_BASE + 0x08)
 113 #define I2C_A_TIME_OUT_CNT               (I2C_A_CONTROL_REG_BASE + 0x0C)
 114 #define I2C_A_FIFO_STATUS                (I2C_A_CONTROL_REG_BASE + 0x10)
 115 #define I2C_A_FS_EN                      (I2C_A_CONTROL_REG_BASE + 0x14)
 116 #define I2C_A_FIFO_DATA                  (I2C_A_CONTROL_REG_BASE + 0x20)
 117
 118 /* -------- I2C B control and state register -------- */
 119 #define I2C_B_CTL_STATUS                 (I2C_B_CONTROL_REG_BASE + 0x00)
 120 #define I2C_B_ADDR                       (I2C_B_CONTROL_REG_BASE + 0x04)
 121 #define I2C_B_SW_CTL                     (I2C_B_CONTROL_REG_BASE + 0x08)
 122 #define I2C_B_TIME_OUT_CNT               (I2C_B_CONTROL_REG_BASE + 0x0C)
 123 #define I2C_B_FIFO_STATUS                (I2C_B_CONTROL_REG_BASE + 0x10)
 124 #define I2C_B_FS_EN                      (I2C_B_CONTROL_REG_BASE + 0x14)
 125 #define I2C_B_FIFO_DATA                  (I2C_B_CONTROL_REG_BASE + 0x20)
 126
 127 #define VIDEO_CTRL_STATUS_A     (ATV_PORTA_CONTROL_REG_BASE + 0x04)
 128
 129 /* -------- Digital TV control register, Port A -------- */
 130 #define MPEG2_CTRL_A            (DTV_PORTA_CONTROL_REG_BASE + 0x00)
 131 #define SERIAL_IN_ADDR_A        (DTV_PORTA_CONTROL_REG_BASE + 0x4C)
 132 #define VLD_CNT_ADDR_A          (DTV_PORTA_CONTROL_REG_BASE + 0x60)
 133 #define ERR_CNT_ADDR_A          (DTV_PORTA_CONTROL_REG_BASE + 0x64)
 134 #define BRD_CNT_ADDR_A          (DTV_PORTA_CONTROL_REG_BASE + 0x68)
 135
 136 /* -------- DMA Control Register, Port A  -------- */
 137 #define DMA_PORTA_CHAN0_ADDR_LOW        (DMA_PORTA_CONTROL_REG_BASE + 0x00)
 138 #define DMA_PORTA_CHAN0_ADDR_HI         (DMA_PORTA_CONTROL_REG_BASE + 0x04)
 139 #define DMA_PORTA_CHAN0_TRANS_STATE     (DMA_PORTA_CONTROL_REG_BASE + 0x08)
 140 #define DMA_PORTA_CHAN0_CONTROL         (DMA_PORTA_CONTROL_REG_BASE + 0x0C)
 141 #define DMA_PORTA_CHAN1_ADDR_LOW        (DMA_PORTA_CONTROL_REG_BASE + 0x10)
 142 #define DMA_PORTA_CHAN1_ADDR_HI         (DMA_PORTA_CONTROL_REG_BASE + 0x14)
 143 #define DMA_PORTA_CHAN1_TRANS_STATE     (DMA_PORTA_CONTROL_REG_BASE + 0x18)
 144 #define DMA_PORTA_CHAN1_CONTROL         (DMA_PORTA_CONTROL_REG_BASE + 0x1C)
 145 #define DMA_PORTA_MANAGEMENT            (DMA_PORTA_CONTROL_REG_BASE + 0x20)
 146 #define VIDEO_CTRL_STATUS_B             (ATV_PORTB_CONTROL_REG_BASE + 0x04)
 147
 148 /* -------- Digital TV control register, Port B -------- */
 149 #define MPEG2_CTRL_B            (DTV_PORTB_CONTROL_REG_BASE + 0x00)
 150 #define SERIAL_IN_ADDR_B        (DTV_PORTB_CONTROL_REG_BASE + 0x4C)
 151 #define VLD_CNT_ADDR_B          (DTV_PORTB_CONTROL_REG_BASE + 0x60)
 152 #define ERR_CNT_ADDR_B          (DTV_PORTB_CONTROL_REG_BASE + 0x64)
 153 #define BRD_CNT_ADDR_B          (DTV_PORTB_CONTROL_REG_BASE + 0x68)
 154
 155 /* -------- AES control register, Port B -------- */
 156 #define AES_CTRL_B              (AES_PORTB_CONTROL_REG_BASE + 0x00)
 157 #define AES_KEY_BASE_B  (AES_PORTB_CONTROL_REG_BASE + 0x04)
 158
 159 /* -------- DMA Control Register, Port B  -------- */
 160 #define DMA_PORTB_CHAN0_ADDR_LOW        (DMA_PORTB_CONTROL_REG_BASE + 0x00)
 161 #define DMA_PORTB_CHAN0_ADDR_HI         (DMA_PORTB_CONTROL_REG_BASE + 0x04)
 162 #define DMA_PORTB_CHAN0_TRANS_STATE     (DMA_PORTB_CONTROL_REG_BASE + 0x08)
 163 #define DMA_PORTB_CHAN0_CONTROL         (DMA_PORTB_CONTROL_REG_BASE + 0x0C)
 164 #define DMA_PORTB_CHAN1_ADDR_LOW        (DMA_PORTB_CONTROL_REG_BASE + 0x10)
 165 #define DMA_PORTB_CHAN1_ADDR_HI         (DMA_PORTB_CONTROL_REG_BASE + 0x14)
 166 #define DMA_PORTB_CHAN1_TRANS_STATE     (DMA_PORTB_CONTROL_REG_BASE + 0x18)
 167 #define DMA_PORTB_CHAN1_CONTROL         (DMA_PORTB_CONTROL_REG_BASE + 0x1C)
 168 #define DMA_PORTB_MANAGEMENT            (DMA_PORTB_CONTROL_REG_BASE + 0x20)
 169
 170 #define DMA_TRANS_UNIT_188 (0x00000007)
 171
 172 /* -------- Macro define of 24 interrupt resource --------*/
 173 #define DMA_A_CHAN0_DONE_INT   (0x00000001)
 174 #define DMA_A_CHAN1_DONE_INT   (0x00000002)
 175 #define DMA_B_CHAN0_DONE_INT   (0x00000004)
 176 #define DMA_B_CHAN1_DONE_INT   (0x00000008)
 177 #define DMA_C_CHAN0_DONE_INT   (0x00000010)
 178 #define DMA_C_CHAN1_DONE_INT   (0x00000020)
 179 #define DMA_D_CHAN0_DONE_INT   (0x00000040)
 180 #define DMA_D_CHAN1_DONE_INT   (0x00000080)
 181 #define DATA_BUF_OVERFLOW_INT  (0x00000100)
 182 #define UART_0_X_INT           (0x00000200)
 183 #define UART_1_X_INT           (0x00000400)
 184 #define IR_X_INT               (0x00000800)
 185 #define GPIO_0_INT             (0x00001000)
 186 #define GPIO_1_INT             (0x00002000)
 187 #define GPIO_2_INT             (0x00004000)
 188 #define GPIO_3_INT             (0x00008000)
 189 #define ALL_INT                (0x0000FFFF)
 190
 191 /* software I2C bit mask */
 192 #define SW_I2C_MSK_MODE         0x01
 193 #define SW_I2C_MSK_CLK_OUT      0x02
 194 #define SW_I2C_MSK_DAT_OUT      0x04
 195 #define SW_I2C_MSK_CLK_EN       0x08
 196 #define SW_I2C_MSK_DAT_EN       0x10
 197 #define SW_I2C_MSK_DAT_IN       0x40
 198 #define SW_I2C_MSK_CLK_IN       0x80
 199
 200 #define SMI_VID         0x1ADE
 201 #define SMI_PID         0x3038
 202 #define SMI_TS_DMA_BUF_SIZE     (1024 * 188)
 203
 204 struct smi_cfg_info {
 205 #define SMI_DVBSKY_S952         0
 206 #define SMI_DVBSKY_S950         1
 207 #define SMI_DVBSKY_T9580        2
 208 #define SMI_DVBSKY_T982         3
 209 #define SMI_TECHNOTREND_S2_4200 4
 210         int type;
 211         char *name;
 212 #define SMI_TS_NULL             0
 213 #define SMI_TS_DMA_SINGLE       1
 214 #define SMI_TS_DMA_BOTH         3
 215 /* SMI_TS_NULL: not use;
 216  * SMI_TS_DMA_SINGLE: use DMA 0 only;
 217  * SMI_TS_DMA_BOTH:use DMA 0 and 1.*/
 218         int ts_0;
 219         int ts_1;
 220 #define DVBSKY_FE_NULL          0
 221 #define DVBSKY_FE_M88RS6000     1
 222 #define DVBSKY_FE_M88DS3103     2
 223 #define DVBSKY_FE_SIT2          3
 224         int fe_0;
 225         int fe_1;
 226         char *rc_map;
 227 };
 228
 229 struct smi_rc {
 230         struct smi_dev *dev;
 231         struct rc_dev *rc_dev;
 232         char input_phys[64];
 233         char device_name[64];
 234         u8 irData[256];
 235
 236         int users;
 237 };
 238
 239 struct smi_port {
 240         struct smi_dev *dev;
 241         int idx;
 242         int enable;
 243         int fe_type;
 244         /* regs */
 245         u32 DMA_CHAN0_ADDR_LOW;
 246         u32 DMA_CHAN0_ADDR_HI;
 247         u32 DMA_CHAN0_TRANS_STATE;
 248         u32 DMA_CHAN0_CONTROL;
 249         u32 DMA_CHAN1_ADDR_LOW;
 250         u32 DMA_CHAN1_ADDR_HI;
 251         u32 DMA_CHAN1_TRANS_STATE;
 252         u32 DMA_CHAN1_CONTROL;
 253         u32 DMA_MANAGEMENT;
 254         /* dma */
 255         dma_addr_t dma_addr[2];
 256         u8 *cpu_addr[2];
 257         u32 _dmaInterruptCH0;
 258         u32 _dmaInterruptCH1;
 259         u32 _int_status;
 260         struct tasklet_struct tasklet;
 261         /* dvb */
 262         struct dmx_frontend hw_frontend;
 263         struct dmx_frontend mem_frontend;
 264         struct dmxdev dmxdev;
 265         struct dvb_adapter dvb_adapter;
 266         struct dvb_demux demux;
 267         struct dvb_net dvbnet;
 268         int users;
 269         struct dvb_frontend *fe;
 270         /* frontend i2c module */
 271         struct i2c_client *i2c_client_demod;
 272         struct i2c_client *i2c_client_tuner;
 273 };
 274
 275 struct smi_dev {
 276         int nr;
 277         struct smi_cfg_info *info;
 278
 279         /* pcie */
 280         struct pci_dev *pci_dev;
 281         u32 __iomem *lmmio;
 282
 283         /* ts port */
 284         struct smi_port ts_port[2];
 285
 286         /* i2c */
 287         struct i2c_adapter i2c_bus[2];
 288         struct i2c_algo_bit_data i2c_bit[2];
 289
 290         /* ir */
 291         struct smi_rc ir;
 292 };
 293
 294 #define smi_read(reg)             readl(dev->lmmio + ((reg)>>2))
 295 #define smi_write(reg, value)     writel((value), dev->lmmio + ((reg)>>2))
 296
 297 #define smi_andor(reg, mask, value) \
 298         writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
 299         ((value) & (mask)), dev->lmmio+((reg)>>2))
 300
 301 #define smi_set(reg, bit)          smi_andor((reg), (bit), (bit))
 302 #define smi_clear(reg, bit)        smi_andor((reg), (bit), 0)
 303
 304 int smi_ir_irq(struct smi_rc *ir, u32 int_status);
 305 void smi_ir_start(struct smi_rc *ir);
 306 void smi_ir_exit(struct smi_dev *dev);
 307 int smi_ir_init(struct smi_dev *dev);
 308
 309 #endif /* #ifndef _SMI_PCIE_H_ */