1 // SPDX-License-Identifier: GPL-2.0-only
4 * MTD driver for the 28F160F3 Flash Memory (non-CFI) on LART.
6 * Author: Abraham vd Merwe <abraham@2d3d.co.za>
8 * Copyright (c) 2001, 2d3D, Inc.
12 * [1] 3 Volt Fast Boot Block Flash Memory" Intel Datasheet
13 * - Order Number: 290644-005
16 * [2] MTD internal API documentation
17 * - http://www.linux-mtd.infradead.org/
21 * Even though this driver is written for 3 Volt Fast Boot
22 * Block Flash Memory, it is rather specific to LART. With
23 * Minor modifications, notably the without data/address line
24 * mangling and different bus settings, etc. it should be
25 * trivial to adapt to other platforms.
27 * If somebody would sponsor me a different board, I'll
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/types.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/string.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/partitions.h>
43 #ifndef CONFIG_SA1100_LART
44 #error This is for LART architecture only
47 static char module_name
[] = "lart";
50 * These values is specific to 28Fxxxx3 flash memory.
51 * See section 2.3.1 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
53 #define FLASH_BLOCKSIZE_PARAM (4096 * BUSWIDTH)
54 #define FLASH_NUMBLOCKS_16m_PARAM 8
55 #define FLASH_NUMBLOCKS_8m_PARAM 8
58 * These values is specific to 28Fxxxx3 flash memory.
59 * See section 2.3.2 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
61 #define FLASH_BLOCKSIZE_MAIN (32768 * BUSWIDTH)
62 #define FLASH_NUMBLOCKS_16m_MAIN 31
63 #define FLASH_NUMBLOCKS_8m_MAIN 15
66 * These values are specific to LART
70 #define BUSWIDTH 4 /* don't change this - a lot of the code _will_ break if you change this */
71 #define FLASH_OFFSET 0xe8000000 /* see linux/arch/arm/mach-sa1100/lart.c */
74 #define NUM_BLOB_BLOCKS FLASH_NUMBLOCKS_16m_PARAM
75 #define PART_BLOB_START 0x00000000
76 #define PART_BLOB_LEN (NUM_BLOB_BLOCKS * FLASH_BLOCKSIZE_PARAM)
79 #define NUM_KERNEL_BLOCKS 7
80 #define PART_KERNEL_START (PART_BLOB_START + PART_BLOB_LEN)
81 #define PART_KERNEL_LEN (NUM_KERNEL_BLOCKS * FLASH_BLOCKSIZE_MAIN)
84 #define NUM_INITRD_BLOCKS 24
85 #define PART_INITRD_START (PART_KERNEL_START + PART_KERNEL_LEN)
86 #define PART_INITRD_LEN (NUM_INITRD_BLOCKS * FLASH_BLOCKSIZE_MAIN)
89 * See section 4.0 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
91 #define READ_ARRAY 0x00FF00FF /* Read Array/Reset */
92 #define READ_ID_CODES 0x00900090 /* Read Identifier Codes */
93 #define ERASE_SETUP 0x00200020 /* Block Erase */
94 #define ERASE_CONFIRM 0x00D000D0 /* Block Erase and Program Resume */
95 #define PGM_SETUP 0x00400040 /* Program */
96 #define STATUS_READ 0x00700070 /* Read Status Register */
97 #define STATUS_CLEAR 0x00500050 /* Clear Status Register */
98 #define STATUS_BUSY 0x00800080 /* Write State Machine Status (WSMS) */
99 #define STATUS_ERASE_ERR 0x00200020 /* Erase Status (ES) */
100 #define STATUS_PGM_ERR 0x00100010 /* Program Status (PS) */
103 * See section 4.2 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
105 #define FLASH_MANUFACTURER 0x00890089
106 #define FLASH_DEVICE_8mbit_TOP 0x88f188f1
107 #define FLASH_DEVICE_8mbit_BOTTOM 0x88f288f2
108 #define FLASH_DEVICE_16mbit_TOP 0x88f388f3
109 #define FLASH_DEVICE_16mbit_BOTTOM 0x88f488f4
111 /***************************************************************************************************/
114 * The data line mapping on LART is as follows:
117 * -------------------
136 /* Mangle data (x) */
137 #define DATA_TO_FLASH(x) \
139 (((x) & 0x08009000) >> 11) + \
140 (((x) & 0x00002000) >> 10) + \
141 (((x) & 0x04004000) >> 8) + \
142 (((x) & 0x00000010) >> 4) + \
143 (((x) & 0x91000820) >> 3) + \
144 (((x) & 0x22080080) >> 2) + \
145 ((x) & 0x40000400) + \
146 (((x) & 0x00040040) << 1) + \
147 (((x) & 0x00110000) << 4) + \
148 (((x) & 0x00220100) << 5) + \
149 (((x) & 0x00800208) << 6) + \
150 (((x) & 0x00400004) << 9) + \
151 (((x) & 0x00000001) << 12) + \
152 (((x) & 0x00000002) << 13) \
155 /* Unmangle data (x) */
156 #define FLASH_TO_DATA(x) \
158 (((x) & 0x00010012) << 11) + \
159 (((x) & 0x00000008) << 10) + \
160 (((x) & 0x00040040) << 8) + \
161 (((x) & 0x00000001) << 4) + \
162 (((x) & 0x12200104) << 3) + \
163 (((x) & 0x08820020) << 2) + \
164 ((x) & 0x40000400) + \
165 (((x) & 0x00080080) >> 1) + \
166 (((x) & 0x01100000) >> 4) + \
167 (((x) & 0x04402000) >> 5) + \
168 (((x) & 0x20008200) >> 6) + \
169 (((x) & 0x80000800) >> 9) + \
170 (((x) & 0x00001000) >> 12) + \
171 (((x) & 0x00004000) >> 13) \
175 * The address line mapping on LART is as follows:
178 * -------------------
192 * BOOT BLOCK BOUNDARY
198 * MAIN BLOCK BOUNDARY
206 * As we can see from above, the addresses aren't mangled across
207 * block boundaries, so we don't need to worry about address
208 * translations except for sending/reading commands during
212 /* Mangle address (x) on chip U2 */
213 #define ADDR_TO_FLASH_U2(x) \
215 (((x) & 0x00000f00) >> 4) + \
216 (((x) & 0x00042000) << 1) + \
217 (((x) & 0x0009c003) << 2) + \
218 (((x) & 0x00021080) << 3) + \
219 (((x) & 0x00000010) << 4) + \
220 (((x) & 0x00000040) << 5) + \
221 (((x) & 0x00000024) << 7) + \
222 (((x) & 0x00000008) << 10) \
225 /* Unmangle address (x) on chip U2 */
226 #define FLASH_U2_TO_ADDR(x) \
228 (((x) << 4) & 0x00000f00) + \
229 (((x) >> 1) & 0x00042000) + \
230 (((x) >> 2) & 0x0009c003) + \
231 (((x) >> 3) & 0x00021080) + \
232 (((x) >> 4) & 0x00000010) + \
233 (((x) >> 5) & 0x00000040) + \
234 (((x) >> 7) & 0x00000024) + \
235 (((x) >> 10) & 0x00000008) \
238 /* Mangle address (x) on chip U3 */
239 #define ADDR_TO_FLASH_U3(x) \
241 (((x) & 0x00000080) >> 3) + \
242 (((x) & 0x00000040) >> 1) + \
243 (((x) & 0x00052020) << 1) + \
244 (((x) & 0x00084f03) << 2) + \
245 (((x) & 0x00029010) << 3) + \
246 (((x) & 0x00000008) << 5) + \
247 (((x) & 0x00000004) << 7) \
250 /* Unmangle address (x) on chip U3 */
251 #define FLASH_U3_TO_ADDR(x) \
253 (((x) << 3) & 0x00000080) + \
254 (((x) << 1) & 0x00000040) + \
255 (((x) >> 1) & 0x00052020) + \
256 (((x) >> 2) & 0x00084f03) + \
257 (((x) >> 3) & 0x00029010) + \
258 (((x) >> 5) & 0x00000008) + \
259 (((x) >> 7) & 0x00000004) \
262 /***************************************************************************************************/
264 static __u8
read8 (__u32 offset
)
266 volatile __u8
*data
= (__u8
*) (FLASH_OFFSET
+ offset
);
268 printk (KERN_DEBUG
"%s(): 0x%.8x -> 0x%.2x\n", __func__
, offset
, *data
);
273 static __u32
read32 (__u32 offset
)
275 volatile __u32
*data
= (__u32
*) (FLASH_OFFSET
+ offset
);
277 printk (KERN_DEBUG
"%s(): 0x%.8x -> 0x%.8x\n", __func__
, offset
, *data
);
282 static void write32 (__u32 x
,__u32 offset
)
284 volatile __u32
*data
= (__u32
*) (FLASH_OFFSET
+ offset
);
287 printk (KERN_DEBUG
"%s(): 0x%.8x <- 0x%.8x\n", __func__
, offset
, *data
);
291 /***************************************************************************************************/
294 * Probe for 16mbit flash memory on a LART board without doing
295 * too much damage. Since we need to write 1 dword to memory,
296 * we're f**cked if this happens to be DRAM since we can't
297 * restore the memory (otherwise we might exit Read Array mode).
299 * Returns 1 if we found 16mbit flash memory on LART, 0 otherwise.
301 static int flash_probe (void)
303 __u32 manufacturer
,devtype
;
305 /* setup "Read Identifier Codes" mode */
306 write32 (DATA_TO_FLASH (READ_ID_CODES
),0x00000000);
308 /* probe U2. U2/U3 returns the same data since the first 3
309 * address lines is mangled in the same way */
310 manufacturer
= FLASH_TO_DATA (read32 (ADDR_TO_FLASH_U2 (0x00000000)));
311 devtype
= FLASH_TO_DATA (read32 (ADDR_TO_FLASH_U2 (0x00000001)));
313 /* put the flash back into command mode */
314 write32 (DATA_TO_FLASH (READ_ARRAY
),0x00000000);
316 return (manufacturer
== FLASH_MANUFACTURER
&& (devtype
== FLASH_DEVICE_16mbit_TOP
|| devtype
== FLASH_DEVICE_16mbit_BOTTOM
));
320 * Erase one block of flash memory at offset ``offset'' which is any
321 * address within the block which should be erased.
323 * Returns 1 if successful, 0 otherwise.
325 static inline int erase_block (__u32 offset
)
330 printk (KERN_DEBUG
"%s(): 0x%.8x\n", __func__
, offset
);
333 /* erase and confirm */
334 write32 (DATA_TO_FLASH (ERASE_SETUP
),offset
);
335 write32 (DATA_TO_FLASH (ERASE_CONFIRM
),offset
);
337 /* wait for block erase to finish */
340 write32 (DATA_TO_FLASH (STATUS_READ
),offset
);
341 status
= FLASH_TO_DATA (read32 (offset
));
343 while ((~status
& STATUS_BUSY
) != 0);
345 /* put the flash back into command mode */
346 write32 (DATA_TO_FLASH (READ_ARRAY
),offset
);
348 /* was the erase successful? */
349 if ((status
& STATUS_ERASE_ERR
))
351 printk (KERN_WARNING
"%s: erase error at address 0x%.8x.\n",module_name
,offset
);
358 static int flash_erase (struct mtd_info
*mtd
,struct erase_info
*instr
)
364 printk (KERN_DEBUG
"%s(addr = 0x%.8x, len = %d)\n", __func__
, instr
->addr
, instr
->len
);
368 * check that both start and end of the requested erase are
369 * aligned with the erasesize at the appropriate addresses.
371 * skip all erase regions which are ended before the start of
372 * the requested erase. Actually, to save on the calculations,
373 * we skip to the first erase region which starts after the
374 * start of the requested erase, and then go back one.
376 for (i
= 0; i
< mtd
->numeraseregions
&& instr
->addr
>= mtd
->eraseregions
[i
].offset
; i
++) ;
380 * ok, now i is pointing at the erase region in which this
381 * erase request starts. Check the start of the requested
382 * erase range is aligned with the erase size which is in
385 if (i
< 0 || (instr
->addr
& (mtd
->eraseregions
[i
].erasesize
- 1)))
388 /* Remember the erase region we start on */
392 * next, check that the end of the requested erase is aligned
393 * with the erase region at that address.
395 * as before, drop back one to point at the region in which
396 * the address actually falls
398 for (; i
< mtd
->numeraseregions
&& instr
->addr
+ instr
->len
>= mtd
->eraseregions
[i
].offset
; i
++) ;
401 /* is the end aligned on a block boundary? */
402 if (i
< 0 || ((instr
->addr
+ instr
->len
) & (mtd
->eraseregions
[i
].erasesize
- 1)))
410 /* now erase those blocks */
413 if (!erase_block (addr
))
416 addr
+= mtd
->eraseregions
[i
].erasesize
;
417 len
-= mtd
->eraseregions
[i
].erasesize
;
419 if (addr
== mtd
->eraseregions
[i
].offset
+ (mtd
->eraseregions
[i
].erasesize
* mtd
->eraseregions
[i
].numblocks
)) i
++;
425 static int flash_read (struct mtd_info
*mtd
,loff_t from
,size_t len
,size_t *retlen
,u_char
*buf
)
428 printk (KERN_DEBUG
"%s(from = 0x%.8x, len = %d)\n", __func__
, (__u32
)from
, len
);
431 /* we always read len bytes */
434 /* first, we read bytes until we reach a dword boundary */
435 if (from
& (BUSWIDTH
- 1))
437 int gap
= BUSWIDTH
- (from
& (BUSWIDTH
- 1));
439 while (len
&& gap
--) {
440 *buf
++ = read8 (from
++);
445 /* now we read dwords until we reach a non-dword boundary */
446 while (len
>= BUSWIDTH
)
448 *((__u32
*) buf
) = read32 (from
);
455 /* top up the last unaligned bytes */
456 if (len
& (BUSWIDTH
- 1))
457 while (len
--) *buf
++ = read8 (from
++);
463 * Write one dword ``x'' to flash memory at offset ``offset''. ``offset''
464 * must be 32 bits, i.e. it must be on a dword boundary.
466 * Returns 1 if successful, 0 otherwise.
468 static inline int write_dword (__u32 offset
,__u32 x
)
473 printk (KERN_DEBUG
"%s(): 0x%.8x <- 0x%.8x\n", __func__
, offset
, x
);
477 write32 (DATA_TO_FLASH (PGM_SETUP
),offset
);
482 /* wait for the write to finish */
485 write32 (DATA_TO_FLASH (STATUS_READ
),offset
);
486 status
= FLASH_TO_DATA (read32 (offset
));
488 while ((~status
& STATUS_BUSY
) != 0);
490 /* put the flash back into command mode */
491 write32 (DATA_TO_FLASH (READ_ARRAY
),offset
);
493 /* was the write successful? */
494 if ((status
& STATUS_PGM_ERR
) || read32 (offset
) != x
)
496 printk (KERN_WARNING
"%s: write error at address 0x%.8x.\n",module_name
,offset
);
503 static int flash_write (struct mtd_info
*mtd
,loff_t to
,size_t len
,size_t *retlen
,const u_char
*buf
)
509 printk (KERN_DEBUG
"%s(to = 0x%.8x, len = %d)\n", __func__
, (__u32
)to
, len
);
513 if (!len
) return (0);
515 /* first, we write a 0xFF.... padded byte until we reach a dword boundary */
516 if (to
& (BUSWIDTH
- 1))
518 __u32 aligned
= to
& ~(BUSWIDTH
- 1);
519 int gap
= to
- aligned
;
523 while (gap
--) tmp
[i
++] = 0xFF;
524 while (len
&& i
< BUSWIDTH
) {
528 while (i
< BUSWIDTH
) tmp
[i
++] = 0xFF;
530 if (!write_dword (aligned
,*((__u32
*) tmp
))) return (-EIO
);
537 /* now we write dwords until we reach a non-dword boundary */
538 while (len
>= BUSWIDTH
)
540 if (!write_dword (to
,*((__u32
*) buf
))) return (-EIO
);
548 /* top up the last unaligned bytes, padded with 0xFF.... */
549 if (len
& (BUSWIDTH
- 1))
553 while (len
--) tmp
[i
++] = buf
[n
++];
554 while (i
< BUSWIDTH
) tmp
[i
++] = 0xFF;
556 if (!write_dword (to
,*((__u32
*) tmp
))) return (-EIO
);
564 /***************************************************************************************************/
566 static struct mtd_info mtd
;
568 static struct mtd_erase_region_info erase_regions
[] = {
569 /* parameter blocks */
571 .offset
= 0x00000000,
572 .erasesize
= FLASH_BLOCKSIZE_PARAM
,
573 .numblocks
= FLASH_NUMBLOCKS_16m_PARAM
,
577 .offset
= FLASH_BLOCKSIZE_PARAM
* FLASH_NUMBLOCKS_16m_PARAM
,
578 .erasesize
= FLASH_BLOCKSIZE_MAIN
,
579 .numblocks
= FLASH_NUMBLOCKS_16m_MAIN
,
583 static const struct mtd_partition lart_partitions
[] = {
587 .offset
= PART_BLOB_START
,
588 .size
= PART_BLOB_LEN
,
593 .offset
= PART_KERNEL_START
, /* MTDPART_OFS_APPEND */
594 .size
= PART_KERNEL_LEN
,
596 /* initial ramdisk / file system */
598 .name
= "file system",
599 .offset
= PART_INITRD_START
, /* MTDPART_OFS_APPEND */
600 .size
= PART_INITRD_LEN
, /* MTDPART_SIZ_FULL */
603 #define NUM_PARTITIONS ARRAY_SIZE(lart_partitions)
605 static int __init
lart_flash_init (void)
608 memset (&mtd
,0,sizeof (mtd
));
609 printk ("MTD driver for LART. Written by Abraham vd Merwe <abraham@2d3d.co.za>\n");
610 printk ("%s: Probing for 28F160x3 flash on LART...\n",module_name
);
613 printk (KERN_WARNING
"%s: Found no LART compatible flash device\n",module_name
);
616 printk ("%s: This looks like a LART board to me.\n",module_name
);
617 mtd
.name
= module_name
;
618 mtd
.type
= MTD_NORFLASH
;
620 mtd
.writebufsize
= 4;
621 mtd
.flags
= MTD_CAP_NORFLASH
;
622 mtd
.size
= FLASH_BLOCKSIZE_PARAM
* FLASH_NUMBLOCKS_16m_PARAM
+ FLASH_BLOCKSIZE_MAIN
* FLASH_NUMBLOCKS_16m_MAIN
;
623 mtd
.erasesize
= FLASH_BLOCKSIZE_MAIN
;
624 mtd
.numeraseregions
= ARRAY_SIZE(erase_regions
);
625 mtd
.eraseregions
= erase_regions
;
626 mtd
._erase
= flash_erase
;
627 mtd
._read
= flash_read
;
628 mtd
._write
= flash_write
;
629 mtd
.owner
= THIS_MODULE
;
634 "mtd.size = 0x%.8x (%uM)\n"
635 "mtd.erasesize = 0x%.8x (%uK)\n"
636 "mtd.numeraseregions = %d\n",
638 mtd
.size
,mtd
.size
/ (1024*1024),
639 mtd
.erasesize
,mtd
.erasesize
/ 1024,
640 mtd
.numeraseregions
);
642 if (mtd
.numeraseregions
)
643 for (result
= 0; result
< mtd
.numeraseregions
; result
++)
646 "mtd.eraseregions[%d].offset = 0x%.8x\n"
647 "mtd.eraseregions[%d].erasesize = 0x%.8x (%uK)\n"
648 "mtd.eraseregions[%d].numblocks = %d\n",
649 result
,mtd
.eraseregions
[result
].offset
,
650 result
,mtd
.eraseregions
[result
].erasesize
,mtd
.eraseregions
[result
].erasesize
/ 1024,
651 result
,mtd
.eraseregions
[result
].numblocks
);
653 printk ("\npartitions = %d\n", ARRAY_SIZE(lart_partitions
));
655 for (result
= 0; result
< ARRAY_SIZE(lart_partitions
); result
++)
658 "lart_partitions[%d].name = %s\n"
659 "lart_partitions[%d].offset = 0x%.8x\n"
660 "lart_partitions[%d].size = 0x%.8x (%uK)\n",
661 result
,lart_partitions
[result
].name
,
662 result
,lart_partitions
[result
].offset
,
663 result
,lart_partitions
[result
].size
,lart_partitions
[result
].size
/ 1024);
666 result
= mtd_device_register(&mtd
, lart_partitions
,
667 ARRAY_SIZE(lart_partitions
));
672 static void __exit
lart_flash_exit (void)
674 mtd_device_unregister(&mtd
);
677 module_init (lart_flash_init
);
678 module_exit (lart_flash_exit
);
680 MODULE_LICENSE("GPL");
681 MODULE_AUTHOR("Abraham vd Merwe <abraham@2d3d.co.za>");
682 MODULE_DESCRIPTION("MTD driver for Intel 28F160F3 on LART board");