1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2015 Broadcom Corporation
9 #include <linux/types.h>
12 struct platform_device
;
16 bool (*ctlrdy_ack
)(struct brcmnand_soc
*soc
);
17 void (*ctlrdy_set_enabled
)(struct brcmnand_soc
*soc
, bool en
);
18 void (*prepare_data_bus
)(struct brcmnand_soc
*soc
, bool prepare
,
22 static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc
*soc
,
25 if (soc
&& soc
->prepare_data_bus
)
26 soc
->prepare_data_bus(soc
, true, is_param
);
29 static inline void brcmnand_soc_data_bus_unprepare(struct brcmnand_soc
*soc
,
32 if (soc
&& soc
->prepare_data_bus
)
33 soc
->prepare_data_bus(soc
, false, is_param
);
36 static inline u32
brcmnand_readl(void __iomem
*addr
)
39 * MIPS endianness is configured by boot strap, which also reverses all
40 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
43 * Other architectures (e.g., ARM) either do not support big endian, or
44 * else leave I/O in little endian mode.
46 if (IS_ENABLED(CONFIG_MIPS
) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN
))
47 return __raw_readl(addr
);
49 return readl_relaxed(addr
);
52 static inline void brcmnand_writel(u32 val
, void __iomem
*addr
)
54 /* See brcmnand_readl() comments */
55 if (IS_ENABLED(CONFIG_MIPS
) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN
))
56 __raw_writel(val
, addr
);
58 writel_relaxed(val
, addr
);
61 int brcmnand_probe(struct platform_device
*pdev
, struct brcmnand_soc
*soc
);
62 int brcmnand_remove(struct platform_device
*pdev
);
64 extern const struct dev_pm_ops brcmnand_pm_ops
;
66 #endif /* __BRCMNAND_H__ */