drivers/mtd/nand/raw/oxnas_nand.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Oxford Semiconductor OXNAS NAND driver
   4
   5  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
   6  * Heavily based on plat_nand.c :
   7  * Author: Vitaly Wool <vitalywool@gmail.com>
   8  * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
   9  * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
  10  */
  11
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/slab.h>
  17 #include <linux/clk.h>
  18 #include <linux/reset.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/rawnand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/of.h>
  23
  24 /* Nand commands */
  25 #define OXNAS_NAND_CMD_ALE              BIT(18)
  26 #define OXNAS_NAND_CMD_CLE              BIT(19)
  27
  28 #define OXNAS_NAND_MAX_CHIPS    1
  29
  30 struct oxnas_nand_ctrl {
  31         struct nand_controller base;
  32         void __iomem *io_base;
  33         struct clk *clk;
  34         struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS];
  35         unsigned int nchips;
  36 };
  37
  38 static uint8_t oxnas_nand_read_byte(struct nand_chip *chip)
  39 {
  40         struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
  41
  42         return readb(oxnas->io_base);
  43 }
  44
  45 static void oxnas_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
  46 {
  47         struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
  48
  49         ioread8_rep(oxnas->io_base, buf, len);
  50 }
  51
  52 static void oxnas_nand_write_buf(struct nand_chip *chip, const u8 *buf,
  53                                  int len)
  54 {
  55         struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
  56
  57         iowrite8_rep(oxnas->io_base, buf, len);
  58 }
  59
  60 /* Single CS command control */
  61 static void oxnas_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
  62                                 unsigned int ctrl)
  63 {
  64         struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
  65
  66         if (ctrl & NAND_CLE)
  67                 writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_CLE);
  68         else if (ctrl & NAND_ALE)
  69                 writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_ALE);
  70 }
  71
  72 /*
  73  * Probe for the NAND device.
  74  */
  75 static int oxnas_nand_probe(struct platform_device *pdev)
  76 {
  77         struct device_node *np = pdev->dev.of_node;
  78         struct device_node *nand_np;
  79         struct oxnas_nand_ctrl *oxnas;
  80         struct nand_chip *chip;
  81         struct mtd_info *mtd;
  82         struct resource *res;
  83         int count = 0;
  84         int err = 0;
  85         int i;
  86
  87         /* Allocate memory for the device structure (and zero it) */
  88         oxnas = devm_kzalloc(&pdev->dev, sizeof(*oxnas),
  89                              GFP_KERNEL);
  90         if (!oxnas)
  91                 return -ENOMEM;
  92
  93         nand_controller_init(&oxnas->base);
  94
  95         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  96         oxnas->io_base = devm_ioremap_resource(&pdev->dev, res);
  97         if (IS_ERR(oxnas->io_base))
  98                 return PTR_ERR(oxnas->io_base);
  99
 100         oxnas->clk = devm_clk_get(&pdev->dev, NULL);
 101         if (IS_ERR(oxnas->clk))
 102                 oxnas->clk = NULL;
 103
 104         /* Only a single chip node is supported */
 105         count = of_get_child_count(np);
 106         if (count > 1)
 107                 return -EINVAL;
 108
 109         err = clk_prepare_enable(oxnas->clk);
 110         if (err)
 111                 return err;
 112
 113         device_reset_optional(&pdev->dev);
 114
 115         for_each_child_of_node(np, nand_np) {
 116                 chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
 117                                     GFP_KERNEL);
 118                 if (!chip) {
 119                         err = -ENOMEM;
 120                         goto err_release_child;
 121                 }
 122
 123                 chip->controller = &oxnas->base;
 124
 125                 nand_set_flash_node(chip, nand_np);
 126                 nand_set_controller_data(chip, oxnas);
 127
 128                 mtd = nand_to_mtd(chip);
 129                 mtd->dev.parent = &pdev->dev;
 130                 mtd->priv = chip;
 131
 132                 chip->legacy.cmd_ctrl = oxnas_nand_cmd_ctrl;
 133                 chip->legacy.read_buf = oxnas_nand_read_buf;
 134                 chip->legacy.read_byte = oxnas_nand_read_byte;
 135                 chip->legacy.write_buf = oxnas_nand_write_buf;
 136                 chip->legacy.chip_delay = 30;
 137
 138                 /* Scan to find existence of the device */
 139                 err = nand_scan(chip, 1);
 140                 if (err)
 141                         goto err_release_child;
 142
 143                 err = mtd_device_register(mtd, NULL, 0);
 144                 if (err)
 145                         goto err_cleanup_nand;
 146
 147                 oxnas->chips[oxnas->nchips++] = chip;
 148         }
 149
 150         /* Exit if no chips found */
 151         if (!oxnas->nchips) {
 152                 err = -ENODEV;
 153                 goto err_clk_unprepare;
 154         }
 155
 156         platform_set_drvdata(pdev, oxnas);
 157
 158         return 0;
 159
 160 err_cleanup_nand:
 161         nand_cleanup(chip);
 162 err_release_child:
 163         of_node_put(nand_np);
 164
 165         for (i = 0; i < oxnas->nchips; i++) {
 166                 chip = oxnas->chips[i];
 167                 WARN_ON(mtd_device_unregister(nand_to_mtd(chip)));
 168                 nand_cleanup(chip);
 169         }
 170
 171 err_clk_unprepare:
 172         clk_disable_unprepare(oxnas->clk);
 173         return err;
 174 }
 175
 176 static int oxnas_nand_remove(struct platform_device *pdev)
 177 {
 178         struct oxnas_nand_ctrl *oxnas = platform_get_drvdata(pdev);
 179         struct nand_chip *chip;
 180         int i;
 181
 182         for (i = 0; i < oxnas->nchips; i++) {
 183                 chip = oxnas->chips[i];
 184                 WARN_ON(mtd_device_unregister(nand_to_mtd(chip)));
 185                 nand_cleanup(chip);
 186         }
 187
 188         clk_disable_unprepare(oxnas->clk);
 189
 190         return 0;
 191 }
 192
 193 static const struct of_device_id oxnas_nand_match[] = {
 194         { .compatible = "oxsemi,ox820-nand" },
 195         {},
 196 };
 197 MODULE_DEVICE_TABLE(of, oxnas_nand_match);
 198
 199 static struct platform_driver oxnas_nand_driver = {
 200         .probe  = oxnas_nand_probe,
 201         .remove = oxnas_nand_remove,
 202         .driver = {
 203                 .name           = "oxnas_nand",
 204                 .of_match_table = oxnas_nand_match,
 205         },
 206 };
 207
 208 module_platform_driver(oxnas_nand_driver);
 209
 210 MODULE_LICENSE("GPL");
 211 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
 212 MODULE_DESCRIPTION("Oxnas NAND driver");
 213 MODULE_ALIAS("platform:oxnas_nand");