2 * Au1xxx counter0 (aka Time-Of-Year counter) RTC interface driver.
4 * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
11 /* All current Au1xxx SoCs have 2 counters fed by an external 32.768 kHz
12 * crystal. Counter 0, which keeps counting during sleep/powerdown, is
13 * used to count seconds since the beginning of the unix epoch.
15 * The counters must be configured and enabled by bootloader/board code;
16 * no checks as to whether they really get a proper 32.768kHz clock are
17 * made as this would take far too long.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/rtc.h>
23 #include <linux/init.h>
24 #include <linux/platform_device.h>
26 #include <asm/mach-au1x00/au1000.h>
28 /* 32kHz clock enabled and detected */
29 #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
31 static int au1xtoy_rtc_read_time(struct device
*dev
, struct rtc_time
*tm
)
35 t
= alchemy_rdsys(AU1000_SYS_TOYREAD
);
37 rtc_time64_to_tm(t
, tm
);
42 static int au1xtoy_rtc_set_time(struct device
*dev
, struct rtc_time
*tm
)
46 t
= rtc_tm_to_time64(tm
);
48 alchemy_wrsys(t
, AU1000_SYS_TOYWRITE
);
50 /* wait for the pending register write to succeed. This can
51 * take up to 6 seconds...
53 while (alchemy_rdsys(AU1000_SYS_CNTRCTRL
) & SYS_CNTRL_C0S
)
59 static const struct rtc_class_ops au1xtoy_rtc_ops
= {
60 .read_time
= au1xtoy_rtc_read_time
,
61 .set_time
= au1xtoy_rtc_set_time
,
64 static int au1xtoy_rtc_probe(struct platform_device
*pdev
)
66 struct rtc_device
*rtcdev
;
69 t
= alchemy_rdsys(AU1000_SYS_CNTRCTRL
);
71 dev_err(&pdev
->dev
, "counters not working; aborting.\n");
75 /* set counter0 tickrate to 1Hz if necessary */
76 if (alchemy_rdsys(AU1000_SYS_TOYTRIM
) != 32767) {
77 /* wait until hardware gives access to TRIM register */
79 while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL
) & SYS_CNTRL_T0S
) && --t
)
83 /* timed out waiting for register access; assume
84 * counters are unusable.
86 dev_err(&pdev
->dev
, "timeout waiting for access\n");
90 /* set 1Hz TOY tick rate */
91 alchemy_wrsys(32767, AU1000_SYS_TOYTRIM
);
94 /* wait until the hardware allows writes to the counter reg */
95 while (alchemy_rdsys(AU1000_SYS_CNTRCTRL
) & SYS_CNTRL_C0S
)
98 rtcdev
= devm_rtc_allocate_device(&pdev
->dev
);
100 return PTR_ERR(rtcdev
);
102 rtcdev
->ops
= &au1xtoy_rtc_ops
;
103 rtcdev
->range_max
= U32_MAX
;
105 platform_set_drvdata(pdev
, rtcdev
);
107 return devm_rtc_register_device(rtcdev
);
110 static struct platform_driver au1xrtc_driver
= {
112 .name
= "rtc-au1xxx",
116 module_platform_driver_probe(au1xrtc_driver
, au1xtoy_rtc_probe
);
118 MODULE_DESCRIPTION("Au1xxx TOY-counter-based RTC driver");
119 MODULE_AUTHOR("Manuel Lauss <manuel.lauss@gmail.com>");
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:rtc-au1xxx");