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Merge tag 'io_uring-5.11-2021-01-16' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / rtc / rtc-ds1307.c
blob183cf7c01364cb8726444771d81a3cdf1aa1cdd0
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
4 *
5 * Copyright (C) 2005 James Chapman (ds1337 core)
6 * Copyright (C) 2006 David Brownell
7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
9 */
10
11 #include <linux/bcd.h>
12 #include <linux/i2c.h>
13 #include <linux/init.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/module.h>
16 #include <linux/property.h>
17 #include <linux/rtc/ds1307.h>
18 #include <linux/rtc.h>
19 #include <linux/slab.h>
20 #include <linux/string.h>
21 #include <linux/hwmon.h>
22 #include <linux/hwmon-sysfs.h>
23 #include <linux/clk-provider.h>
24 #include <linux/regmap.h>
25 #include <linux/watchdog.h>
26
27 /*
28 * We can't determine type by probing, but if we expect pre-Linux code
29 * to have set the chip up as a clock (turning on the oscillator and
30 * setting the date and time), Linux can ignore the non-clock features.
31 * That's a natural job for a factory or repair bench.
32 */
33 enum ds_type {
34 unknown_ds_type, /* always first and 0 */
35 ds_1307,
36 ds_1308,
37 ds_1337,
38 ds_1338,
39 ds_1339,
40 ds_1340,
41 ds_1341,
42 ds_1388,
43 ds_3231,
44 m41t0,
45 m41t00,
46 m41t11,
47 mcp794xx,
48 rx_8025,
49 rx_8130,
50 last_ds_type /* always last */
51 /* rs5c372 too? different address... */
52 };
53
54 /* RTC registers don't differ much, except for the century flag */
55 #define DS1307_REG_SECS 0x00 /* 00-59 */
56 # define DS1307_BIT_CH 0x80
57 # define DS1340_BIT_nEOSC 0x80
58 # define MCP794XX_BIT_ST 0x80
59 #define DS1307_REG_MIN 0x01 /* 00-59 */
60 # define M41T0_BIT_OF 0x80
61 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
62 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
63 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
64 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
65 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
66 #define DS1307_REG_WDAY 0x03 /* 01-07 */
67 # define MCP794XX_BIT_VBATEN 0x08
68 #define DS1307_REG_MDAY 0x04 /* 01-31 */
69 #define DS1307_REG_MONTH 0x05 /* 01-12 */
70 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
71 #define DS1307_REG_YEAR 0x06 /* 00-99 */
72
73 /*
74 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
75 * start at 7, and they differ a LOT. Only control and status matter for
76 * basic RTC date and time functionality; be careful using them.
77 */
78 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
79 # define DS1307_BIT_OUT 0x80
80 # define DS1338_BIT_OSF 0x20
81 # define DS1307_BIT_SQWE 0x10
82 # define DS1307_BIT_RS1 0x02
83 # define DS1307_BIT_RS0 0x01
84 #define DS1337_REG_CONTROL 0x0e
85 # define DS1337_BIT_nEOSC 0x80
86 # define DS1339_BIT_BBSQI 0x20
87 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
88 # define DS1337_BIT_RS2 0x10
89 # define DS1337_BIT_RS1 0x08
90 # define DS1337_BIT_INTCN 0x04
91 # define DS1337_BIT_A2IE 0x02
92 # define DS1337_BIT_A1IE 0x01
93 #define DS1340_REG_CONTROL 0x07
94 # define DS1340_BIT_OUT 0x80
95 # define DS1340_BIT_FT 0x40
96 # define DS1340_BIT_CALIB_SIGN 0x20
97 # define DS1340_M_CALIBRATION 0x1f
98 #define DS1340_REG_FLAG 0x09
99 # define DS1340_BIT_OSF 0x80
100 #define DS1337_REG_STATUS 0x0f
101 # define DS1337_BIT_OSF 0x80
102 # define DS3231_BIT_EN32KHZ 0x08
103 # define DS1337_BIT_A2I 0x02
104 # define DS1337_BIT_A1I 0x01
105 #define DS1339_REG_ALARM1_SECS 0x07
106
107 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
108
109 #define RX8025_REG_CTRL1 0x0e
110 # define RX8025_BIT_2412 0x20
111 #define RX8025_REG_CTRL2 0x0f
112 # define RX8025_BIT_PON 0x10
113 # define RX8025_BIT_VDET 0x40
114 # define RX8025_BIT_XST 0x20
115
116 #define RX8130_REG_ALARM_MIN 0x17
117 #define RX8130_REG_ALARM_HOUR 0x18
118 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
119 #define RX8130_REG_EXTENSION 0x1c
120 #define RX8130_REG_EXTENSION_WADA BIT(3)
121 #define RX8130_REG_FLAG 0x1d
122 #define RX8130_REG_FLAG_VLF BIT(1)
123 #define RX8130_REG_FLAG_AF BIT(3)
124 #define RX8130_REG_CONTROL0 0x1e
125 #define RX8130_REG_CONTROL0_AIE BIT(3)
126 #define RX8130_REG_CONTROL1 0x1f
127 #define RX8130_REG_CONTROL1_INIEN BIT(4)
128 #define RX8130_REG_CONTROL1_CHGEN BIT(5)
129
130 #define MCP794XX_REG_CONTROL 0x07
131 # define MCP794XX_BIT_ALM0_EN 0x10
132 # define MCP794XX_BIT_ALM1_EN 0x20
133 #define MCP794XX_REG_ALARM0_BASE 0x0a
134 #define MCP794XX_REG_ALARM0_CTRL 0x0d
135 #define MCP794XX_REG_ALARM1_BASE 0x11
136 #define MCP794XX_REG_ALARM1_CTRL 0x14
137 # define MCP794XX_BIT_ALMX_IF BIT(3)
138 # define MCP794XX_BIT_ALMX_C0 BIT(4)
139 # define MCP794XX_BIT_ALMX_C1 BIT(5)
140 # define MCP794XX_BIT_ALMX_C2 BIT(6)
141 # define MCP794XX_BIT_ALMX_POL BIT(7)
142 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
143 MCP794XX_BIT_ALMX_C1 | \
144 MCP794XX_BIT_ALMX_C2)
145
146 #define M41TXX_REG_CONTROL 0x07
147 # define M41TXX_BIT_OUT BIT(7)
148 # define M41TXX_BIT_FT BIT(6)
149 # define M41TXX_BIT_CALIB_SIGN BIT(5)
150 # define M41TXX_M_CALIBRATION GENMASK(4, 0)
151
152 #define DS1388_REG_WDOG_HUN_SECS 0x08
153 #define DS1388_REG_WDOG_SECS 0x09
154 #define DS1388_REG_FLAG 0x0b
155 # define DS1388_BIT_WF BIT(6)
156 # define DS1388_BIT_OSF BIT(7)
157 #define DS1388_REG_CONTROL 0x0c
158 # define DS1388_BIT_RST BIT(0)
159 # define DS1388_BIT_WDE BIT(1)
160 # define DS1388_BIT_nEOSC BIT(7)
161
162 /* negative offset step is -2.034ppm */
163 #define M41TXX_NEG_OFFSET_STEP_PPB 2034
164 /* positive offset step is +4.068ppm */
165 #define M41TXX_POS_OFFSET_STEP_PPB 4068
166 /* Min and max values supported with 'offset' interface by M41TXX */
167 #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
168 #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
169
170 struct ds1307 {
171 enum ds_type type;
172 unsigned long flags;
173 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
174 #define HAS_ALARM 1 /* bit 1 == irq claimed */
175 struct device *dev;
176 struct regmap *regmap;
177 const char *name;
178 struct rtc_device *rtc;
179 #ifdef CONFIG_COMMON_CLK
180 struct clk_hw clks[2];
181 #endif
182 };
183
184 struct chip_desc {
185 unsigned alarm:1;
186 u16 nvram_offset;
187 u16 nvram_size;
188 u8 offset; /* register's offset */
189 u8 century_reg;
190 u8 century_enable_bit;
191 u8 century_bit;
192 u8 bbsqi_bit;
193 irq_handler_t irq_handler;
194 const struct rtc_class_ops *rtc_ops;
195 u16 trickle_charger_reg;
196 u8 (*do_trickle_setup)(struct ds1307 *, u32,
197 bool);
198 /* Does the RTC require trickle-resistor-ohms to select the value of
199 * the resistor between Vcc and Vbackup?
200 */
201 bool requires_trickle_resistor;
202 /* Some RTC's batteries and supercaps were charged by default, others
203 * allow charging but were not configured previously to do so.
204 * Remember this behavior to stay backwards compatible.
205 */
206 bool charge_default;
207 };
208
209 static const struct chip_desc chips[last_ds_type];
210
211 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
212 {
213 struct ds1307 *ds1307 = dev_get_drvdata(dev);
214 int tmp, ret;
215 const struct chip_desc *chip = &chips[ds1307->type];
216 u8 regs[7];
217
218 if (ds1307->type == rx_8130) {
219 unsigned int regflag;
220 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);
221 if (ret) {
222 dev_err(dev, "%s error %d\n", "read", ret);
223 return ret;
224 }
225
226 if (regflag & RX8130_REG_FLAG_VLF) {
227 dev_warn_once(dev, "oscillator failed, set time!\n");
228 return -EINVAL;
229 }
230 }
231
232 /* read the RTC date and time registers all at once */
233 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
234 sizeof(regs));
235 if (ret) {
236 dev_err(dev, "%s error %d\n", "read", ret);
237 return ret;
238 }
239
240 dev_dbg(dev, "%s: %7ph\n", "read", regs);
241
242 /* if oscillator fail bit is set, no data can be trusted */
243 if (ds1307->type == m41t0 &&
244 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
245 dev_warn_once(dev, "oscillator failed, set time!\n");
246 return -EINVAL;
247 }
248
249 tmp = regs[DS1307_REG_SECS];
250 switch (ds1307->type) {
251 case ds_1307:
252 case m41t0:
253 case m41t00:
254 case m41t11:
255 if (tmp & DS1307_BIT_CH)
256 return -EINVAL;
257 break;
258 case ds_1308:
259 case ds_1338:
260 if (tmp & DS1307_BIT_CH)
261 return -EINVAL;
262
263 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
264 if (ret)
265 return ret;
266 if (tmp & DS1338_BIT_OSF)
267 return -EINVAL;
268 break;
269 case ds_1340:
270 if (tmp & DS1340_BIT_nEOSC)
271 return -EINVAL;
272
273 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
274 if (ret)
275 return ret;
276 if (tmp & DS1340_BIT_OSF)
277 return -EINVAL;
278 break;
279 case ds_1388:
280 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
281 if (ret)
282 return ret;
283 if (tmp & DS1388_BIT_OSF)
284 return -EINVAL;
285 break;
286 case mcp794xx:
287 if (!(tmp & MCP794XX_BIT_ST))
288 return -EINVAL;
289
290 break;
291 default:
292 break;
293 }
294
295 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
296 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
297 tmp = regs[DS1307_REG_HOUR] & 0x3f;
298 t->tm_hour = bcd2bin(tmp);
299 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
300 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
301 tmp = regs[DS1307_REG_MONTH] & 0x1f;
302 t->tm_mon = bcd2bin(tmp) - 1;
303 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
304
305 if (regs[chip->century_reg] & chip->century_bit &&
306 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
307 t->tm_year += 100;
308
309 dev_dbg(dev, "%s secs=%d, mins=%d, "
310 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
311 "read", t->tm_sec, t->tm_min,
312 t->tm_hour, t->tm_mday,
313 t->tm_mon, t->tm_year, t->tm_wday);
314
315 return 0;
316 }
317
318 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
319 {
320 struct ds1307 *ds1307 = dev_get_drvdata(dev);
321 const struct chip_desc *chip = &chips[ds1307->type];
322 int result;
323 int tmp;
324 u8 regs[7];
325
326 dev_dbg(dev, "%s secs=%d, mins=%d, "
327 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
328 "write", t->tm_sec, t->tm_min,
329 t->tm_hour, t->tm_mday,
330 t->tm_mon, t->tm_year, t->tm_wday);
331
332 if (t->tm_year < 100)
333 return -EINVAL;
334
335 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
336 if (t->tm_year > (chip->century_bit ? 299 : 199))
337 return -EINVAL;
338 #else
339 if (t->tm_year > 199)
340 return -EINVAL;
341 #endif
342
343 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
344 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
345 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
346 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
347 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
348 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
349
350 /* assume 20YY not 19YY */
351 tmp = t->tm_year - 100;
352 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
353
354 if (chip->century_enable_bit)
355 regs[chip->century_reg] |= chip->century_enable_bit;
356 if (t->tm_year > 199 && chip->century_bit)
357 regs[chip->century_reg] |= chip->century_bit;
358
359 switch (ds1307->type) {
360 case ds_1308:
361 case ds_1338:
362 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
363 DS1338_BIT_OSF, 0);
364 break;
365 case ds_1340:
366 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
367 DS1340_BIT_OSF, 0);
368 break;
369 case ds_1388:
370 regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
371 DS1388_BIT_OSF, 0);
372 break;
373 case mcp794xx:
374 /*
375 * these bits were cleared when preparing the date/time
376 * values and need to be set again before writing the
377 * regsfer out to the device.
378 */
379 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
380 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
381 break;
382 default:
383 break;
384 }
385
386 dev_dbg(dev, "%s: %7ph\n", "write", regs);
387
388 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
389 sizeof(regs));
390 if (result) {
391 dev_err(dev, "%s error %d\n", "write", result);
392 return result;
393 }
394
395 if (ds1307->type == rx_8130) {
396 /* clear Voltage Loss Flag as data is available now */
397 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
398 ~(u8)RX8130_REG_FLAG_VLF);
399 if (result) {
400 dev_err(dev, "%s error %d\n", "write", result);
401 return result;
402 }
403 }
404
405 return 0;
406 }
407
408 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
409 {
410 struct ds1307 *ds1307 = dev_get_drvdata(dev);
411 int ret;
412 u8 regs[9];
413
414 if (!test_bit(HAS_ALARM, &ds1307->flags))
415 return -EINVAL;
416
417 /* read all ALARM1, ALARM2, and status registers at once */
418 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
419 regs, sizeof(regs));
420 if (ret) {
421 dev_err(dev, "%s error %d\n", "alarm read", ret);
422 return ret;
423 }
424
425 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
426 &regs[0], &regs[4], &regs[7]);
427
428 /*
429 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
430 * and that all four fields are checked matches
431 */
432 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
433 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
434 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
435 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
436
437 /* ... and status */
438 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
439 t->pending = !!(regs[8] & DS1337_BIT_A1I);
440
441 dev_dbg(dev, "%s secs=%d, mins=%d, "
442 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
443 "alarm read", t->time.tm_sec, t->time.tm_min,
444 t->time.tm_hour, t->time.tm_mday,
445 t->enabled, t->pending);
446
447 return 0;
448 }
449
450 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
451 {
452 struct ds1307 *ds1307 = dev_get_drvdata(dev);
453 unsigned char regs[9];
454 u8 control, status;
455 int ret;
456
457 if (!test_bit(HAS_ALARM, &ds1307->flags))
458 return -EINVAL;
459
460 dev_dbg(dev, "%s secs=%d, mins=%d, "
461 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
462 "alarm set", t->time.tm_sec, t->time.tm_min,
463 t->time.tm_hour, t->time.tm_mday,
464 t->enabled, t->pending);
465
466 /* read current status of both alarms and the chip */
467 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
468 sizeof(regs));
469 if (ret) {
470 dev_err(dev, "%s error %d\n", "alarm write", ret);
471 return ret;
472 }
473 control = regs[7];
474 status = regs[8];
475
476 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
477 &regs[0], &regs[4], control, status);
478
479 /* set ALARM1, using 24 hour and day-of-month modes */
480 regs[0] = bin2bcd(t->time.tm_sec);
481 regs[1] = bin2bcd(t->time.tm_min);
482 regs[2] = bin2bcd(t->time.tm_hour);
483 regs[3] = bin2bcd(t->time.tm_mday);
484
485 /* set ALARM2 to non-garbage */
486 regs[4] = 0;
487 regs[5] = 0;
488 regs[6] = 0;
489
490 /* disable alarms */
491 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
492 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
493
494 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
495 sizeof(regs));
496 if (ret) {
497 dev_err(dev, "can't set alarm time\n");
498 return ret;
499 }
500
501 /* optionally enable ALARM1 */
502 if (t->enabled) {
503 dev_dbg(dev, "alarm IRQ armed\n");
504 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
505 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
506 }
507
508 return 0;
509 }
510
511 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
512 {
513 struct ds1307 *ds1307 = dev_get_drvdata(dev);
514
515 if (!test_bit(HAS_ALARM, &ds1307->flags))
516 return -ENOTTY;
517
518 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
519 DS1337_BIT_A1IE,
520 enabled ? DS1337_BIT_A1IE : 0);
521 }
522
523 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
524 {
525 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
526 DS1307_TRICKLE_CHARGER_NO_DIODE;
527
528 setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
529
530 switch (ohms) {
531 case 250:
532 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
533 break;
534 case 2000:
535 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
536 break;
537 case 4000:
538 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
539 break;
540 default:
541 dev_warn(ds1307->dev,
542 "Unsupported ohm value %u in dt\n", ohms);
543 return 0;
544 }
545 return setup;
546 }
547
548 static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode)
549 {
550 /* make sure that the backup battery is enabled */
551 u8 setup = RX8130_REG_CONTROL1_INIEN;
552 if (diode)
553 setup |= RX8130_REG_CONTROL1_CHGEN;
554
555 return setup;
556 }
557
558 static irqreturn_t rx8130_irq(int irq, void *dev_id)
559 {
560 struct ds1307 *ds1307 = dev_id;
561 struct mutex *lock = &ds1307->rtc->ops_lock;
562 u8 ctl[3];
563 int ret;
564
565 mutex_lock(lock);
566
567 /* Read control registers. */
568 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
569 sizeof(ctl));
570 if (ret < 0)
571 goto out;
572 if (!(ctl[1] & RX8130_REG_FLAG_AF))
573 goto out;
574 ctl[1] &= ~RX8130_REG_FLAG_AF;
575 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
576
577 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
578 sizeof(ctl));
579 if (ret < 0)
580 goto out;
581
582 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
583
584 out:
585 mutex_unlock(lock);
586
587 return IRQ_HANDLED;
588 }
589
590 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
591 {
592 struct ds1307 *ds1307 = dev_get_drvdata(dev);
593 u8 ald[3], ctl[3];
594 int ret;
595
596 if (!test_bit(HAS_ALARM, &ds1307->flags))
597 return -EINVAL;
598
599 /* Read alarm registers. */
600 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
601 sizeof(ald));
602 if (ret < 0)
603 return ret;
604
605 /* Read control registers. */
606 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
607 sizeof(ctl));
608 if (ret < 0)
609 return ret;
610
611 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
612 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
613
614 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
615 t->time.tm_sec = -1;
616 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
617 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
618 t->time.tm_wday = -1;
619 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
620 t->time.tm_mon = -1;
621 t->time.tm_year = -1;
622 t->time.tm_yday = -1;
623 t->time.tm_isdst = -1;
624
625 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
626 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
627 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
628
629 return 0;
630 }
631
632 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
633 {
634 struct ds1307 *ds1307 = dev_get_drvdata(dev);
635 u8 ald[3], ctl[3];
636 int ret;
637
638 if (!test_bit(HAS_ALARM, &ds1307->flags))
639 return -EINVAL;
640
641 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
642 "enabled=%d pending=%d\n", __func__,
643 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
644 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
645 t->enabled, t->pending);
646
647 /* Read control registers. */
648 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
649 sizeof(ctl));
650 if (ret < 0)
651 return ret;
652
653 ctl[0] &= RX8130_REG_EXTENSION_WADA;
654 ctl[1] &= ~RX8130_REG_FLAG_AF;
655 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
656
657 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
658 sizeof(ctl));
659 if (ret < 0)
660 return ret;
661
662 /* Hardware alarm precision is 1 minute! */
663 ald[0] = bin2bcd(t->time.tm_min);
664 ald[1] = bin2bcd(t->time.tm_hour);
665 ald[2] = bin2bcd(t->time.tm_mday);
666
667 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
668 sizeof(ald));
669 if (ret < 0)
670 return ret;
671
672 if (!t->enabled)
673 return 0;
674
675 ctl[2] |= RX8130_REG_CONTROL0_AIE;
676
677 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
678 }
679
680 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
681 {
682 struct ds1307 *ds1307 = dev_get_drvdata(dev);
683 int ret, reg;
684
685 if (!test_bit(HAS_ALARM, &ds1307->flags))
686 return -EINVAL;
687
688 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
689 if (ret < 0)
690 return ret;
691
692 if (enabled)
693 reg |= RX8130_REG_CONTROL0_AIE;
694 else
695 reg &= ~RX8130_REG_CONTROL0_AIE;
696
697 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
698 }
699
700 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
701 {
702 struct ds1307 *ds1307 = dev_id;
703 struct mutex *lock = &ds1307->rtc->ops_lock;
704 int reg, ret;
705
706 mutex_lock(lock);
707
708 /* Check and clear alarm 0 interrupt flag. */
709 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
710 if (ret)
711 goto out;
712 if (!(reg & MCP794XX_BIT_ALMX_IF))
713 goto out;
714 reg &= ~MCP794XX_BIT_ALMX_IF;
715 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
716 if (ret)
717 goto out;
718
719 /* Disable alarm 0. */
720 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
721 MCP794XX_BIT_ALM0_EN, 0);
722 if (ret)
723 goto out;
724
725 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
726
727 out:
728 mutex_unlock(lock);
729
730 return IRQ_HANDLED;
731 }
732
733 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
734 {
735 struct ds1307 *ds1307 = dev_get_drvdata(dev);
736 u8 regs[10];
737 int ret;
738
739 if (!test_bit(HAS_ALARM, &ds1307->flags))
740 return -EINVAL;
741
742 /* Read control and alarm 0 registers. */
743 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
744 sizeof(regs));
745 if (ret)
746 return ret;
747
748 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
749
750 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
751 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
752 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
753 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
754 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
755 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
756 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
757 t->time.tm_year = -1;
758 t->time.tm_yday = -1;
759 t->time.tm_isdst = -1;
760
761 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
762 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
763 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
764 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
765 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
766 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
767 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
768
769 return 0;
770 }
771
772 /*
773 * We may have a random RTC weekday, therefore calculate alarm weekday based
774 * on current weekday we read from the RTC timekeeping regs
775 */
776 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
777 {
778 struct rtc_time tm_now;
779 int days_now, days_alarm, ret;
780
781 ret = ds1307_get_time(dev, &tm_now);
782 if (ret)
783 return ret;
784
785 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
786 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
787
788 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
789 }
790
791 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
792 {
793 struct ds1307 *ds1307 = dev_get_drvdata(dev);
794 unsigned char regs[10];
795 int wday, ret;
796
797 if (!test_bit(HAS_ALARM, &ds1307->flags))
798 return -EINVAL;
799
800 wday = mcp794xx_alm_weekday(dev, &t->time);
801 if (wday < 0)
802 return wday;
803
804 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
805 "enabled=%d pending=%d\n", __func__,
806 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
807 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
808 t->enabled, t->pending);
809
810 /* Read control and alarm 0 registers. */
811 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
812 sizeof(regs));
813 if (ret)
814 return ret;
815
816 /* Set alarm 0, using 24-hour and day-of-month modes. */
817 regs[3] = bin2bcd(t->time.tm_sec);
818 regs[4] = bin2bcd(t->time.tm_min);
819 regs[5] = bin2bcd(t->time.tm_hour);
820 regs[6] = wday;
821 regs[7] = bin2bcd(t->time.tm_mday);
822 regs[8] = bin2bcd(t->time.tm_mon + 1);
823
824 /* Clear the alarm 0 interrupt flag. */
825 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
826 /* Set alarm match: second, minute, hour, day, date, month. */
827 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
828 /* Disable interrupt. We will not enable until completely programmed */
829 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
830
831 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
832 sizeof(regs));
833 if (ret)
834 return ret;
835
836 if (!t->enabled)
837 return 0;
838 regs[0] |= MCP794XX_BIT_ALM0_EN;
839 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
840 }
841
842 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
843 {
844 struct ds1307 *ds1307 = dev_get_drvdata(dev);
845
846 if (!test_bit(HAS_ALARM, &ds1307->flags))
847 return -EINVAL;
848
849 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
850 MCP794XX_BIT_ALM0_EN,
851 enabled ? MCP794XX_BIT_ALM0_EN : 0);
852 }
853
854 static int m41txx_rtc_read_offset(struct device *dev, long *offset)
855 {
856 struct ds1307 *ds1307 = dev_get_drvdata(dev);
857 unsigned int ctrl_reg;
858 u8 val;
859
860 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
861
862 val = ctrl_reg & M41TXX_M_CALIBRATION;
863
864 /* check if positive */
865 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
866 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
867 else
868 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
869
870 return 0;
871 }
872
873 static int m41txx_rtc_set_offset(struct device *dev, long offset)
874 {
875 struct ds1307 *ds1307 = dev_get_drvdata(dev);
876 unsigned int ctrl_reg;
877
878 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
879 return -ERANGE;
880
881 if (offset >= 0) {
882 ctrl_reg = DIV_ROUND_CLOSEST(offset,
883 M41TXX_POS_OFFSET_STEP_PPB);
884 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
885 } else {
886 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
887 M41TXX_NEG_OFFSET_STEP_PPB);
888 }
889
890 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
891 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
892 ctrl_reg);
893 }
894
895 #ifdef CONFIG_WATCHDOG_CORE
896 static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
897 {
898 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
899 u8 regs[2];
900 int ret;
901
902 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
903 DS1388_BIT_WF, 0);
904 if (ret)
905 return ret;
906
907 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
908 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
909 if (ret)
910 return ret;
911
912 /*
913 * watchdog timeouts are measured in seconds. So ignore hundredths of
914 * seconds field.
915 */
916 regs[0] = 0;
917 regs[1] = bin2bcd(wdt_dev->timeout);
918
919 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
920 sizeof(regs));
921 if (ret)
922 return ret;
923
924 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
925 DS1388_BIT_WDE | DS1388_BIT_RST,
926 DS1388_BIT_WDE | DS1388_BIT_RST);
927 }
928
929 static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
930 {
931 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
932
933 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
934 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
935 }
936
937 static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
938 {
939 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
940 u8 regs[2];
941
942 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
943 sizeof(regs));
944 }
945
946 static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
947 unsigned int val)
948 {
949 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
950 u8 regs[2];
951
952 wdt_dev->timeout = val;
953 regs[0] = 0;
954 regs[1] = bin2bcd(wdt_dev->timeout);
955
956 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
957 sizeof(regs));
958 }
959 #endif
960
961 static const struct rtc_class_ops rx8130_rtc_ops = {
962 .read_time = ds1307_get_time,
963 .set_time = ds1307_set_time,
964 .read_alarm = rx8130_read_alarm,
965 .set_alarm = rx8130_set_alarm,
966 .alarm_irq_enable = rx8130_alarm_irq_enable,
967 };
968
969 static const struct rtc_class_ops mcp794xx_rtc_ops = {
970 .read_time = ds1307_get_time,
971 .set_time = ds1307_set_time,
972 .read_alarm = mcp794xx_read_alarm,
973 .set_alarm = mcp794xx_set_alarm,
974 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
975 };
976
977 static const struct rtc_class_ops m41txx_rtc_ops = {
978 .read_time = ds1307_get_time,
979 .set_time = ds1307_set_time,
980 .read_alarm = ds1337_read_alarm,
981 .set_alarm = ds1337_set_alarm,
982 .alarm_irq_enable = ds1307_alarm_irq_enable,
983 .read_offset = m41txx_rtc_read_offset,
984 .set_offset = m41txx_rtc_set_offset,
985 };
986
987 static const struct chip_desc chips[last_ds_type] = {
988 [ds_1307] = {
989 .nvram_offset = 8,
990 .nvram_size = 56,
991 },
992 [ds_1308] = {
993 .nvram_offset = 8,
994 .nvram_size = 56,
995 },
996 [ds_1337] = {
997 .alarm = 1,
998 .century_reg = DS1307_REG_MONTH,
999 .century_bit = DS1337_BIT_CENTURY,
1000 },
1001 [ds_1338] = {
1002 .nvram_offset = 8,
1003 .nvram_size = 56,
1004 },
1005 [ds_1339] = {
1006 .alarm = 1,
1007 .century_reg = DS1307_REG_MONTH,
1008 .century_bit = DS1337_BIT_CENTURY,
1009 .bbsqi_bit = DS1339_BIT_BBSQI,
1010 .trickle_charger_reg = 0x10,
1011 .do_trickle_setup = &do_trickle_setup_ds1339,
1012 .requires_trickle_resistor = true,
1013 .charge_default = true,
1014 },
1015 [ds_1340] = {
1016 .century_reg = DS1307_REG_HOUR,
1017 .century_enable_bit = DS1340_BIT_CENTURY_EN,
1018 .century_bit = DS1340_BIT_CENTURY,
1019 .do_trickle_setup = &do_trickle_setup_ds1339,
1020 .trickle_charger_reg = 0x08,
1021 .requires_trickle_resistor = true,
1022 .charge_default = true,
1023 },
1024 [ds_1341] = {
1025 .century_reg = DS1307_REG_MONTH,
1026 .century_bit = DS1337_BIT_CENTURY,
1027 },
1028 [ds_1388] = {
1029 .offset = 1,
1030 .trickle_charger_reg = 0x0a,
1031 },
1032 [ds_3231] = {
1033 .alarm = 1,
1034 .century_reg = DS1307_REG_MONTH,
1035 .century_bit = DS1337_BIT_CENTURY,
1036 .bbsqi_bit = DS3231_BIT_BBSQW,
1037 },
1038 [rx_8130] = {
1039 .alarm = 1,
1040 /* this is battery backed SRAM */
1041 .nvram_offset = 0x20,
1042 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
1043 .offset = 0x10,
1044 .irq_handler = rx8130_irq,
1045 .rtc_ops = &rx8130_rtc_ops,
1046 .trickle_charger_reg = RX8130_REG_CONTROL1,
1047 .do_trickle_setup = &do_trickle_setup_rx8130,
1048 },
1049 [m41t0] = {
1050 .rtc_ops = &m41txx_rtc_ops,
1051 },
1052 [m41t00] = {
1053 .rtc_ops = &m41txx_rtc_ops,
1054 },
1055 [m41t11] = {
1056 /* this is battery backed SRAM */
1057 .nvram_offset = 8,
1058 .nvram_size = 56,
1059 .rtc_ops = &m41txx_rtc_ops,
1060 },
1061 [mcp794xx] = {
1062 .alarm = 1,
1063 /* this is battery backed SRAM */
1064 .nvram_offset = 0x20,
1065 .nvram_size = 0x40,
1066 .irq_handler = mcp794xx_irq,
1067 .rtc_ops = &mcp794xx_rtc_ops,
1068 },
1069 };
1070
1071 static const struct i2c_device_id ds1307_id[] = {
1072 { "ds1307", ds_1307 },
1073 { "ds1308", ds_1308 },
1074 { "ds1337", ds_1337 },
1075 { "ds1338", ds_1338 },
1076 { "ds1339", ds_1339 },
1077 { "ds1388", ds_1388 },
1078 { "ds1340", ds_1340 },
1079 { "ds1341", ds_1341 },
1080 { "ds3231", ds_3231 },
1081 { "m41t0", m41t0 },
1082 { "m41t00", m41t00 },
1083 { "m41t11", m41t11 },
1084 { "mcp7940x", mcp794xx },
1085 { "mcp7941x", mcp794xx },
1086 { "pt7c4338", ds_1307 },
1087 { "rx8025", rx_8025 },
1088 { "isl12057", ds_1337 },
1089 { "rx8130", rx_8130 },
1090 { }
1091 };
1092 MODULE_DEVICE_TABLE(i2c, ds1307_id);
1093
1094 static const struct of_device_id ds1307_of_match[] = {
1095 {
1096 .compatible = "dallas,ds1307",
1097 .data = (void *)ds_1307
1098 },
1099 {
1100 .compatible = "dallas,ds1308",
1101 .data = (void *)ds_1308
1102 },
1103 {
1104 .compatible = "dallas,ds1337",
1105 .data = (void *)ds_1337
1106 },
1107 {
1108 .compatible = "dallas,ds1338",
1109 .data = (void *)ds_1338
1110 },
1111 {
1112 .compatible = "dallas,ds1339",
1113 .data = (void *)ds_1339
1114 },
1115 {
1116 .compatible = "dallas,ds1388",
1117 .data = (void *)ds_1388
1118 },
1119 {
1120 .compatible = "dallas,ds1340",
1121 .data = (void *)ds_1340
1122 },
1123 {
1124 .compatible = "dallas,ds1341",
1125 .data = (void *)ds_1341
1126 },
1127 {
1128 .compatible = "maxim,ds3231",
1129 .data = (void *)ds_3231
1130 },
1131 {
1132 .compatible = "st,m41t0",
1133 .data = (void *)m41t0
1134 },
1135 {
1136 .compatible = "st,m41t00",
1137 .data = (void *)m41t00
1138 },
1139 {
1140 .compatible = "st,m41t11",
1141 .data = (void *)m41t11
1142 },
1143 {
1144 .compatible = "microchip,mcp7940x",
1145 .data = (void *)mcp794xx
1146 },
1147 {
1148 .compatible = "microchip,mcp7941x",
1149 .data = (void *)mcp794xx
1150 },
1151 {
1152 .compatible = "pericom,pt7c4338",
1153 .data = (void *)ds_1307
1154 },
1155 {
1156 .compatible = "epson,rx8025",
1157 .data = (void *)rx_8025
1158 },
1159 {
1160 .compatible = "isil,isl12057",
1161 .data = (void *)ds_1337
1162 },
1163 {
1164 .compatible = "epson,rx8130",
1165 .data = (void *)rx_8130
1166 },
1167 { }
1168 };
1169 MODULE_DEVICE_TABLE(of, ds1307_of_match);
1170
1171 /*
1172 * The ds1337 and ds1339 both have two alarms, but we only use the first
1173 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
1174 * signal; ds1339 chips have only one alarm signal.
1175 */
1176 static irqreturn_t ds1307_irq(int irq, void *dev_id)
1177 {
1178 struct ds1307 *ds1307 = dev_id;
1179 struct mutex *lock = &ds1307->rtc->ops_lock;
1180 int stat, ret;
1181
1182 mutex_lock(lock);
1183 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1184 if (ret)
1185 goto out;
1186
1187 if (stat & DS1337_BIT_A1I) {
1188 stat &= ~DS1337_BIT_A1I;
1189 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1190
1191 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1192 DS1337_BIT_A1IE, 0);
1193 if (ret)
1194 goto out;
1195
1196 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1197 }
1198
1199 out:
1200 mutex_unlock(lock);
1201
1202 return IRQ_HANDLED;
1203 }
1204
1205 /*----------------------------------------------------------------------*/
1206
1207 static const struct rtc_class_ops ds13xx_rtc_ops = {
1208 .read_time = ds1307_get_time,
1209 .set_time = ds1307_set_time,
1210 .read_alarm = ds1337_read_alarm,
1211 .set_alarm = ds1337_set_alarm,
1212 .alarm_irq_enable = ds1307_alarm_irq_enable,
1213 };
1214
1215 static ssize_t frequency_test_store(struct device *dev,
1216 struct device_attribute *attr,
1217 const char *buf, size_t count)
1218 {
1219 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1220 bool freq_test_en;
1221 int ret;
1222
1223 ret = kstrtobool(buf, &freq_test_en);
1224 if (ret) {
1225 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1226 return ret;
1227 }
1228
1229 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1230 freq_test_en ? M41TXX_BIT_FT : 0);
1231
1232 return count;
1233 }
1234
1235 static ssize_t frequency_test_show(struct device *dev,
1236 struct device_attribute *attr,
1237 char *buf)
1238 {
1239 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1240 unsigned int ctrl_reg;
1241
1242 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1243
1244 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
1245 "off\n");
1246 }
1247
1248 static DEVICE_ATTR_RW(frequency_test);
1249
1250 static struct attribute *rtc_freq_test_attrs[] = {
1251 &dev_attr_frequency_test.attr,
1252 NULL,
1253 };
1254
1255 static const struct attribute_group rtc_freq_test_attr_group = {
1256 .attrs = rtc_freq_test_attrs,
1257 };
1258
1259 static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1260 {
1261 int err;
1262
1263 switch (ds1307->type) {
1264 case m41t0:
1265 case m41t00:
1266 case m41t11:
1267 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1268 if (err)
1269 return err;
1270 break;
1271 default:
1272 break;
1273 }
1274
1275 return 0;
1276 }
1277
1278 /*----------------------------------------------------------------------*/
1279
1280 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1281 size_t bytes)
1282 {
1283 struct ds1307 *ds1307 = priv;
1284 const struct chip_desc *chip = &chips[ds1307->type];
1285
1286 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
1287 val, bytes);
1288 }
1289
1290 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1291 size_t bytes)
1292 {
1293 struct ds1307 *ds1307 = priv;
1294 const struct chip_desc *chip = &chips[ds1307->type];
1295
1296 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
1297 val, bytes);
1298 }
1299
1300 /*----------------------------------------------------------------------*/
1301
1302 static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1303 const struct chip_desc *chip)
1304 {
1305 u32 ohms, chargeable;
1306 bool diode = chip->charge_default;
1307
1308 if (!chip->do_trickle_setup)
1309 return 0;
1310
1311 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1312 &ohms) && chip->requires_trickle_resistor)
1313 return 0;
1314
1315 /* aux-voltage-chargeable takes precedence over the deprecated
1316 * trickle-diode-disable
1317 */
1318 if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable",
1319 &chargeable)) {
1320 switch (chargeable) {
1321 case 0:
1322 diode = false;
1323 break;
1324 case 1:
1325 diode = true;
1326 break;
1327 default:
1328 dev_warn(ds1307->dev,
1329 "unsupported aux-voltage-chargeable value\n");
1330 break;
1331 }
1332 } else if (device_property_read_bool(ds1307->dev,
1333 "trickle-diode-disable")) {
1334 diode = false;
1335 }
1336
1337 return chip->do_trickle_setup(ds1307, ohms, diode);
1338 }
1339
1340 /*----------------------------------------------------------------------*/
1341
1342 #if IS_REACHABLE(CONFIG_HWMON)
1343
1344 /*
1345 * Temperature sensor support for ds3231 devices.
1346 */
1347
1348 #define DS3231_REG_TEMPERATURE 0x11
1349
1350 /*
1351 * A user-initiated temperature conversion is not started by this function,
1352 * so the temperature is updated once every 64 seconds.
1353 */
1354 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1355 {
1356 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1357 u8 temp_buf[2];
1358 s16 temp;
1359 int ret;
1360
1361 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1362 temp_buf, sizeof(temp_buf));
1363 if (ret)
1364 return ret;
1365 /*
1366 * Temperature is represented as a 10-bit code with a resolution of
1367 * 0.25 degree celsius and encoded in two's complement format.
1368 */
1369 temp = (temp_buf[0] << 8) | temp_buf[1];
1370 temp >>= 6;
1371 *mC = temp * 250;
1372
1373 return 0;
1374 }
1375
1376 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1377 struct device_attribute *attr, char *buf)
1378 {
1379 int ret;
1380 s32 temp;
1381
1382 ret = ds3231_hwmon_read_temp(dev, &temp);
1383 if (ret)
1384 return ret;
1385
1386 return sprintf(buf, "%d\n", temp);
1387 }
1388 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1389 NULL, 0);
1390
1391 static struct attribute *ds3231_hwmon_attrs[] = {
1392 &sensor_dev_attr_temp1_input.dev_attr.attr,
1393 NULL,
1394 };
1395 ATTRIBUTE_GROUPS(ds3231_hwmon);
1396
1397 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1398 {
1399 struct device *dev;
1400
1401 if (ds1307->type != ds_3231)
1402 return;
1403
1404 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1405 ds1307,
1406 ds3231_hwmon_groups);
1407 if (IS_ERR(dev)) {
1408 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1409 PTR_ERR(dev));
1410 }
1411 }
1412
1413 #else
1414
1415 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1416 {
1417 }
1418
1419 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1420
1421 /*----------------------------------------------------------------------*/
1422
1423 /*
1424 * Square-wave output support for DS3231
1425 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1426 */
1427 #ifdef CONFIG_COMMON_CLK
1428
1429 enum {
1430 DS3231_CLK_SQW = 0,
1431 DS3231_CLK_32KHZ,
1432 };
1433
1434 #define clk_sqw_to_ds1307(clk) \
1435 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1436 #define clk_32khz_to_ds1307(clk) \
1437 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1438
1439 static int ds3231_clk_sqw_rates[] = {
1440 1,
1441 1024,
1442 4096,
1443 8192,
1444 };
1445
1446 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1447 {
1448 struct mutex *lock = &ds1307->rtc->ops_lock;
1449 int ret;
1450
1451 mutex_lock(lock);
1452 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1453 mask, value);
1454 mutex_unlock(lock);
1455
1456 return ret;
1457 }
1458
1459 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1460 unsigned long parent_rate)
1461 {
1462 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1463 int control, ret;
1464 int rate_sel = 0;
1465
1466 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1467 if (ret)
1468 return ret;
1469 if (control & DS1337_BIT_RS1)
1470 rate_sel += 1;
1471 if (control & DS1337_BIT_RS2)
1472 rate_sel += 2;
1473
1474 return ds3231_clk_sqw_rates[rate_sel];
1475 }
1476
1477 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1478 unsigned long *prate)
1479 {
1480 int i;
1481
1482 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1483 if (ds3231_clk_sqw_rates[i] <= rate)
1484 return ds3231_clk_sqw_rates[i];
1485 }
1486
1487 return 0;
1488 }
1489
1490 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1491 unsigned long parent_rate)
1492 {
1493 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1494 int control = 0;
1495 int rate_sel;
1496
1497 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1498 rate_sel++) {
1499 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1500 break;
1501 }
1502
1503 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1504 return -EINVAL;
1505
1506 if (rate_sel & 1)
1507 control |= DS1337_BIT_RS1;
1508 if (rate_sel & 2)
1509 control |= DS1337_BIT_RS2;
1510
1511 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1512 control);
1513 }
1514
1515 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1516 {
1517 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1518
1519 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1520 }
1521
1522 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1523 {
1524 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1525
1526 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1527 }
1528
1529 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1530 {
1531 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1532 int control, ret;
1533
1534 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1535 if (ret)
1536 return ret;
1537
1538 return !(control & DS1337_BIT_INTCN);
1539 }
1540
1541 static const struct clk_ops ds3231_clk_sqw_ops = {
1542 .prepare = ds3231_clk_sqw_prepare,
1543 .unprepare = ds3231_clk_sqw_unprepare,
1544 .is_prepared = ds3231_clk_sqw_is_prepared,
1545 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1546 .round_rate = ds3231_clk_sqw_round_rate,
1547 .set_rate = ds3231_clk_sqw_set_rate,
1548 };
1549
1550 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1551 unsigned long parent_rate)
1552 {
1553 return 32768;
1554 }
1555
1556 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1557 {
1558 struct mutex *lock = &ds1307->rtc->ops_lock;
1559 int ret;
1560
1561 mutex_lock(lock);
1562 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1563 DS3231_BIT_EN32KHZ,
1564 enable ? DS3231_BIT_EN32KHZ : 0);
1565 mutex_unlock(lock);
1566
1567 return ret;
1568 }
1569
1570 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1571 {
1572 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1573
1574 return ds3231_clk_32khz_control(ds1307, true);
1575 }
1576
1577 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1578 {
1579 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1580
1581 ds3231_clk_32khz_control(ds1307, false);
1582 }
1583
1584 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1585 {
1586 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1587 int status, ret;
1588
1589 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1590 if (ret)
1591 return ret;
1592
1593 return !!(status & DS3231_BIT_EN32KHZ);
1594 }
1595
1596 static const struct clk_ops ds3231_clk_32khz_ops = {
1597 .prepare = ds3231_clk_32khz_prepare,
1598 .unprepare = ds3231_clk_32khz_unprepare,
1599 .is_prepared = ds3231_clk_32khz_is_prepared,
1600 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1601 };
1602
1603 static const char *ds3231_clks_names[] = {
1604 [DS3231_CLK_SQW] = "ds3231_clk_sqw",
1605 [DS3231_CLK_32KHZ] = "ds3231_clk_32khz",
1606 };
1607
1608 static struct clk_init_data ds3231_clks_init[] = {
1609 [DS3231_CLK_SQW] = {
1610 .ops = &ds3231_clk_sqw_ops,
1611 },
1612 [DS3231_CLK_32KHZ] = {
1613 .ops = &ds3231_clk_32khz_ops,
1614 },
1615 };
1616
1617 static int ds3231_clks_register(struct ds1307 *ds1307)
1618 {
1619 struct device_node *node = ds1307->dev->of_node;
1620 struct clk_onecell_data *onecell;
1621 int i;
1622
1623 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1624 if (!onecell)
1625 return -ENOMEM;
1626
1627 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1628 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1629 sizeof(onecell->clks[0]), GFP_KERNEL);
1630 if (!onecell->clks)
1631 return -ENOMEM;
1632
1633 /* optional override of the clockname */
1634 device_property_read_string_array(ds1307->dev, "clock-output-names",
1635 ds3231_clks_names,
1636 ARRAY_SIZE(ds3231_clks_names));
1637
1638 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1639 struct clk_init_data init = ds3231_clks_init[i];
1640
1641 /*
1642 * Interrupt signal due to alarm conditions and square-wave
1643 * output share same pin, so don't initialize both.
1644 */
1645 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1646 continue;
1647
1648 init.name = ds3231_clks_names[i];
1649 ds1307->clks[i].init = &init;
1650
1651 onecell->clks[i] = devm_clk_register(ds1307->dev,
1652 &ds1307->clks[i]);
1653 if (IS_ERR(onecell->clks[i]))
1654 return PTR_ERR(onecell->clks[i]);
1655 }
1656
1657 if (node)
1658 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1659
1660 return 0;
1661 }
1662
1663 static void ds1307_clks_register(struct ds1307 *ds1307)
1664 {
1665 int ret;
1666
1667 if (ds1307->type != ds_3231)
1668 return;
1669
1670 ret = ds3231_clks_register(ds1307);
1671 if (ret) {
1672 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1673 ret);
1674 }
1675 }
1676
1677 #else
1678
1679 static void ds1307_clks_register(struct ds1307 *ds1307)
1680 {
1681 }
1682
1683 #endif /* CONFIG_COMMON_CLK */
1684
1685 #ifdef CONFIG_WATCHDOG_CORE
1686 static const struct watchdog_info ds1388_wdt_info = {
1687 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
1688 .identity = "DS1388 watchdog",
1689 };
1690
1691 static const struct watchdog_ops ds1388_wdt_ops = {
1692 .owner = THIS_MODULE,
1693 .start = ds1388_wdt_start,
1694 .stop = ds1388_wdt_stop,
1695 .ping = ds1388_wdt_ping,
1696 .set_timeout = ds1388_wdt_set_timeout,
1697
1698 };
1699
1700 static void ds1307_wdt_register(struct ds1307 *ds1307)
1701 {
1702 struct watchdog_device *wdt;
1703 int err;
1704 int val;
1705
1706 if (ds1307->type != ds_1388)
1707 return;
1708
1709 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
1710 if (!wdt)
1711 return;
1712
1713 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
1714 if (!err && val & DS1388_BIT_WF)
1715 wdt->bootstatus = WDIOF_CARDRESET;
1716
1717 wdt->info = &ds1388_wdt_info;
1718 wdt->ops = &ds1388_wdt_ops;
1719 wdt->timeout = 99;
1720 wdt->max_timeout = 99;
1721 wdt->min_timeout = 1;
1722
1723 watchdog_init_timeout(wdt, 0, ds1307->dev);
1724 watchdog_set_drvdata(wdt, ds1307);
1725 devm_watchdog_register_device(ds1307->dev, wdt);
1726 }
1727 #else
1728 static void ds1307_wdt_register(struct ds1307 *ds1307)
1729 {
1730 }
1731 #endif /* CONFIG_WATCHDOG_CORE */
1732
1733 static const struct regmap_config regmap_config = {
1734 .reg_bits = 8,
1735 .val_bits = 8,
1736 };
1737
1738 static int ds1307_probe(struct i2c_client *client,
1739 const struct i2c_device_id *id)
1740 {
1741 struct ds1307 *ds1307;
1742 const void *match;
1743 int err = -ENODEV;
1744 int tmp;
1745 const struct chip_desc *chip;
1746 bool want_irq;
1747 bool ds1307_can_wakeup_device = false;
1748 unsigned char regs[8];
1749 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1750 u8 trickle_charger_setup = 0;
1751
1752 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1753 if (!ds1307)
1754 return -ENOMEM;
1755
1756 dev_set_drvdata(&client->dev, ds1307);
1757 ds1307->dev = &client->dev;
1758 ds1307->name = client->name;
1759
1760 ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1761 if (IS_ERR(ds1307->regmap)) {
1762 dev_err(ds1307->dev, "regmap allocation failed\n");
1763 return PTR_ERR(ds1307->regmap);
1764 }
1765
1766 i2c_set_clientdata(client, ds1307);
1767
1768 match = device_get_match_data(&client->dev);
1769 if (match) {
1770 ds1307->type = (enum ds_type)match;
1771 chip = &chips[ds1307->type];
1772 } else if (id) {
1773 chip = &chips[id->driver_data];
1774 ds1307->type = id->driver_data;
1775 } else {
1776 return -ENODEV;
1777 }
1778
1779 want_irq = client->irq > 0 && chip->alarm;
1780
1781 if (!pdata)
1782 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1783 else if (pdata->trickle_charger_setup)
1784 trickle_charger_setup = pdata->trickle_charger_setup;
1785
1786 if (trickle_charger_setup && chip->trickle_charger_reg) {
1787 dev_dbg(ds1307->dev,
1788 "writing trickle charger info 0x%x to 0x%x\n",
1789 trickle_charger_setup, chip->trickle_charger_reg);
1790 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1791 trickle_charger_setup);
1792 }
1793
1794 /*
1795 * For devices with no IRQ directly connected to the SoC, the RTC chip
1796 * can be forced as a wakeup source by stating that explicitly in
1797 * the device's .dts file using the "wakeup-source" boolean property.
1798 * If the "wakeup-source" property is set, don't request an IRQ.
1799 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1800 * if supported by the RTC.
1801 */
1802 if (chip->alarm && device_property_read_bool(&client->dev, "wakeup-source"))
1803 ds1307_can_wakeup_device = true;
1804
1805 switch (ds1307->type) {
1806 case ds_1337:
1807 case ds_1339:
1808 case ds_1341:
1809 case ds_3231:
1810 /* get registers that the "rtc" read below won't read... */
1811 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1812 regs, 2);
1813 if (err) {
1814 dev_dbg(ds1307->dev, "read error %d\n", err);
1815 goto exit;
1816 }
1817
1818 /* oscillator off? turn it on, so clock can tick. */
1819 if (regs[0] & DS1337_BIT_nEOSC)
1820 regs[0] &= ~DS1337_BIT_nEOSC;
1821
1822 /*
1823 * Using IRQ or defined as wakeup-source?
1824 * Disable the square wave and both alarms.
1825 * For some variants, be sure alarms can trigger when we're
1826 * running on Vbackup (BBSQI/BBSQW)
1827 */
1828 if (want_irq || ds1307_can_wakeup_device) {
1829 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1830 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1831 }
1832
1833 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1834 regs[0]);
1835
1836 /* oscillator fault? clear flag, and warn */
1837 if (regs[1] & DS1337_BIT_OSF) {
1838 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1839 regs[1] & ~DS1337_BIT_OSF);
1840 dev_warn(ds1307->dev, "SET TIME!\n");
1841 }
1842 break;
1843
1844 case rx_8025:
1845 err = regmap_bulk_read(ds1307->regmap,
1846 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1847 if (err) {
1848 dev_dbg(ds1307->dev, "read error %d\n", err);
1849 goto exit;
1850 }
1851
1852 /* oscillator off? turn it on, so clock can tick. */
1853 if (!(regs[1] & RX8025_BIT_XST)) {
1854 regs[1] |= RX8025_BIT_XST;
1855 regmap_write(ds1307->regmap,
1856 RX8025_REG_CTRL2 << 4 | 0x08,
1857 regs[1]);
1858 dev_warn(ds1307->dev,
1859 "oscillator stop detected - SET TIME!\n");
1860 }
1861
1862 if (regs[1] & RX8025_BIT_PON) {
1863 regs[1] &= ~RX8025_BIT_PON;
1864 regmap_write(ds1307->regmap,
1865 RX8025_REG_CTRL2 << 4 | 0x08,
1866 regs[1]);
1867 dev_warn(ds1307->dev, "power-on detected\n");
1868 }
1869
1870 if (regs[1] & RX8025_BIT_VDET) {
1871 regs[1] &= ~RX8025_BIT_VDET;
1872 regmap_write(ds1307->regmap,
1873 RX8025_REG_CTRL2 << 4 | 0x08,
1874 regs[1]);
1875 dev_warn(ds1307->dev, "voltage drop detected\n");
1876 }
1877
1878 /* make sure we are running in 24hour mode */
1879 if (!(regs[0] & RX8025_BIT_2412)) {
1880 u8 hour;
1881
1882 /* switch to 24 hour mode */
1883 regmap_write(ds1307->regmap,
1884 RX8025_REG_CTRL1 << 4 | 0x08,
1885 regs[0] | RX8025_BIT_2412);
1886
1887 err = regmap_bulk_read(ds1307->regmap,
1888 RX8025_REG_CTRL1 << 4 | 0x08,
1889 regs, 2);
1890 if (err) {
1891 dev_dbg(ds1307->dev, "read error %d\n", err);
1892 goto exit;
1893 }
1894
1895 /* correct hour */
1896 hour = bcd2bin(regs[DS1307_REG_HOUR]);
1897 if (hour == 12)
1898 hour = 0;
1899 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1900 hour += 12;
1901
1902 regmap_write(ds1307->regmap,
1903 DS1307_REG_HOUR << 4 | 0x08, hour);
1904 }
1905 break;
1906 case ds_1388:
1907 err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp);
1908 if (err) {
1909 dev_dbg(ds1307->dev, "read error %d\n", err);
1910 goto exit;
1911 }
1912
1913 /* oscillator off? turn it on, so clock can tick. */
1914 if (tmp & DS1388_BIT_nEOSC) {
1915 tmp &= ~DS1388_BIT_nEOSC;
1916 regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp);
1917 }
1918 break;
1919 default:
1920 break;
1921 }
1922
1923 /* read RTC registers */
1924 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1925 sizeof(regs));
1926 if (err) {
1927 dev_dbg(ds1307->dev, "read error %d\n", err);
1928 goto exit;
1929 }
1930
1931 if (ds1307->type == mcp794xx &&
1932 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1933 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1934 regs[DS1307_REG_WDAY] |
1935 MCP794XX_BIT_VBATEN);
1936 }
1937
1938 tmp = regs[DS1307_REG_HOUR];
1939 switch (ds1307->type) {
1940 case ds_1340:
1941 case m41t0:
1942 case m41t00:
1943 case m41t11:
1944 /*
1945 * NOTE: ignores century bits; fix before deploying
1946 * systems that will run through year 2100.
1947 */
1948 break;
1949 case rx_8025:
1950 break;
1951 default:
1952 if (!(tmp & DS1307_BIT_12HR))
1953 break;
1954
1955 /*
1956 * Be sure we're in 24 hour mode. Multi-master systems
1957 * take note...
1958 */
1959 tmp = bcd2bin(tmp & 0x1f);
1960 if (tmp == 12)
1961 tmp = 0;
1962 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1963 tmp += 12;
1964 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1965 bin2bcd(tmp));
1966 }
1967
1968 if (want_irq || ds1307_can_wakeup_device) {
1969 device_set_wakeup_capable(ds1307->dev, true);
1970 set_bit(HAS_ALARM, &ds1307->flags);
1971 }
1972
1973 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1974 if (IS_ERR(ds1307->rtc))
1975 return PTR_ERR(ds1307->rtc);
1976
1977 if (ds1307_can_wakeup_device && !want_irq) {
1978 dev_info(ds1307->dev,
1979 "'wakeup-source' is set, request for an IRQ is disabled!\n");
1980 /* We cannot support UIE mode if we do not have an IRQ line */
1981 ds1307->rtc->uie_unsupported = 1;
1982 }
1983
1984 if (want_irq) {
1985 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1986 chip->irq_handler ?: ds1307_irq,
1987 IRQF_SHARED | IRQF_ONESHOT,
1988 ds1307->name, ds1307);
1989 if (err) {
1990 client->irq = 0;
1991 device_set_wakeup_capable(ds1307->dev, false);
1992 clear_bit(HAS_ALARM, &ds1307->flags);
1993 dev_err(ds1307->dev, "unable to request IRQ!\n");
1994 } else {
1995 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1996 }
1997 }
1998
1999 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
2000 err = ds1307_add_frequency_test(ds1307);
2001 if (err)
2002 return err;
2003
2004 err = devm_rtc_register_device(ds1307->rtc);
2005 if (err)
2006 return err;
2007
2008 if (chip->nvram_size) {
2009 struct nvmem_config nvmem_cfg = {
2010 .name = "ds1307_nvram",
2011 .word_size = 1,
2012 .stride = 1,
2013 .size = chip->nvram_size,
2014 .reg_read = ds1307_nvram_read,
2015 .reg_write = ds1307_nvram_write,
2016 .priv = ds1307,
2017 };
2018
2019 devm_rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
2020 }
2021
2022 ds1307_hwmon_register(ds1307);
2023 ds1307_clks_register(ds1307);
2024 ds1307_wdt_register(ds1307);
2025
2026 return 0;
2027
2028 exit:
2029 return err;
2030 }
2031
2032 static struct i2c_driver ds1307_driver = {
2033 .driver = {
2034 .name = "rtc-ds1307",
2035 .of_match_table = ds1307_of_match,
2036 },
2037 .probe = ds1307_probe,
2038 .id_table = ds1307_id,
2039 };
2040
2041 module_i2c_driver(ds1307_driver);
2042
2043 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
2044 MODULE_LICENSE("GPL");
Linux with added FPC-III support