drivers/rtc/rtc-ds1685.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time
   4  * chips.
   5  *
   6  * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
   7  * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
   8  *
   9  * References:
  10  *    DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
  11  *    DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
  12  *    DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
  13  *    Application Note 90, Using the Multiplex Bus RTC Extended Features.
  14  */
  15
  16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17
  18 #include <linux/bcd.h>
  19 #include <linux/delay.h>
  20 #include <linux/io.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/rtc.h>
  24 #include <linux/workqueue.h>
  25
  26 #include <linux/rtc/ds1685.h>
  27
  28 #ifdef CONFIG_PROC_FS
  29 #include <linux/proc_fs.h>
  30 #endif
  31
  32
  33 /* ----------------------------------------------------------------------- */
  34 /*
  35  *  Standard read/write
  36  *  all registers are mapped in CPU address space
  37  */
  38
  39 /**
  40  * ds1685_read - read a value from an rtc register.
  41  * @rtc: pointer to the ds1685 rtc structure.
  42  * @reg: the register address to read.
  43  */
  44 static u8
  45 ds1685_read(struct ds1685_priv *rtc, int reg)
  46 {
  47         return readb((u8 __iomem *)rtc->regs +
  48                      (reg * rtc->regstep));
  49 }
  50
  51 /**
  52  * ds1685_write - write a value to an rtc register.
  53  * @rtc: pointer to the ds1685 rtc structure.
  54  * @reg: the register address to write.
  55  * @value: value to write to the register.
  56  */
  57 static void
  58 ds1685_write(struct ds1685_priv *rtc, int reg, u8 value)
  59 {
  60         writeb(value, ((u8 __iomem *)rtc->regs +
  61                        (reg * rtc->regstep)));
  62 }
  63 /* ----------------------------------------------------------------------- */
  64
  65 /*
  66  * Indirect read/write functions
  67  * access happens via address and data register mapped in CPU address space
  68  */
  69
  70 /**
  71  * ds1685_indirect_read - read a value from an rtc register.
  72  * @rtc: pointer to the ds1685 rtc structure.
  73  * @reg: the register address to read.
  74  */
  75 static u8
  76 ds1685_indirect_read(struct ds1685_priv *rtc, int reg)
  77 {
  78         writeb(reg, rtc->regs);
  79         return readb(rtc->data);
  80 }
  81
  82 /**
  83  * ds1685_indirect_write - write a value to an rtc register.
  84  * @rtc: pointer to the ds1685 rtc structure.
  85  * @reg: the register address to write.
  86  * @value: value to write to the register.
  87  */
  88 static void
  89 ds1685_indirect_write(struct ds1685_priv *rtc, int reg, u8 value)
  90 {
  91         writeb(reg, rtc->regs);
  92         writeb(value, rtc->data);
  93 }
  94
  95 /* ----------------------------------------------------------------------- */
  96 /* Inlined functions */
  97
  98 /**
  99  * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD.
 100  * @rtc: pointer to the ds1685 rtc structure.
 101  * @val: u8 time value to consider converting.
 102  * @bcd_mask: u8 mask value if BCD mode is used.
 103  * @bin_mask: u8 mask value if BIN mode is used.
 104  *
 105  * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE.
 106  */
 107 static inline u8
 108 ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask)
 109 {
 110         if (rtc->bcd_mode)
 111                 return (bcd2bin(val) & bcd_mask);
 112
 113         return (val & bin_mask);
 114 }
 115
 116 /**
 117  * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD.
 118  * @rtc: pointer to the ds1685 rtc structure.
 119  * @val: u8 time value to consider converting.
 120  * @bin_mask: u8 mask value if BIN mode is used.
 121  * @bcd_mask: u8 mask value if BCD mode is used.
 122  *
 123  * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE.
 124  */
 125 static inline u8
 126 ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask)
 127 {
 128         if (rtc->bcd_mode)
 129                 return (bin2bcd(val) & bcd_mask);
 130
 131         return (val & bin_mask);
 132 }
 133
 134 /**
 135  * s1685_rtc_check_mday - check validity of the day of month.
 136  * @rtc: pointer to the ds1685 rtc structure.
 137  * @mday: day of month.
 138  *
 139  * Returns -EDOM if the day of month is not within 1..31 range.
 140  */
 141 static inline int
 142 ds1685_rtc_check_mday(struct ds1685_priv *rtc, u8 mday)
 143 {
 144         if (rtc->bcd_mode) {
 145                 if (mday < 0x01 || mday > 0x31 || (mday & 0x0f) > 0x09)
 146                         return -EDOM;
 147         } else {
 148                 if (mday < 1 || mday > 31)
 149                         return -EDOM;
 150         }
 151         return 0;
 152 }
 153
 154 /**
 155  * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0.
 156  * @rtc: pointer to the ds1685 rtc structure.
 157  */
 158 static inline void
 159 ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc)
 160 {
 161         rtc->write(rtc, RTC_CTRL_A,
 162                    (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0)));
 163 }
 164
 165 /**
 166  * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1.
 167  * @rtc: pointer to the ds1685 rtc structure.
 168  */
 169 static inline void
 170 ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc)
 171 {
 172         rtc->write(rtc, RTC_CTRL_A,
 173                    (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0));
 174 }
 175
 176 /**
 177  * ds1685_rtc_begin_data_access - prepare the rtc for data access.
 178  * @rtc: pointer to the ds1685 rtc structure.
 179  *
 180  * This takes several steps to prepare the rtc for access to get/set time
 181  * and alarm values from the rtc registers:
 182  *  - Sets the SET bit in Control Register B.
 183  *  - Reads Ext Control Register 4A and checks the INCR bit.
 184  *  - If INCR is active, a short delay is added before Ext Control Register 4A
 185  *    is read again in a loop until INCR is inactive.
 186  *  - Switches the rtc to bank 1.  This allows access to all relevant
 187  *    data for normal rtc operation, as bank 0 contains only the nvram.
 188  */
 189 static inline void
 190 ds1685_rtc_begin_data_access(struct ds1685_priv *rtc)
 191 {
 192         /* Set the SET bit in Ctrl B */
 193         rtc->write(rtc, RTC_CTRL_B,
 194                    (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
 195
 196         /* Switch to Bank 1 */
 197         ds1685_rtc_switch_to_bank1(rtc);
 198
 199         /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
 200         while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
 201                 cpu_relax();
 202 }
 203
 204 /**
 205  * ds1685_rtc_end_data_access - end data access on the rtc.
 206  * @rtc: pointer to the ds1685 rtc structure.
 207  *
 208  * This ends what was started by ds1685_rtc_begin_data_access:
 209  *  - Switches the rtc back to bank 0.
 210  *  - Clears the SET bit in Control Register B.
 211  */
 212 static inline void
 213 ds1685_rtc_end_data_access(struct ds1685_priv *rtc)
 214 {
 215         /* Switch back to Bank 0 */
 216         ds1685_rtc_switch_to_bank0(rtc);
 217
 218         /* Clear the SET bit in Ctrl B */
 219         rtc->write(rtc, RTC_CTRL_B,
 220                    (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
 221 }
 222
 223 /**
 224  * ds1685_rtc_get_ssn - retrieve the silicon serial number.
 225  * @rtc: pointer to the ds1685 rtc structure.
 226  * @ssn: u8 array to hold the bits of the silicon serial number.
 227  *
 228  * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The
 229  * first byte is the model number, the next six bytes are the serial number
 230  * digits, and the final byte is a CRC check byte.  Together, they form the
 231  * silicon serial number.
 232  *
 233  * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be
 234  * called first before calling this function, else data will be read out of
 235  * the bank0 NVRAM.  Be sure to call ds1685_rtc_switch_to_bank0 when done.
 236  */
 237 static inline void
 238 ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn)
 239 {
 240         ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL);
 241         ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1);
 242         ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2);
 243         ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3);
 244         ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4);
 245         ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5);
 246         ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6);
 247         ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC);
 248 }
 249 /* ----------------------------------------------------------------------- */
 250
 251
 252 /* ----------------------------------------------------------------------- */
 253 /* Read/Set Time & Alarm functions */
 254
 255 /**
 256  * ds1685_rtc_read_time - reads the time registers.
 257  * @dev: pointer to device structure.
 258  * @tm: pointer to rtc_time structure.
 259  */
 260 static int
 261 ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm)
 262 {
 263         struct ds1685_priv *rtc = dev_get_drvdata(dev);
 264         u8 century;
 265         u8 seconds, minutes, hours, wday, mday, month, years;
 266
 267         /* Fetch the time info from the RTC registers. */
 268         ds1685_rtc_begin_data_access(rtc);
 269         seconds = rtc->read(rtc, RTC_SECS);
 270         minutes = rtc->read(rtc, RTC_MINS);
 271         hours   = rtc->read(rtc, RTC_HRS);
 272         wday    = rtc->read(rtc, RTC_WDAY);
 273         mday    = rtc->read(rtc, RTC_MDAY);
 274         month   = rtc->read(rtc, RTC_MONTH);
 275         years   = rtc->read(rtc, RTC_YEAR);
 276         century = rtc->read(rtc, RTC_CENTURY);
 277         ds1685_rtc_end_data_access(rtc);
 278
 279         /* bcd2bin if needed, perform fixups, and store to rtc_time. */
 280         years        = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK,
 281                                           RTC_YEAR_BIN_MASK);
 282         century      = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK,
 283                                           RTC_CENTURY_MASK);
 284         tm->tm_sec   = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK,
 285                                           RTC_SECS_BIN_MASK);
 286         tm->tm_min   = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK,
 287                                           RTC_MINS_BIN_MASK);
 288         tm->tm_hour  = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK,
 289                                           RTC_HRS_24_BIN_MASK);
 290         tm->tm_wday  = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK,
 291                                            RTC_WDAY_MASK) - 1);
 292         tm->tm_mday  = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
 293                                           RTC_MDAY_BIN_MASK);
 294         tm->tm_mon   = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK,
 295                                            RTC_MONTH_BIN_MASK) - 1);
 296         tm->tm_year  = ((years + (century * 100)) - 1900);
 297         tm->tm_yday  = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
 298         tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */
 299
 300         return 0;
 301 }
 302
 303 /**
 304  * ds1685_rtc_set_time - sets the time registers.
 305  * @dev: pointer to device structure.
 306  * @tm: pointer to rtc_time structure.
 307  */
 308 static int
 309 ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
 310 {
 311         struct ds1685_priv *rtc = dev_get_drvdata(dev);
 312         u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century;
 313
 314         /* Fetch the time info from rtc_time. */
 315         seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK,
 316                                      RTC_SECS_BCD_MASK);
 317         minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK,
 318                                      RTC_MINS_BCD_MASK);
 319         hours   = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK,
 320                                      RTC_HRS_24_BCD_MASK);
 321         wday    = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK,
 322                                      RTC_WDAY_MASK);
 323         mday    = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK,
 324                                      RTC_MDAY_BCD_MASK);
 325         month   = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK,
 326                                      RTC_MONTH_BCD_MASK);
 327         years   = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100),
 328                                      RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK);
 329         century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100),
 330                                      RTC_CENTURY_MASK, RTC_CENTURY_MASK);
 331
 332         /*
 333          * Perform Sanity Checks:
 334          *   - Months: !> 12, Month Day != 0.
 335          *   - Month Day !> Max days in current month.
 336          *   - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7.
 337          */
 338         if ((tm->tm_mon > 11) || (mday == 0))
 339                 return -EDOM;
 340
 341         if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year))
 342                 return -EDOM;
 343
 344         if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) ||
 345             (tm->tm_sec >= 60)  || (wday > 7))
 346                 return -EDOM;
 347
 348         /*
 349          * Set the data mode to use and store the time values in the
 350          * RTC registers.
 351          */
 352         ds1685_rtc_begin_data_access(rtc);
 353         ctrlb = rtc->read(rtc, RTC_CTRL_B);
 354         if (rtc->bcd_mode)
 355                 ctrlb &= ~(RTC_CTRL_B_DM);
 356         else
 357                 ctrlb |= RTC_CTRL_B_DM;
 358         rtc->write(rtc, RTC_CTRL_B, ctrlb);
 359         rtc->write(rtc, RTC_SECS, seconds);
 360         rtc->write(rtc, RTC_MINS, minutes);
 361         rtc->write(rtc, RTC_HRS, hours);
 362         rtc->write(rtc, RTC_WDAY, wday);
 363         rtc->write(rtc, RTC_MDAY, mday);
 364         rtc->write(rtc, RTC_MONTH, month);
 365         rtc->write(rtc, RTC_YEAR, years);
 366         rtc->write(rtc, RTC_CENTURY, century);
 367         ds1685_rtc_end_data_access(rtc);
 368
 369         return 0;
 370 }
 371
 372 /**
 373  * ds1685_rtc_read_alarm - reads the alarm registers.
 374  * @dev: pointer to device structure.
 375  * @alrm: pointer to rtc_wkalrm structure.
 376  *
 377  * There are three primary alarm registers: seconds, minutes, and hours.
 378  * A fourth alarm register for the month date is also available in bank1 for
 379  * kickstart/wakeup features.  The DS1685/DS1687 manual states that a
 380  * "don't care" value ranging from 0xc0 to 0xff may be written into one or
 381  * more of the three alarm bytes to act as a wildcard value.  The fourth
 382  * byte doesn't support a "don't care" value.
 383  */
 384 static int
 385 ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 386 {
 387         struct ds1685_priv *rtc = dev_get_drvdata(dev);
 388         u8 seconds, minutes, hours, mday, ctrlb, ctrlc;
 389         int ret;
 390
 391         /* Fetch the alarm info from the RTC alarm registers. */
 392         ds1685_rtc_begin_data_access(rtc);
 393         seconds = rtc->read(rtc, RTC_SECS_ALARM);
 394         minutes = rtc->read(rtc, RTC_MINS_ALARM);
 395         hours   = rtc->read(rtc, RTC_HRS_ALARM);
 396         mday    = rtc->read(rtc, RTC_MDAY_ALARM);
 397         ctrlb   = rtc->read(rtc, RTC_CTRL_B);
 398         ctrlc   = rtc->read(rtc, RTC_CTRL_C);
 399         ds1685_rtc_end_data_access(rtc);
 400
 401         /* Check the month date for validity. */
 402         ret = ds1685_rtc_check_mday(rtc, mday);
 403         if (ret)
 404                 return ret;
 405
 406         /*
 407          * Check the three alarm bytes.
 408          *
 409          * The Linux RTC system doesn't support the "don't care" capability
 410          * of this RTC chip.  We check for it anyways in case support is
 411          * added in the future and only assign when we care.
 412          */
 413         if (likely(seconds < 0xc0))
 414                 alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds,
 415                                                        RTC_SECS_BCD_MASK,
 416                                                        RTC_SECS_BIN_MASK);
 417
 418         if (likely(minutes < 0xc0))
 419                 alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes,
 420                                                        RTC_MINS_BCD_MASK,
 421                                                        RTC_MINS_BIN_MASK);
 422
 423         if (likely(hours < 0xc0))
 424                 alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours,
 425                                                         RTC_HRS_24_BCD_MASK,
 426                                                         RTC_HRS_24_BIN_MASK);
 427
 428         /* Write the data to rtc_wkalrm. */
 429         alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
 430                                                 RTC_MDAY_BIN_MASK);
 431         alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE);
 432         alrm->pending = !!(ctrlc & RTC_CTRL_C_AF);
 433
 434         return 0;
 435 }
 436
 437 /**
 438  * ds1685_rtc_set_alarm - sets the alarm in registers.
 439  * @dev: pointer to device structure.
 440  * @alrm: pointer to rtc_wkalrm structure.
 441  */
 442 static int
 443 ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 444 {
 445         struct ds1685_priv *rtc = dev_get_drvdata(dev);
 446         u8 ctrlb, seconds, minutes, hours, mday;
 447         int ret;
 448
 449         /* Fetch the alarm info and convert to BCD. */
 450         seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec,
 451                                      RTC_SECS_BIN_MASK,
 452                                      RTC_SECS_BCD_MASK);
 453         minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min,
 454                                      RTC_MINS_BIN_MASK,
 455                                      RTC_MINS_BCD_MASK);
 456         hours   = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour,
 457                                      RTC_HRS_24_BIN_MASK,
 458                                      RTC_HRS_24_BCD_MASK);
 459         mday    = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday,
 460                                      RTC_MDAY_BIN_MASK,
 461                                      RTC_MDAY_BCD_MASK);
 462
 463         /* Check the month date for validity. */
 464         ret = ds1685_rtc_check_mday(rtc, mday);
 465         if (ret)
 466                 return ret;
 467
 468         /*
 469          * Check the three alarm bytes.
 470          *
 471          * The Linux RTC system doesn't support the "don't care" capability
 472          * of this RTC chip because rtc_valid_tm tries to validate every
 473          * field, and we only support four fields.  We put the support
 474          * here anyways for the future.
 475          */
 476         if (unlikely(seconds >= 0xc0))
 477                 seconds = 0xff;
 478
 479         if (unlikely(minutes >= 0xc0))
 480                 minutes = 0xff;
 481
 482         if (unlikely(hours >= 0xc0))
 483                 hours = 0xff;
 484
 485         alrm->time.tm_mon       = -1;
 486         alrm->time.tm_year      = -1;
 487         alrm->time.tm_wday      = -1;
 488         alrm->time.tm_yday      = -1;
 489         alrm->time.tm_isdst     = -1;
 490
 491         /* Disable the alarm interrupt first. */
 492         ds1685_rtc_begin_data_access(rtc);
 493         ctrlb = rtc->read(rtc, RTC_CTRL_B);
 494         rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE)));
 495
 496         /* Read ctrlc to clear RTC_CTRL_C_AF. */
 497         rtc->read(rtc, RTC_CTRL_C);
 498
 499         /*
 500          * Set the data mode to use and store the time values in the
 501          * RTC registers.
 502          */
 503         ctrlb = rtc->read(rtc, RTC_CTRL_B);
 504         if (rtc->bcd_mode)
 505                 ctrlb &= ~(RTC_CTRL_B_DM);
 506         else
 507                 ctrlb |= RTC_CTRL_B_DM;
 508         rtc->write(rtc, RTC_CTRL_B, ctrlb);
 509         rtc->write(rtc, RTC_SECS_ALARM, seconds);
 510         rtc->write(rtc, RTC_MINS_ALARM, minutes);
 511         rtc->write(rtc, RTC_HRS_ALARM, hours);
 512         rtc->write(rtc, RTC_MDAY_ALARM, mday);
 513
 514         /* Re-enable the alarm if needed. */
 515         if (alrm->enabled) {
 516                 ctrlb = rtc->read(rtc, RTC_CTRL_B);
 517                 ctrlb |= RTC_CTRL_B_AIE;
 518                 rtc->write(rtc, RTC_CTRL_B, ctrlb);
 519         }
 520
 521         /* Done! */
 522         ds1685_rtc_end_data_access(rtc);
 523
 524         return 0;
 525 }
 526 /* ----------------------------------------------------------------------- */
 527
 528
 529 /* ----------------------------------------------------------------------- */
 530 /* /dev/rtcX Interface functions */
 531
 532 /**
 533  * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off.
 534  * @dev: pointer to device structure.
 535  * @enabled: flag indicating whether to enable or disable.
 536  */
 537 static int
 538 ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 539 {
 540         struct ds1685_priv *rtc = dev_get_drvdata(dev);
 541
 542         /* Flip the requisite interrupt-enable bit. */
 543         if (enabled)
 544                 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) |
 545                                              RTC_CTRL_B_AIE));
 546         else
 547                 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) &
 548                                              ~(RTC_CTRL_B_AIE)));
 549
 550         /* Read Control C to clear all the flag bits. */
 551         rtc->read(rtc, RTC_CTRL_C);
 552
 553         return 0;
 554 }
 555 /* ----------------------------------------------------------------------- */
 556
 557
 558 /* ----------------------------------------------------------------------- */
 559 /* IRQ handler */
 560
 561 /**
 562  * ds1685_rtc_extended_irq - take care of extended interrupts
 563  * @rtc: pointer to the ds1685 rtc structure.
 564  * @pdev: platform device pointer.
 565  */
 566 static void
 567 ds1685_rtc_extended_irq(struct ds1685_priv *rtc, struct platform_device *pdev)
 568 {
 569         u8 ctrl4a, ctrl4b;
 570
 571         ds1685_rtc_switch_to_bank1(rtc);
 572         ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
 573         ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
 574
 575         /*
 576          * Check for a kickstart interrupt. With Vcc applied, this
 577          * typically means that the power button was pressed, so we
 578          * begin the shutdown sequence.
 579          */
 580         if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) {
 581                 /* Briefly disable kickstarts to debounce button presses. */
 582                 rtc->write(rtc, RTC_EXT_CTRL_4B,
 583                            (rtc->read(rtc, RTC_EXT_CTRL_4B) &
 584                             ~(RTC_CTRL_4B_KSE)));
 585
 586                 /* Clear the kickstart flag. */
 587                 rtc->write(rtc, RTC_EXT_CTRL_4A,
 588                            (ctrl4a & ~(RTC_CTRL_4A_KF)));
 589
 590
 591                 /*
 592                  * Sleep 500ms before re-enabling kickstarts.  This allows
 593                  * adequate time to avoid reading signal jitter as additional
 594                  * button presses.
 595                  */
 596                 msleep(500);
 597                 rtc->write(rtc, RTC_EXT_CTRL_4B,
 598                            (rtc->read(rtc, RTC_EXT_CTRL_4B) |
 599                             RTC_CTRL_4B_KSE));
 600
 601                 /* Call the platform pre-poweroff function. Else, shutdown. */
 602                 if (rtc->prepare_poweroff != NULL)
 603                         rtc->prepare_poweroff();
 604                 else
 605                         ds1685_rtc_poweroff(pdev);
 606         }
 607
 608         /*
 609          * Check for a wake-up interrupt.  With Vcc applied, this is
 610          * essentially a second alarm interrupt, except it takes into
 611          * account the 'date' register in bank1 in addition to the
 612          * standard three alarm registers.
 613          */
 614         if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) {
 615                 rtc->write(rtc, RTC_EXT_CTRL_4A,
 616                            (ctrl4a & ~(RTC_CTRL_4A_WF)));
 617
 618                 /* Call the platform wake_alarm function if defined. */
 619                 if (rtc->wake_alarm != NULL)
 620                         rtc->wake_alarm();
 621                 else
 622                         dev_warn(&pdev->dev,
 623                                  "Wake Alarm IRQ just occurred!\n");
 624         }
 625
 626         /*
 627          * Check for a ram-clear interrupt.  This happens if RIE=1 and RF=0
 628          * when RCE=1 in 4B.  This clears all NVRAM bytes in bank0 by setting
 629          * each byte to a logic 1.  This has no effect on any extended
 630          * NV-SRAM that might be present, nor on the time/calendar/alarm
 631          * registers.  After a ram-clear is completed, there is a minimum
 632          * recovery time of ~150ms in which all reads/writes are locked out.
 633          * NOTE: A ram-clear can still occur if RCE=1 and RIE=0.  We cannot
 634          * catch this scenario.
 635          */
 636         if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) {
 637                 rtc->write(rtc, RTC_EXT_CTRL_4A,
 638                            (ctrl4a & ~(RTC_CTRL_4A_RF)));
 639                 msleep(150);
 640
 641                 /* Call the platform post_ram_clear function if defined. */
 642                 if (rtc->post_ram_clear != NULL)
 643                         rtc->post_ram_clear();
 644                 else
 645                         dev_warn(&pdev->dev,
 646                                  "RAM-Clear IRQ just occurred!\n");
 647         }
 648         ds1685_rtc_switch_to_bank0(rtc);
 649 }
 650
 651 /**
 652  * ds1685_rtc_irq_handler - IRQ handler.
 653  * @irq: IRQ number.
 654  * @dev_id: platform device pointer.
 655  */
 656 static irqreturn_t
 657 ds1685_rtc_irq_handler(int irq, void *dev_id)
 658 {
 659         struct platform_device *pdev = dev_id;
 660         struct ds1685_priv *rtc = platform_get_drvdata(pdev);
 661         struct mutex *rtc_mutex;
 662         u8 ctrlb, ctrlc;
 663         unsigned long events = 0;
 664         u8 num_irqs = 0;
 665
 666         /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */
 667         if (unlikely(!rtc))
 668                 return IRQ_HANDLED;
 669
 670         rtc_mutex = &rtc->dev->ops_lock;
 671         mutex_lock(rtc_mutex);
 672
 673         /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */
 674         ctrlb = rtc->read(rtc, RTC_CTRL_B);
 675         ctrlc = rtc->read(rtc, RTC_CTRL_C);
 676
 677         /* Is the IRQF bit set? */
 678         if (likely(ctrlc & RTC_CTRL_C_IRQF)) {
 679                 /*
 680                  * We need to determine if it was one of the standard
 681                  * events: PF, AF, or UF.  If so, we handle them and
 682                  * update the RTC core.
 683                  */
 684                 if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) {
 685                         events = RTC_IRQF;
 686
 687                         /* Check for a periodic interrupt. */
 688                         if ((ctrlb & RTC_CTRL_B_PIE) &&
 689                             (ctrlc & RTC_CTRL_C_PF)) {
 690                                 events |= RTC_PF;
 691                                 num_irqs++;
 692                         }
 693
 694                         /* Check for an alarm interrupt. */
 695                         if ((ctrlb & RTC_CTRL_B_AIE) &&
 696                             (ctrlc & RTC_CTRL_C_AF)) {
 697                                 events |= RTC_AF;
 698                                 num_irqs++;
 699                         }
 700
 701                         /* Check for an update interrupt. */
 702                         if ((ctrlb & RTC_CTRL_B_UIE) &&
 703                             (ctrlc & RTC_CTRL_C_UF)) {
 704                                 events |= RTC_UF;
 705                                 num_irqs++;
 706                         }
 707                 } else {
 708                         /*
 709                          * One of the "extended" interrupts was received that
 710                          * is not recognized by the RTC core.
 711                          */
 712                         ds1685_rtc_extended_irq(rtc, pdev);
 713                 }
 714         }
 715         rtc_update_irq(rtc->dev, num_irqs, events);
 716         mutex_unlock(rtc_mutex);
 717
 718         return events ? IRQ_HANDLED : IRQ_NONE;
 719 }
 720 /* ----------------------------------------------------------------------- */
 721
 722
 723 /* ----------------------------------------------------------------------- */
 724 /* ProcFS interface */
 725
 726 #ifdef CONFIG_PROC_FS
 727 #define NUM_REGS        6       /* Num of control registers. */
 728 #define NUM_BITS        8       /* Num bits per register. */
 729 #define NUM_SPACES      4       /* Num spaces between each bit. */
 730
 731 /*
 732  * Periodic Interrupt Rates.
 733  */
 734 static const char *ds1685_rtc_pirq_rate[16] = {
 735         "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms",
 736         "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms",
 737         "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms"
 738 };
 739
 740 /*
 741  * Square-Wave Output Frequencies.
 742  */
 743 static const char *ds1685_rtc_sqw_freq[16] = {
 744         "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz",
 745         "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz"
 746 };
 747
 748 /**
 749  * ds1685_rtc_proc - procfs access function.
 750  * @dev: pointer to device structure.
 751  * @seq: pointer to seq_file structure.
 752  */
 753 static int
 754 ds1685_rtc_proc(struct device *dev, struct seq_file *seq)
 755 {
 756         struct ds1685_priv *rtc = dev_get_drvdata(dev);
 757         u8 ctrla, ctrlb, ctrld, ctrl4a, ctrl4b, ssn[8];
 758         char *model;
 759
 760         /* Read all the relevant data from the control registers. */
 761         ds1685_rtc_switch_to_bank1(rtc);
 762         ds1685_rtc_get_ssn(rtc, ssn);
 763         ctrla = rtc->read(rtc, RTC_CTRL_A);
 764         ctrlb = rtc->read(rtc, RTC_CTRL_B);
 765         ctrld = rtc->read(rtc, RTC_CTRL_D);
 766         ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
 767         ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
 768         ds1685_rtc_switch_to_bank0(rtc);
 769
 770         /* Determine the RTC model. */
 771         switch (ssn[0]) {
 772         case RTC_MODEL_DS1685:
 773                 model = "DS1685/DS1687\0";
 774                 break;
 775         case RTC_MODEL_DS1689:
 776                 model = "DS1689/DS1693\0";
 777                 break;
 778         case RTC_MODEL_DS17285:
 779                 model = "DS17285/DS17287\0";
 780                 break;
 781         case RTC_MODEL_DS17485:
 782                 model = "DS17485/DS17487\0";
 783                 break;
 784         case RTC_MODEL_DS17885:
 785                 model = "DS17885/DS17887\0";
 786                 break;
 787         default:
 788                 model = "Unknown\0";
 789                 break;
 790         }
 791
 792         /* Print out the information. */
 793         seq_printf(seq,
 794            "Model\t\t: %s\n"
 795            "Oscillator\t: %s\n"
 796            "12/24hr\t\t: %s\n"
 797            "DST\t\t: %s\n"
 798            "Data mode\t: %s\n"
 799            "Battery\t\t: %s\n"
 800            "Aux batt\t: %s\n"
 801            "Update IRQ\t: %s\n"
 802            "Periodic IRQ\t: %s\n"
 803            "Periodic Rate\t: %s\n"
 804            "SQW Freq\t: %s\n"
 805            "Serial #\t: %8phC\n",
 806            model,
 807            ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"),
 808            ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"),
 809            ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"),
 810            ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"),
 811            ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"),
 812            ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"),
 813            ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"),
 814            ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"),
 815            (!(ctrl4b & RTC_CTRL_4B_E32K) ?
 816             ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"),
 817            (!((ctrl4b & RTC_CTRL_4B_E32K)) ?
 818             ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"),
 819            ssn);
 820         return 0;
 821 }
 822 #else
 823 #define ds1685_rtc_proc NULL
 824 #endif /* CONFIG_PROC_FS */
 825 /* ----------------------------------------------------------------------- */
 826
 827
 828 /* ----------------------------------------------------------------------- */
 829 /* RTC Class operations */
 830
 831 static const struct rtc_class_ops
 832 ds1685_rtc_ops = {
 833         .proc = ds1685_rtc_proc,
 834         .read_time = ds1685_rtc_read_time,
 835         .set_time = ds1685_rtc_set_time,
 836         .read_alarm = ds1685_rtc_read_alarm,
 837         .set_alarm = ds1685_rtc_set_alarm,
 838         .alarm_irq_enable = ds1685_rtc_alarm_irq_enable,
 839 };
 840 /* ----------------------------------------------------------------------- */
 841
 842 static int ds1685_nvram_read(void *priv, unsigned int pos, void *val,
 843                              size_t size)
 844 {
 845         struct ds1685_priv *rtc = priv;
 846         struct mutex *rtc_mutex = &rtc->dev->ops_lock;
 847         ssize_t count;
 848         u8 *buf = val;
 849         int err;
 850
 851         err = mutex_lock_interruptible(rtc_mutex);
 852         if (err)
 853                 return err;
 854
 855         ds1685_rtc_switch_to_bank0(rtc);
 856
 857         /* Read NVRAM in time and bank0 registers. */
 858         for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
 859              count++, size--) {
 860                 if (count < NVRAM_SZ_TIME)
 861                         *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++));
 862                 else
 863                         *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++));
 864         }
 865
 866 #ifndef CONFIG_RTC_DRV_DS1689
 867         if (size > 0) {
 868                 ds1685_rtc_switch_to_bank1(rtc);
 869
 870 #ifndef CONFIG_RTC_DRV_DS1685
 871                 /* Enable burst-mode on DS17x85/DS17x87 */
 872                 rtc->write(rtc, RTC_EXT_CTRL_4A,
 873                            (rtc->read(rtc, RTC_EXT_CTRL_4A) |
 874                             RTC_CTRL_4A_BME));
 875
 876                 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
 877                  * reading with burst-mode */
 878                 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
 879                            (pos - NVRAM_TOTAL_SZ_BANK0));
 880 #endif
 881
 882                 /* Read NVRAM in bank1 registers. */
 883                 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
 884                      count++, size--) {
 885 #ifdef CONFIG_RTC_DRV_DS1685
 886                         /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
 887                          * before each read. */
 888                         rtc->write(rtc, RTC_BANK1_RAM_ADDR,
 889                                    (pos - NVRAM_TOTAL_SZ_BANK0));
 890 #endif
 891                         *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT);
 892                         pos++;
 893                 }
 894
 895 #ifndef CONFIG_RTC_DRV_DS1685
 896                 /* Disable burst-mode on DS17x85/DS17x87 */
 897                 rtc->write(rtc, RTC_EXT_CTRL_4A,
 898                            (rtc->read(rtc, RTC_EXT_CTRL_4A) &
 899                             ~(RTC_CTRL_4A_BME)));
 900 #endif
 901                 ds1685_rtc_switch_to_bank0(rtc);
 902         }
 903 #endif /* !CONFIG_RTC_DRV_DS1689 */
 904         mutex_unlock(rtc_mutex);
 905
 906         return 0;
 907 }
 908
 909 static int ds1685_nvram_write(void *priv, unsigned int pos, void *val,
 910                               size_t size)
 911 {
 912         struct ds1685_priv *rtc = priv;
 913         struct mutex *rtc_mutex = &rtc->dev->ops_lock;
 914         ssize_t count;
 915         u8 *buf = val;
 916         int err;
 917
 918         err = mutex_lock_interruptible(rtc_mutex);
 919         if (err)
 920                 return err;
 921
 922         ds1685_rtc_switch_to_bank0(rtc);
 923
 924         /* Write NVRAM in time and bank0 registers. */
 925         for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
 926              count++, size--)
 927                 if (count < NVRAM_SZ_TIME)
 928                         rtc->write(rtc, (NVRAM_TIME_BASE + pos++),
 929                                    *buf++);
 930                 else
 931                         rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++);
 932
 933 #ifndef CONFIG_RTC_DRV_DS1689
 934         if (size > 0) {
 935                 ds1685_rtc_switch_to_bank1(rtc);
 936
 937 #ifndef CONFIG_RTC_DRV_DS1685
 938                 /* Enable burst-mode on DS17x85/DS17x87 */
 939                 rtc->write(rtc, RTC_EXT_CTRL_4A,
 940                            (rtc->read(rtc, RTC_EXT_CTRL_4A) |
 941                             RTC_CTRL_4A_BME));
 942
 943                 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
 944                  * writing with burst-mode */
 945                 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
 946                            (pos - NVRAM_TOTAL_SZ_BANK0));
 947 #endif
 948
 949                 /* Write NVRAM in bank1 registers. */
 950                 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
 951                      count++, size--) {
 952 #ifdef CONFIG_RTC_DRV_DS1685
 953                         /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
 954                          * before each read. */
 955                         rtc->write(rtc, RTC_BANK1_RAM_ADDR,
 956                                    (pos - NVRAM_TOTAL_SZ_BANK0));
 957 #endif
 958                         rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++);
 959                         pos++;
 960                 }
 961
 962 #ifndef CONFIG_RTC_DRV_DS1685
 963                 /* Disable burst-mode on DS17x85/DS17x87 */
 964                 rtc->write(rtc, RTC_EXT_CTRL_4A,
 965                            (rtc->read(rtc, RTC_EXT_CTRL_4A) &
 966                             ~(RTC_CTRL_4A_BME)));
 967 #endif
 968                 ds1685_rtc_switch_to_bank0(rtc);
 969         }
 970 #endif /* !CONFIG_RTC_DRV_DS1689 */
 971         mutex_unlock(rtc_mutex);
 972
 973         return 0;
 974 }
 975
 976 /* ----------------------------------------------------------------------- */
 977 /* SysFS interface */
 978
 979 /**
 980  * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status.
 981  * @dev: pointer to device structure.
 982  * @attr: pointer to device_attribute structure.
 983  * @buf: pointer to char array to hold the output.
 984  */
 985 static ssize_t
 986 ds1685_rtc_sysfs_battery_show(struct device *dev,
 987                               struct device_attribute *attr, char *buf)
 988 {
 989         struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
 990         u8 ctrld;
 991
 992         ctrld = rtc->read(rtc, RTC_CTRL_D);
 993
 994         return sprintf(buf, "%s\n",
 995                         (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A");
 996 }
 997 static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL);
 998
 999 /**
1000  * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status.
1001  * @dev: pointer to device structure.
1002  * @attr: pointer to device_attribute structure.
1003  * @buf: pointer to char array to hold the output.
1004  */
1005 static ssize_t
1006 ds1685_rtc_sysfs_auxbatt_show(struct device *dev,
1007                               struct device_attribute *attr, char *buf)
1008 {
1009         struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
1010         u8 ctrl4a;
1011
1012         ds1685_rtc_switch_to_bank1(rtc);
1013         ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
1014         ds1685_rtc_switch_to_bank0(rtc);
1015
1016         return sprintf(buf, "%s\n",
1017                         (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A");
1018 }
1019 static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL);
1020
1021 /**
1022  * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number.
1023  * @dev: pointer to device structure.
1024  * @attr: pointer to device_attribute structure.
1025  * @buf: pointer to char array to hold the output.
1026  */
1027 static ssize_t
1028 ds1685_rtc_sysfs_serial_show(struct device *dev,
1029                              struct device_attribute *attr, char *buf)
1030 {
1031         struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
1032         u8 ssn[8];
1033
1034         ds1685_rtc_switch_to_bank1(rtc);
1035         ds1685_rtc_get_ssn(rtc, ssn);
1036         ds1685_rtc_switch_to_bank0(rtc);
1037
1038         return sprintf(buf, "%8phC\n", ssn);
1039 }
1040 static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL);
1041
1042 /*
1043  * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features.
1044  */
1045 static struct attribute*
1046 ds1685_rtc_sysfs_misc_attrs[] = {
1047         &dev_attr_battery.attr,
1048         &dev_attr_auxbatt.attr,
1049         &dev_attr_serial.attr,
1050         NULL,
1051 };
1052
1053 /*
1054  * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features.
1055  */
1056 static const struct attribute_group
1057 ds1685_rtc_sysfs_misc_grp = {
1058         .name = "misc",
1059         .attrs = ds1685_rtc_sysfs_misc_attrs,
1060 };
1061
1062 /* ----------------------------------------------------------------------- */
1063 /* Driver Probe/Removal */
1064
1065 /**
1066  * ds1685_rtc_probe - initializes rtc driver.
1067  * @pdev: pointer to platform_device structure.
1068  */
1069 static int
1070 ds1685_rtc_probe(struct platform_device *pdev)
1071 {
1072         struct rtc_device *rtc_dev;
1073         struct ds1685_priv *rtc;
1074         struct ds1685_rtc_platform_data *pdata;
1075         u8 ctrla, ctrlb, hours;
1076         unsigned char am_pm;
1077         int ret = 0;
1078         struct nvmem_config nvmem_cfg = {
1079                 .name = "ds1685_nvram",
1080                 .size = NVRAM_TOTAL_SZ,
1081                 .reg_read = ds1685_nvram_read,
1082                 .reg_write = ds1685_nvram_write,
1083         };
1084
1085         /* Get the platform data. */
1086         pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data;
1087         if (!pdata)
1088                 return -ENODEV;
1089
1090         /* Allocate memory for the rtc device. */
1091         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
1092         if (!rtc)
1093                 return -ENOMEM;
1094
1095         /* Setup resources and access functions */
1096         switch (pdata->access_type) {
1097         case ds1685_reg_direct:
1098                 rtc->regs = devm_platform_ioremap_resource(pdev, 0);
1099                 if (IS_ERR(rtc->regs))
1100                         return PTR_ERR(rtc->regs);
1101                 rtc->read = ds1685_read;
1102                 rtc->write = ds1685_write;
1103                 break;
1104         case ds1685_reg_indirect:
1105                 rtc->regs = devm_platform_ioremap_resource(pdev, 0);
1106                 if (IS_ERR(rtc->regs))
1107                         return PTR_ERR(rtc->regs);
1108                 rtc->data = devm_platform_ioremap_resource(pdev, 1);
1109                 if (IS_ERR(rtc->data))
1110                         return PTR_ERR(rtc->data);
1111                 rtc->read = ds1685_indirect_read;
1112                 rtc->write = ds1685_indirect_write;
1113                 break;
1114         }
1115
1116         if (!rtc->read || !rtc->write)
1117                 return -ENXIO;
1118
1119         /* Get the register step size. */
1120         if (pdata->regstep > 0)
1121                 rtc->regstep = pdata->regstep;
1122         else
1123                 rtc->regstep = 1;
1124
1125         /* Platform pre-shutdown function, if defined. */
1126         if (pdata->plat_prepare_poweroff)
1127                 rtc->prepare_poweroff = pdata->plat_prepare_poweroff;
1128
1129         /* Platform wake_alarm function, if defined. */
1130         if (pdata->plat_wake_alarm)
1131                 rtc->wake_alarm = pdata->plat_wake_alarm;
1132
1133         /* Platform post_ram_clear function, if defined. */
1134         if (pdata->plat_post_ram_clear)
1135                 rtc->post_ram_clear = pdata->plat_post_ram_clear;
1136
1137         /* set the driver data. */
1138         platform_set_drvdata(pdev, rtc);
1139
1140         /* Turn the oscillator on if is not already on (DV1 = 1). */
1141         ctrla = rtc->read(rtc, RTC_CTRL_A);
1142         if (!(ctrla & RTC_CTRL_A_DV1))
1143                 ctrla |= RTC_CTRL_A_DV1;
1144
1145         /* Enable the countdown chain (DV2 = 0) */
1146         ctrla &= ~(RTC_CTRL_A_DV2);
1147
1148         /* Clear RS3-RS0 in Control A. */
1149         ctrla &= ~(RTC_CTRL_A_RS_MASK);
1150
1151         /*
1152          * All done with Control A.  Switch to Bank 1 for the remainder of
1153          * the RTC setup so we have access to the extended functions.
1154          */
1155         ctrla |= RTC_CTRL_A_DV0;
1156         rtc->write(rtc, RTC_CTRL_A, ctrla);
1157
1158         /* Default to 32768kHz output. */
1159         rtc->write(rtc, RTC_EXT_CTRL_4B,
1160                    (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K));
1161
1162         /* Set the SET bit in Control B so we can do some housekeeping. */
1163         rtc->write(rtc, RTC_CTRL_B,
1164                    (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
1165
1166         /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
1167         while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
1168                 cpu_relax();
1169
1170         /*
1171          * If the platform supports BCD mode, then set DM=0 in Control B.
1172          * Otherwise, set DM=1 for BIN mode.
1173          */
1174         ctrlb = rtc->read(rtc, RTC_CTRL_B);
1175         if (pdata->bcd_mode)
1176                 ctrlb &= ~(RTC_CTRL_B_DM);
1177         else
1178                 ctrlb |= RTC_CTRL_B_DM;
1179         rtc->bcd_mode = pdata->bcd_mode;
1180
1181         /*
1182          * Disable Daylight Savings Time (DSE = 0).
1183          * The RTC has hardcoded timezone information that is rendered
1184          * obselete.  We'll let the OS deal with DST settings instead.
1185          */
1186         if (ctrlb & RTC_CTRL_B_DSE)
1187                 ctrlb &= ~(RTC_CTRL_B_DSE);
1188
1189         /* Force 24-hour mode (2412 = 1). */
1190         if (!(ctrlb & RTC_CTRL_B_2412)) {
1191                 /* Reinitialize the time hours. */
1192                 hours = rtc->read(rtc, RTC_HRS);
1193                 am_pm = hours & RTC_HRS_AMPM_MASK;
1194                 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1195                                            RTC_HRS_12_BIN_MASK);
1196                 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1197
1198                 /* Enable 24-hour mode. */
1199                 ctrlb |= RTC_CTRL_B_2412;
1200
1201                 /* Write back to Control B, including DM & DSE bits. */
1202                 rtc->write(rtc, RTC_CTRL_B, ctrlb);
1203
1204                 /* Write the time hours back. */
1205                 rtc->write(rtc, RTC_HRS,
1206                            ds1685_rtc_bin2bcd(rtc, hours,
1207                                               RTC_HRS_24_BIN_MASK,
1208                                               RTC_HRS_24_BCD_MASK));
1209
1210                 /* Reinitialize the alarm hours. */
1211                 hours = rtc->read(rtc, RTC_HRS_ALARM);
1212                 am_pm = hours & RTC_HRS_AMPM_MASK;
1213                 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1214                                            RTC_HRS_12_BIN_MASK);
1215                 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1216
1217                 /* Write the alarm hours back. */
1218                 rtc->write(rtc, RTC_HRS_ALARM,
1219                            ds1685_rtc_bin2bcd(rtc, hours,
1220                                               RTC_HRS_24_BIN_MASK,
1221                                               RTC_HRS_24_BCD_MASK));
1222         } else {
1223                 /* 24-hour mode is already set, so write Control B back. */
1224                 rtc->write(rtc, RTC_CTRL_B, ctrlb);
1225         }
1226
1227         /* Unset the SET bit in Control B so the RTC can update. */
1228         rtc->write(rtc, RTC_CTRL_B,
1229                    (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
1230
1231         /* Check the main battery. */
1232         if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT))
1233                 dev_warn(&pdev->dev,
1234                          "Main battery is exhausted! RTC may be invalid!\n");
1235
1236         /* Check the auxillary battery.  It is optional. */
1237         if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2))
1238                 dev_warn(&pdev->dev,
1239                          "Aux battery is exhausted or not available.\n");
1240
1241         /* Read Ctrl B and clear PIE/AIE/UIE. */
1242         rtc->write(rtc, RTC_CTRL_B,
1243                    (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK)));
1244
1245         /* Reading Ctrl C auto-clears PF/AF/UF. */
1246         rtc->read(rtc, RTC_CTRL_C);
1247
1248         /* Read Ctrl 4B and clear RIE/WIE/KSE. */
1249         rtc->write(rtc, RTC_EXT_CTRL_4B,
1250                    (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK)));
1251
1252         /* Clear RF/WF/KF in Ctrl 4A. */
1253         rtc->write(rtc, RTC_EXT_CTRL_4A,
1254                    (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK)));
1255
1256         /*
1257          * Re-enable KSE to handle power button events.  We do not enable
1258          * WIE or RIE by default.
1259          */
1260         rtc->write(rtc, RTC_EXT_CTRL_4B,
1261                    (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE));
1262
1263         rtc_dev = devm_rtc_allocate_device(&pdev->dev);
1264         if (IS_ERR(rtc_dev))
1265                 return PTR_ERR(rtc_dev);
1266
1267         rtc_dev->ops = &ds1685_rtc_ops;
1268
1269         /* Century bit is useless because leap year fails in 1900 and 2100 */
1270         rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
1271         rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
1272
1273         /* Maximum periodic rate is 8192Hz (0.122070ms). */
1274         rtc_dev->max_user_freq = RTC_MAX_USER_FREQ;
1275
1276         /* See if the platform doesn't support UIE. */
1277         if (pdata->uie_unsupported)
1278                 rtc_dev->uie_unsupported = 1;
1279
1280         rtc->dev = rtc_dev;
1281
1282         /*
1283          * Fetch the IRQ and setup the interrupt handler.
1284          *
1285          * Not all platforms have the IRQF pin tied to something.  If not, the
1286          * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but
1287          * there won't be an automatic way of notifying the kernel about it,
1288          * unless ctrlc is explicitly polled.
1289          */
1290         if (!pdata->no_irq) {
1291                 ret = platform_get_irq(pdev, 0);
1292                 if (ret <= 0)
1293                         return ret;
1294
1295                 rtc->irq_num = ret;
1296
1297                 /* Request an IRQ. */
1298                 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_num,
1299                                        NULL, ds1685_rtc_irq_handler,
1300                                        IRQF_SHARED | IRQF_ONESHOT,
1301                                        pdev->name, pdev);
1302
1303                 /* Check to see if something came back. */
1304                 if (unlikely(ret)) {
1305                         dev_warn(&pdev->dev,
1306                                  "RTC interrupt not available\n");
1307                         rtc->irq_num = 0;
1308                 }
1309         }
1310         rtc->no_irq = pdata->no_irq;
1311
1312         /* Setup complete. */
1313         ds1685_rtc_switch_to_bank0(rtc);
1314
1315         ret = rtc_add_group(rtc_dev, &ds1685_rtc_sysfs_misc_grp);
1316         if (ret)
1317                 return ret;
1318
1319         nvmem_cfg.priv = rtc;
1320         ret = devm_rtc_nvmem_register(rtc_dev, &nvmem_cfg);
1321         if (ret)
1322                 return ret;
1323
1324         return devm_rtc_register_device(rtc_dev);
1325 }
1326
1327 /**
1328  * ds1685_rtc_remove - removes rtc driver.
1329  * @pdev: pointer to platform_device structure.
1330  */
1331 static int
1332 ds1685_rtc_remove(struct platform_device *pdev)
1333 {
1334         struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1335
1336         /* Read Ctrl B and clear PIE/AIE/UIE. */
1337         rtc->write(rtc, RTC_CTRL_B,
1338                    (rtc->read(rtc, RTC_CTRL_B) &
1339                     ~(RTC_CTRL_B_PAU_MASK)));
1340
1341         /* Reading Ctrl C auto-clears PF/AF/UF. */
1342         rtc->read(rtc, RTC_CTRL_C);
1343
1344         /* Read Ctrl 4B and clear RIE/WIE/KSE. */
1345         rtc->write(rtc, RTC_EXT_CTRL_4B,
1346                    (rtc->read(rtc, RTC_EXT_CTRL_4B) &
1347                     ~(RTC_CTRL_4B_RWK_MASK)));
1348
1349         /* Manually clear RF/WF/KF in Ctrl 4A. */
1350         rtc->write(rtc, RTC_EXT_CTRL_4A,
1351                    (rtc->read(rtc, RTC_EXT_CTRL_4A) &
1352                     ~(RTC_CTRL_4A_RWK_MASK)));
1353
1354         return 0;
1355 }
1356
1357 /*
1358  * ds1685_rtc_driver - rtc driver properties.
1359  */
1360 static struct platform_driver ds1685_rtc_driver = {
1361         .driver         = {
1362                 .name   = "rtc-ds1685",
1363         },
1364         .probe          = ds1685_rtc_probe,
1365         .remove         = ds1685_rtc_remove,
1366 };
1367 module_platform_driver(ds1685_rtc_driver);
1368 /* ----------------------------------------------------------------------- */
1369
1370
1371 /* ----------------------------------------------------------------------- */
1372 /* Poweroff function */
1373
1374 /**
1375  * ds1685_rtc_poweroff - uses the RTC chip to power the system off.
1376  * @pdev: pointer to platform_device structure.
1377  */
1378 void __noreturn
1379 ds1685_rtc_poweroff(struct platform_device *pdev)
1380 {
1381         u8 ctrla, ctrl4a, ctrl4b;
1382         struct ds1685_priv *rtc;
1383
1384         /* Check for valid RTC data, else, spin forever. */
1385         if (unlikely(!pdev)) {
1386                 pr_emerg("platform device data not available, spinning forever ...\n");
1387                 while(1);
1388                 unreachable();
1389         } else {
1390                 /* Get the rtc data. */
1391                 rtc = platform_get_drvdata(pdev);
1392
1393                 /*
1394                  * Disable our IRQ.  We're powering down, so we're not
1395                  * going to worry about cleaning up.  Most of that should
1396                  * have been taken care of by the shutdown scripts and this
1397                  * is the final function call.
1398                  */
1399                 if (!rtc->no_irq)
1400                         disable_irq_nosync(rtc->irq_num);
1401
1402                 /* Oscillator must be on and the countdown chain enabled. */
1403                 ctrla = rtc->read(rtc, RTC_CTRL_A);
1404                 ctrla |= RTC_CTRL_A_DV1;
1405                 ctrla &= ~(RTC_CTRL_A_DV2);
1406                 rtc->write(rtc, RTC_CTRL_A, ctrla);
1407
1408                 /*
1409                  * Read Control 4A and check the status of the auxillary
1410                  * battery.  This must be present and working (VRT2 = 1)
1411                  * for wakeup and kickstart functionality to be useful.
1412                  */
1413                 ds1685_rtc_switch_to_bank1(rtc);
1414                 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
1415                 if (ctrl4a & RTC_CTRL_4A_VRT2) {
1416                         /* Clear all of the interrupt flags on Control 4A. */
1417                         ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK);
1418                         rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a);
1419
1420                         /*
1421                          * The auxillary battery is present and working.
1422                          * Enable extended functions (ABE=1), enable
1423                          * wake-up (WIE=1), and enable kickstart (KSE=1)
1424                          * in Control 4B.
1425                          */
1426                         ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
1427                         ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE |
1428                                    RTC_CTRL_4B_KSE);
1429                         rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b);
1430                 }
1431
1432                 /* Set PAB to 1 in Control 4A to power the system down. */
1433                 dev_warn(&pdev->dev, "Powerdown.\n");
1434                 msleep(20);
1435                 rtc->write(rtc, RTC_EXT_CTRL_4A,
1436                            (ctrl4a | RTC_CTRL_4A_PAB));
1437
1438                 /* Spin ... we do not switch back to bank0. */
1439                 while(1);
1440                 unreachable();
1441         }
1442 }
1443 EXPORT_SYMBOL(ds1685_rtc_poweroff);
1444 /* ----------------------------------------------------------------------- */
1445
1446
1447 MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>");
1448 MODULE_AUTHOR("Matthias Fuchs <matthias.fuchs@esd-electronics.com>");
1449 MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver");
1450 MODULE_LICENSE("GPL");
1451 MODULE_ALIAS("platform:rtc-ds1685");