drivers/spi/spi-mpc512x-psc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * MPC512x PSC in SPI mode driver.
   4  *
   5  * Copyright (C) 2007,2008 Freescale Semiconductor Inc.
   6  * Original port from 52xx driver:
   7  *      Hongjun Chen <hong-jun.chen@freescale.com>
   8  *
   9  * Fork of mpc52xx_psc_spi.c:
  10  *      Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/errno.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/completion.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/spi/spi.h>
  25 #include <linux/fsl_devices.h>
  26 #include <linux/gpio.h>
  27 #include <asm/mpc52xx_psc.h>
  28
  29 enum {
  30         TYPE_MPC5121,
  31         TYPE_MPC5125,
  32 };
  33
  34 /*
  35  * This macro abstracts the differences in the PSC register layout between
  36  * MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc).
  37  */
  38 #define psc_addr(mps, regname) ({                                       \
  39         void *__ret = NULL;                                             \
  40         switch (mps->type) {                                            \
  41         case TYPE_MPC5121: {                                            \
  42                         struct mpc52xx_psc __iomem *psc = mps->psc;     \
  43                         __ret = &psc->regname;                          \
  44                 };                                                      \
  45                 break;                                                  \
  46         case TYPE_MPC5125: {                                            \
  47                         struct mpc5125_psc __iomem *psc = mps->psc;     \
  48                         __ret = &psc->regname;                          \
  49                 };                                                      \
  50                 break;                                                  \
  51         }                                                               \
  52         __ret; })
  53
  54 struct mpc512x_psc_spi {
  55         void (*cs_control)(struct spi_device *spi, bool on);
  56
  57         /* driver internal data */
  58         int type;
  59         void __iomem *psc;
  60         struct mpc512x_psc_fifo __iomem *fifo;
  61         unsigned int irq;
  62         u8 bits_per_word;
  63         struct clk *clk_mclk;
  64         struct clk *clk_ipg;
  65         u32 mclk_rate;
  66
  67         struct completion txisrdone;
  68 };
  69
  70 /* controller state */
  71 struct mpc512x_psc_spi_cs {
  72         int bits_per_word;
  73         int speed_hz;
  74 };
  75
  76 /* set clock freq, clock ramp, bits per work
  77  * if t is NULL then reset the values to the default values
  78  */
  79 static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
  80                                           struct spi_transfer *t)
  81 {
  82         struct mpc512x_psc_spi_cs *cs = spi->controller_state;
  83
  84         cs->speed_hz = (t && t->speed_hz)
  85             ? t->speed_hz : spi->max_speed_hz;
  86         cs->bits_per_word = (t && t->bits_per_word)
  87             ? t->bits_per_word : spi->bits_per_word;
  88         cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
  89         return 0;
  90 }
  91
  92 static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
  93 {
  94         struct mpc512x_psc_spi_cs *cs = spi->controller_state;
  95         struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
  96         u32 sicr;
  97         u32 ccr;
  98         int speed;
  99         u16 bclkdiv;
 100
 101         sicr = in_be32(psc_addr(mps, sicr));
 102
 103         /* Set clock phase and polarity */
 104         if (spi->mode & SPI_CPHA)
 105                 sicr |= 0x00001000;
 106         else
 107                 sicr &= ~0x00001000;
 108
 109         if (spi->mode & SPI_CPOL)
 110                 sicr |= 0x00002000;
 111         else
 112                 sicr &= ~0x00002000;
 113
 114         if (spi->mode & SPI_LSB_FIRST)
 115                 sicr |= 0x10000000;
 116         else
 117                 sicr &= ~0x10000000;
 118         out_be32(psc_addr(mps, sicr), sicr);
 119
 120         ccr = in_be32(psc_addr(mps, ccr));
 121         ccr &= 0xFF000000;
 122         speed = cs->speed_hz;
 123         if (!speed)
 124                 speed = 1000000;        /* default 1MHz */
 125         bclkdiv = (mps->mclk_rate / speed) - 1;
 126
 127         ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
 128         out_be32(psc_addr(mps, ccr), ccr);
 129         mps->bits_per_word = cs->bits_per_word;
 130
 131         if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
 132                 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
 133 }
 134
 135 static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
 136 {
 137         struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
 138
 139         if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
 140                 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
 141
 142 }
 143
 144 /* extract and scale size field in txsz or rxsz */
 145 #define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
 146
 147 #define EOFBYTE 1
 148
 149 static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
 150                                          struct spi_transfer *t)
 151 {
 152         struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
 153         struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
 154         size_t tx_len = t->len;
 155         size_t rx_len = t->len;
 156         u8 *tx_buf = (u8 *)t->tx_buf;
 157         u8 *rx_buf = (u8 *)t->rx_buf;
 158
 159         if (!tx_buf && !rx_buf && t->len)
 160                 return -EINVAL;
 161
 162         while (rx_len || tx_len) {
 163                 size_t txcount;
 164                 u8 data;
 165                 size_t fifosz;
 166                 size_t rxcount;
 167                 int rxtries;
 168
 169                 /*
 170                  * send the TX bytes in as large a chunk as possible
 171                  * but neither exceed the TX nor the RX FIFOs
 172                  */
 173                 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
 174                 txcount = min(fifosz, tx_len);
 175                 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz));
 176                 fifosz -= in_be32(&fifo->rxcnt) + 1;
 177                 txcount = min(fifosz, txcount);
 178                 if (txcount) {
 179
 180                         /* fill the TX FIFO */
 181                         while (txcount-- > 0) {
 182                                 data = tx_buf ? *tx_buf++ : 0;
 183                                 if (tx_len == EOFBYTE && t->cs_change)
 184                                         setbits32(&fifo->txcmd,
 185                                                   MPC512x_PSC_FIFO_EOF);
 186                                 out_8(&fifo->txdata_8, data);
 187                                 tx_len--;
 188                         }
 189
 190                         /* have the ISR trigger when the TX FIFO is empty */
 191                         reinit_completion(&mps->txisrdone);
 192                         out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
 193                         out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
 194                         wait_for_completion(&mps->txisrdone);
 195                 }
 196
 197                 /*
 198                  * consume as much RX data as the FIFO holds, while we
 199                  * iterate over the transfer's TX data length
 200                  *
 201                  * only insist in draining all the remaining RX bytes
 202                  * when the TX bytes were exhausted (that's at the very
 203                  * end of this transfer, not when still iterating over
 204                  * the transfer's chunks)
 205                  */
 206                 rxtries = 50;
 207                 do {
 208
 209                         /*
 210                          * grab whatever was in the FIFO when we started
 211                          * looking, don't bother fetching what was added to
 212                          * the FIFO while we read from it -- we'll return
 213                          * here eventually and prefer sending out remaining
 214                          * TX data
 215                          */
 216                         fifosz = in_be32(&fifo->rxcnt);
 217                         rxcount = min(fifosz, rx_len);
 218                         while (rxcount-- > 0) {
 219                                 data = in_8(&fifo->rxdata_8);
 220                                 if (rx_buf)
 221                                         *rx_buf++ = data;
 222                                 rx_len--;
 223                         }
 224
 225                         /*
 226                          * come back later if there still is TX data to send,
 227                          * bail out of the RX drain loop if all of the TX data
 228                          * was sent and all of the RX data was received (i.e.
 229                          * when the transmission has completed)
 230                          */
 231                         if (tx_len)
 232                                 break;
 233                         if (!rx_len)
 234                                 break;
 235
 236                         /*
 237                          * TX data transmission has completed while RX data
 238                          * is still pending -- that's a transient situation
 239                          * which depends on wire speed and specific
 240                          * hardware implementation details (buffering) yet
 241                          * should resolve very quickly
 242                          *
 243                          * just yield for a moment to not hog the CPU for
 244                          * too long when running SPI at low speed
 245                          *
 246                          * the timeout range is rather arbitrary and tries
 247                          * to balance throughput against system load; the
 248                          * chosen values result in a minimal timeout of 50
 249                          * times 10us and thus work at speeds as low as
 250                          * some 20kbps, while the maximum timeout at the
 251                          * transfer's end could be 5ms _if_ nothing else
 252                          * ticks in the system _and_ RX data still wasn't
 253                          * received, which only occurs in situations that
 254                          * are exceptional; removing the unpredictability
 255                          * of the timeout either decreases throughput
 256                          * (longer timeouts), or puts more load on the
 257                          * system (fixed short timeouts) or requires the
 258                          * use of a timeout API instead of a counter and an
 259                          * unknown inner delay
 260                          */
 261                         usleep_range(10, 100);
 262
 263                 } while (--rxtries > 0);
 264                 if (!tx_len && rx_len && !rxtries) {
 265                         /*
 266                          * not enough RX bytes even after several retries
 267                          * and the resulting rather long timeout?
 268                          */
 269                         rxcount = in_be32(&fifo->rxcnt);
 270                         dev_warn(&spi->dev,
 271                                  "short xfer, missing %zd RX bytes, FIFO level %zd\n",
 272                                  rx_len, rxcount);
 273                 }
 274
 275                 /*
 276                  * drain and drop RX data which "should not be there" in
 277                  * the first place, for undisturbed transmission this turns
 278                  * into a NOP (except for the FIFO level fetch)
 279                  */
 280                 if (!tx_len && !rx_len) {
 281                         while (in_be32(&fifo->rxcnt))
 282                                 in_8(&fifo->rxdata_8);
 283                 }
 284
 285         }
 286         return 0;
 287 }
 288
 289 static int mpc512x_psc_spi_msg_xfer(struct spi_master *master,
 290                                     struct spi_message *m)
 291 {
 292         struct spi_device *spi;
 293         unsigned cs_change;
 294         int status;
 295         struct spi_transfer *t;
 296
 297         spi = m->spi;
 298         cs_change = 1;
 299         status = 0;
 300         list_for_each_entry(t, &m->transfers, transfer_list) {
 301                 status = mpc512x_psc_spi_transfer_setup(spi, t);
 302                 if (status < 0)
 303                         break;
 304
 305                 if (cs_change)
 306                         mpc512x_psc_spi_activate_cs(spi);
 307                 cs_change = t->cs_change;
 308
 309                 status = mpc512x_psc_spi_transfer_rxtx(spi, t);
 310                 if (status)
 311                         break;
 312                 m->actual_length += t->len;
 313
 314                 spi_transfer_delay_exec(t);
 315
 316                 if (cs_change)
 317                         mpc512x_psc_spi_deactivate_cs(spi);
 318         }
 319
 320         m->status = status;
 321         if (m->complete)
 322                 m->complete(m->context);
 323
 324         if (status || !cs_change)
 325                 mpc512x_psc_spi_deactivate_cs(spi);
 326
 327         mpc512x_psc_spi_transfer_setup(spi, NULL);
 328
 329         spi_finalize_current_message(master);
 330         return status;
 331 }
 332
 333 static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master)
 334 {
 335         struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
 336
 337         dev_dbg(&master->dev, "%s()\n", __func__);
 338
 339         /* Zero MR2 */
 340         in_8(psc_addr(mps, mr2));
 341         out_8(psc_addr(mps, mr2), 0x0);
 342
 343         /* enable transmitter/receiver */
 344         out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
 345
 346         return 0;
 347 }
 348
 349 static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master)
 350 {
 351         struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
 352         struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
 353
 354         dev_dbg(&master->dev, "%s()\n", __func__);
 355
 356         /* disable transmitter/receiver and fifo interrupt */
 357         out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 358         out_be32(&fifo->tximr, 0);
 359
 360         return 0;
 361 }
 362
 363 static int mpc512x_psc_spi_setup(struct spi_device *spi)
 364 {
 365         struct mpc512x_psc_spi_cs *cs = spi->controller_state;
 366         int ret;
 367
 368         if (spi->bits_per_word % 8)
 369                 return -EINVAL;
 370
 371         if (!cs) {
 372                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 373                 if (!cs)
 374                         return -ENOMEM;
 375
 376                 if (gpio_is_valid(spi->cs_gpio)) {
 377                         ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
 378                         if (ret) {
 379                                 dev_err(&spi->dev, "can't get CS gpio: %d\n",
 380                                         ret);
 381                                 kfree(cs);
 382                                 return ret;
 383                         }
 384                         gpio_direction_output(spi->cs_gpio,
 385                                         spi->mode & SPI_CS_HIGH ? 0 : 1);
 386                 }
 387
 388                 spi->controller_state = cs;
 389         }
 390
 391         cs->bits_per_word = spi->bits_per_word;
 392         cs->speed_hz = spi->max_speed_hz;
 393
 394         return 0;
 395 }
 396
 397 static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
 398 {
 399         if (gpio_is_valid(spi->cs_gpio))
 400                 gpio_free(spi->cs_gpio);
 401         kfree(spi->controller_state);
 402 }
 403
 404 static int mpc512x_psc_spi_port_config(struct spi_master *master,
 405                                        struct mpc512x_psc_spi *mps)
 406 {
 407         struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
 408         u32 sicr;
 409         u32 ccr;
 410         int speed;
 411         u16 bclkdiv;
 412
 413         /* Reset the PSC into a known state */
 414         out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX);
 415         out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX);
 416         out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 417
 418         /* Disable psc interrupts all useful interrupts are in fifo */
 419         out_be16(psc_addr(mps, isr_imr.imr), 0);
 420
 421         /* Disable fifo interrupts, will be enabled later */
 422         out_be32(&fifo->tximr, 0);
 423         out_be32(&fifo->rximr, 0);
 424
 425         /* Setup fifo slice address and size */
 426         /*out_be32(&fifo->txsz, 0x0fe00004);*/
 427         /*out_be32(&fifo->rxsz, 0x0ff00004);*/
 428
 429         sicr =  0x01000000 |    /* SIM = 0001 -- 8 bit */
 430                 0x00800000 |    /* GenClk = 1 -- internal clk */
 431                 0x00008000 |    /* SPI = 1 */
 432                 0x00004000 |    /* MSTR = 1   -- SPI master */
 433                 0x00000800;     /* UseEOF = 1 -- SS low until EOF */
 434
 435         out_be32(psc_addr(mps, sicr), sicr);
 436
 437         ccr = in_be32(psc_addr(mps, ccr));
 438         ccr &= 0xFF000000;
 439         speed = 1000000;        /* default 1MHz */
 440         bclkdiv = (mps->mclk_rate / speed) - 1;
 441         ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
 442         out_be32(psc_addr(mps, ccr), ccr);
 443
 444         /* Set 2ms DTL delay */
 445         out_8(psc_addr(mps, ctur), 0x00);
 446         out_8(psc_addr(mps, ctlr), 0x82);
 447
 448         /* we don't use the alarms */
 449         out_be32(&fifo->rxalarm, 0xfff);
 450         out_be32(&fifo->txalarm, 0);
 451
 452         /* Enable FIFO slices for Rx/Tx */
 453         out_be32(&fifo->rxcmd,
 454                  MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
 455         out_be32(&fifo->txcmd,
 456                  MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
 457
 458         mps->bits_per_word = 8;
 459
 460         return 0;
 461 }
 462
 463 static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
 464 {
 465         struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
 466         struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
 467
 468         /* clear interrupt and wake up the rx/tx routine */
 469         if (in_be32(&fifo->txisr) &
 470             in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
 471                 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
 472                 out_be32(&fifo->tximr, 0);
 473                 complete(&mps->txisrdone);
 474                 return IRQ_HANDLED;
 475         }
 476         return IRQ_NONE;
 477 }
 478
 479 static void mpc512x_spi_cs_control(struct spi_device *spi, bool onoff)
 480 {
 481         gpio_set_value(spi->cs_gpio, onoff);
 482 }
 483
 484 static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
 485                                               u32 size, unsigned int irq)
 486 {
 487         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 488         struct mpc512x_psc_spi *mps;
 489         struct spi_master *master;
 490         int ret;
 491         void *tempp;
 492         struct clk *clk;
 493
 494         master = spi_alloc_master(dev, sizeof *mps);
 495         if (master == NULL)
 496                 return -ENOMEM;
 497
 498         dev_set_drvdata(dev, master);
 499         mps = spi_master_get_devdata(master);
 500         mps->type = (int)of_device_get_match_data(dev);
 501         mps->irq = irq;
 502
 503         if (pdata == NULL) {
 504                 mps->cs_control = mpc512x_spi_cs_control;
 505         } else {
 506                 mps->cs_control = pdata->cs_control;
 507                 master->bus_num = pdata->bus_num;
 508                 master->num_chipselect = pdata->max_chipselect;
 509         }
 510
 511         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 512         master->setup = mpc512x_psc_spi_setup;
 513         master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw;
 514         master->transfer_one_message = mpc512x_psc_spi_msg_xfer;
 515         master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw;
 516         master->cleanup = mpc512x_psc_spi_cleanup;
 517         master->dev.of_node = dev->of_node;
 518
 519         tempp = devm_ioremap(dev, regaddr, size);
 520         if (!tempp) {
 521                 dev_err(dev, "could not ioremap I/O port range\n");
 522                 ret = -EFAULT;
 523                 goto free_master;
 524         }
 525         mps->psc = tempp;
 526         mps->fifo =
 527                 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
 528         ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
 529                                 "mpc512x-psc-spi", mps);
 530         if (ret)
 531                 goto free_master;
 532         init_completion(&mps->txisrdone);
 533
 534         clk = devm_clk_get(dev, "mclk");
 535         if (IS_ERR(clk)) {
 536                 ret = PTR_ERR(clk);
 537                 goto free_master;
 538         }
 539         ret = clk_prepare_enable(clk);
 540         if (ret)
 541                 goto free_master;
 542         mps->clk_mclk = clk;
 543         mps->mclk_rate = clk_get_rate(clk);
 544
 545         clk = devm_clk_get(dev, "ipg");
 546         if (IS_ERR(clk)) {
 547                 ret = PTR_ERR(clk);
 548                 goto free_mclk_clock;
 549         }
 550         ret = clk_prepare_enable(clk);
 551         if (ret)
 552                 goto free_mclk_clock;
 553         mps->clk_ipg = clk;
 554
 555         ret = mpc512x_psc_spi_port_config(master, mps);
 556         if (ret < 0)
 557                 goto free_ipg_clock;
 558
 559         ret = devm_spi_register_master(dev, master);
 560         if (ret < 0)
 561                 goto free_ipg_clock;
 562
 563         return ret;
 564
 565 free_ipg_clock:
 566         clk_disable_unprepare(mps->clk_ipg);
 567 free_mclk_clock:
 568         clk_disable_unprepare(mps->clk_mclk);
 569 free_master:
 570         spi_master_put(master);
 571
 572         return ret;
 573 }
 574
 575 static int mpc512x_psc_spi_do_remove(struct device *dev)
 576 {
 577         struct spi_master *master = dev_get_drvdata(dev);
 578         struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
 579
 580         clk_disable_unprepare(mps->clk_mclk);
 581         clk_disable_unprepare(mps->clk_ipg);
 582
 583         return 0;
 584 }
 585
 586 static int mpc512x_psc_spi_of_probe(struct platform_device *op)
 587 {
 588         const u32 *regaddr_p;
 589         u64 regaddr64, size64;
 590
 591         regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
 592         if (!regaddr_p) {
 593                 dev_err(&op->dev, "Invalid PSC address\n");
 594                 return -EINVAL;
 595         }
 596         regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
 597
 598         return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
 599                                 irq_of_parse_and_map(op->dev.of_node, 0));
 600 }
 601
 602 static int mpc512x_psc_spi_of_remove(struct platform_device *op)
 603 {
 604         return mpc512x_psc_spi_do_remove(&op->dev);
 605 }
 606
 607 static const struct of_device_id mpc512x_psc_spi_of_match[] = {
 608         { .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 },
 609         { .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 },
 610         {},
 611 };
 612
 613 MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
 614
 615 static struct platform_driver mpc512x_psc_spi_of_driver = {
 616         .probe = mpc512x_psc_spi_of_probe,
 617         .remove = mpc512x_psc_spi_of_remove,
 618         .driver = {
 619                 .name = "mpc512x-psc-spi",
 620                 .of_match_table = mpc512x_psc_spi_of_match,
 621         },
 622 };
 623 module_platform_driver(mpc512x_psc_spi_of_driver);
 624
 625 MODULE_AUTHOR("John Rigby");
 626 MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
 627 MODULE_LICENSE("GPL");