| blob | 17877e85980b290137d12f23a08cf41e743d2325 |
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * This header provides constants specific to AM33XX pinctrl bindings.
4 */
6 #ifndef _DT_BINDINGS_PINCTRL_AM33XX_H
7 #define _DT_BINDINGS_PINCTRL_AM33XX_H
9 #include <dt-bindings/pinctrl/omap.h>
11 /* am33xx specific mux bit defines */
12 #undef PULL_ENA
13 #undef INPUT_EN
15 #define PULL_DISABLE (1 << 3)
16 #define INPUT_EN (1 << 5)
17 #define SLEWCTRL_SLOW (1 << 6)
18 #define SLEWCTRL_FAST 0
20 /* update macro depending on INPUT_EN and PULL_ENA */
21 #undef PIN_OUTPUT
22 #undef PIN_OUTPUT_PULLUP
23 #undef PIN_OUTPUT_PULLDOWN
24 #undef PIN_INPUT
25 #undef PIN_INPUT_PULLUP
26 #undef PIN_INPUT_PULLDOWN
28 #define PIN_OUTPUT (PULL_DISABLE)
29 #define PIN_OUTPUT_PULLUP (PULL_UP)
30 #define PIN_OUTPUT_PULLDOWN 0
31 #define PIN_INPUT (INPUT_EN | PULL_DISABLE)
32 #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
33 #define PIN_INPUT_PULLDOWN (INPUT_EN)
35 /* undef non-existing modes */
36 #undef PIN_OFF_NONE
37 #undef PIN_OFF_OUTPUT_HIGH
38 #undef PIN_OFF_OUTPUT_LOW
39 #undef PIN_OFF_INPUT_PULLUP
40 #undef PIN_OFF_INPUT_PULLDOWN
41 #undef PIN_OFF_WAKEUPENABLE
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
52 #define AM335X_PIN_GPMC_AD7 0x81c
53 #define AM335X_PIN_GPMC_AD8 0x820
54 #define AM335X_PIN_GPMC_AD9 0x824
55 #define AM335X_PIN_GPMC_AD10 0x828
56 #define AM335X_PIN_GPMC_AD11 0x82c
57 #define AM335X_PIN_GPMC_AD12 0x830
58 #define AM335X_PIN_GPMC_AD13 0x834
59 #define AM335X_PIN_GPMC_AD14 0x838
60 #define AM335X_PIN_GPMC_AD15 0x83c
61 #define AM335X_PIN_GPMC_A0 0x840
62 #define AM335X_PIN_GPMC_A1 0x844
63 #define AM335X_PIN_GPMC_A2 0x848
64 #define AM335X_PIN_GPMC_A3 0x84c
65 #define AM335X_PIN_GPMC_A4 0x850
66 #define AM335X_PIN_GPMC_A5 0x854
67 #define AM335X_PIN_GPMC_A6 0x858
68 #define AM335X_PIN_GPMC_A7 0x85c
69 #define AM335X_PIN_GPMC_A8 0x860
70 #define AM335X_PIN_GPMC_A9 0x864
71 #define AM335X_PIN_GPMC_A10 0x868
72 #define AM335X_PIN_GPMC_A11 0x86c
73 #define AM335X_PIN_GPMC_WAIT0 0x870
74 #define AM335X_PIN_GPMC_WPN 0x874
75 #define AM335X_PIN_GPMC_BEN1 0x878
76 #define AM335X_PIN_GPMC_CSN0 0x87c
77 #define AM335X_PIN_GPMC_CSN1 0x880
78 #define AM335X_PIN_GPMC_CSN2 0x884
79 #define AM335X_PIN_GPMC_CSN3 0x888
80 #define AM335X_PIN_GPMC_CLK 0x88c
81 #define AM335X_PIN_GPMC_ADVN_ALE 0x890
82 #define AM335X_PIN_GPMC_OEN_REN 0x894
83 #define AM335X_PIN_GPMC_WEN 0x898
84 #define AM335X_PIN_GPMC_BEN0_CLE 0x89c
85 #define AM335X_PIN_LCD_DATA0 0x8a0
86 #define AM335X_PIN_LCD_DATA1 0x8a4
87 #define AM335X_PIN_LCD_DATA2 0x8a8
88 #define AM335X_PIN_LCD_DATA3 0x8ac
89 #define AM335X_PIN_LCD_DATA4 0x8b0
90 #define AM335X_PIN_LCD_DATA5 0x8b4
91 #define AM335X_PIN_LCD_DATA6 0x8b8
92 #define AM335X_PIN_LCD_DATA7 0x8bc
93 #define AM335X_PIN_LCD_DATA8 0x8c0
94 #define AM335X_PIN_LCD_DATA9 0x8c4
95 #define AM335X_PIN_LCD_DATA10 0x8c8
96 #define AM335X_PIN_LCD_DATA11 0x8cc
97 #define AM335X_PIN_LCD_DATA12 0x8d0
98 #define AM335X_PIN_LCD_DATA13 0x8d4
99 #define AM335X_PIN_LCD_DATA14 0x8d8
100 #define AM335X_PIN_LCD_DATA15 0x8dc
101 #define AM335X_PIN_LCD_VSYNC 0x8e0
102 #define AM335X_PIN_LCD_HSYNC 0x8e4
103 #define AM335X_PIN_LCD_PCLK 0x8e8
104 #define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec
105 #define AM335X_PIN_MMC0_DAT3 0x8f0
106 #define AM335X_PIN_MMC0_DAT2 0x8f4
107 #define AM335X_PIN_MMC0_DAT1 0x8f8
108 #define AM335X_PIN_MMC0_DAT0 0x8fc
109 #define AM335X_PIN_MMC0_CLK 0x900
110 #define AM335X_PIN_MMC0_CMD 0x904
111 #define AM335X_PIN_MII1_COL 0x908
112 #define AM335X_PIN_MII1_CRS 0x90c
113 #define AM335X_PIN_MII1_RX_ER 0x910
114 #define AM335X_PIN_MII1_TX_EN 0x914
115 #define AM335X_PIN_MII1_RX_DV 0x918
116 #define AM335X_PIN_MII1_TXD3 0x91c
117 #define AM335X_PIN_MII1_TXD2 0x920
118 #define AM335X_PIN_MII1_TXD1 0x924
119 #define AM335X_PIN_MII1_TXD0 0x928
120 #define AM335X_PIN_MII1_TX_CLK 0x92c
121 #define AM335X_PIN_MII1_RX_CLK 0x930
122 #define AM335X_PIN_MII1_RXD3 0x934
123 #define AM335X_PIN_MII1_RXD2 0x938
124 #define AM335X_PIN_MII1_RXD1 0x93c
125 #define AM335X_PIN_MII1_RXD0 0x940
126 #define AM335X_PIN_RMII1_REF_CLK 0x944
127 #define AM335X_PIN_MDIO 0x948
128 #define AM335X_PIN_MDC 0x94c
129 #define AM335X_PIN_SPI0_SCLK 0x950
130 #define AM335X_PIN_SPI0_D0 0x954
131 #define AM335X_PIN_SPI0_D1 0x958
132 #define AM335X_PIN_SPI0_CS0 0x95c
133 #define AM335X_PIN_SPI0_CS1 0x960
134 #define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964
135 #define AM335X_PIN_UART0_CTSN 0x968
136 #define AM335X_PIN_UART0_RTSN 0x96c
137 #define AM335X_PIN_UART0_RXD 0x970
138 #define AM335X_PIN_UART0_TXD 0x974
139 #define AM335X_PIN_UART1_CTSN 0x978
140 #define AM335X_PIN_UART1_RTSN 0x97c
141 #define AM335X_PIN_UART1_RXD 0x980
142 #define AM335X_PIN_UART1_TXD 0x984
143 #define AM335X_PIN_I2C0_SDA 0x988
144 #define AM335X_PIN_I2C0_SCL 0x98c
145 #define AM335X_PIN_MCASP0_ACLKX 0x990
146 #define AM335X_PIN_MCASP0_FSX 0x994
147 #define AM335X_PIN_MCASP0_AXR0 0x998
148 #define AM335X_PIN_MCASP0_AHCLKR 0x99c
149 #define AM335X_PIN_MCASP0_ACLKR 0x9a0
150 #define AM335X_PIN_MCASP0_FSR 0x9a4
151 #define AM335X_PIN_MCASP0_AXR1 0x9a8
152 #define AM335X_PIN_MCASP0_AHCLKX 0x9ac
153 #define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0
154 #define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4
155 #define AM335X_PIN_WARMRSTN 0x9b8
156 #define AM335X_PIN_NNMI 0x9c0
157 #define AM335X_PIN_TMS 0x9d0
158 #define AM335X_PIN_TDI 0x9d4
159 #define AM335X_PIN_TDO 0x9d8
160 #define AM335X_PIN_TCK 0x9dc
161 #define AM335X_PIN_TRSTN 0x9e0
162 #define AM335X_PIN_EMU0 0x9e4
163 #define AM335X_PIN_EMU1 0x9e8
164 #define AM335X_PIN_RTC_PWRONRSTN 0x9f8
165 #define AM335X_PIN_PMIC_POWER_EN 0x9fc
166 #define AM335X_PIN_EXT_WAKEUP 0xa00
167 #define AM335X_PIN_USB0_DRVVBUS 0xa1c
168 #define AM335X_PIN_USB1_DRVVBUS 0xa34
170 #define AM335X_PIN_OFFSET_MAX 0x0a34U
172 #endif