| blob | 644760bf5725b560786a65e3c8ffd411bd47baf6 |
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Device Tree defines for Lochnagar pinctrl
4 *
5 * Copyright (c) 2018 Cirrus Logic, Inc. and
6 * Cirrus Logic International Semiconductor Ltd.
7 *
8 * Author: Charles Keepax <ckeepax@opensource.cirrus.com>
9 */
11 #ifndef DT_BINDINGS_PINCTRL_LOCHNAGAR_H
12 #define DT_BINDINGS_PINCTRL_LOCHNAGAR_H
14 #define LOCHNAGAR1_PIN_CDC_RESET 0
15 #define LOCHNAGAR1_PIN_DSP_RESET 1
16 #define LOCHNAGAR1_PIN_CDC_CIF1MODE 2
17 #define LOCHNAGAR1_PIN_NUM_GPIOS 3
19 #define LOCHNAGAR2_PIN_CDC_RESET 0
20 #define LOCHNAGAR2_PIN_DSP_RESET 1
21 #define LOCHNAGAR2_PIN_CDC_CIF1MODE 2
22 #define LOCHNAGAR2_PIN_CDC_LDOENA 3
23 #define LOCHNAGAR2_PIN_SPDIF_HWMODE 4
24 #define LOCHNAGAR2_PIN_SPDIF_RESET 5
25 #define LOCHNAGAR2_PIN_FPGA_GPIO1 6
26 #define LOCHNAGAR2_PIN_FPGA_GPIO2 7
27 #define LOCHNAGAR2_PIN_FPGA_GPIO3 8
28 #define LOCHNAGAR2_PIN_FPGA_GPIO4 9
29 #define LOCHNAGAR2_PIN_FPGA_GPIO5 10
30 #define LOCHNAGAR2_PIN_FPGA_GPIO6 11
31 #define LOCHNAGAR2_PIN_CDC_GPIO1 12
32 #define LOCHNAGAR2_PIN_CDC_GPIO2 13
33 #define LOCHNAGAR2_PIN_CDC_GPIO3 14
34 #define LOCHNAGAR2_PIN_CDC_GPIO4 15
35 #define LOCHNAGAR2_PIN_CDC_GPIO5 16
36 #define LOCHNAGAR2_PIN_CDC_GPIO6 17
37 #define LOCHNAGAR2_PIN_CDC_GPIO7 18
38 #define LOCHNAGAR2_PIN_CDC_GPIO8 19
39 #define LOCHNAGAR2_PIN_DSP_GPIO1 20
40 #define LOCHNAGAR2_PIN_DSP_GPIO2 21
41 #define LOCHNAGAR2_PIN_DSP_GPIO3 22
42 #define LOCHNAGAR2_PIN_DSP_GPIO4 23
43 #define LOCHNAGAR2_PIN_DSP_GPIO5 24
44 #define LOCHNAGAR2_PIN_DSP_GPIO6 25
45 #define LOCHNAGAR2_PIN_GF_GPIO2 26
46 #define LOCHNAGAR2_PIN_GF_GPIO3 27
47 #define LOCHNAGAR2_PIN_GF_GPIO7 28
48 #define LOCHNAGAR2_PIN_CDC_AIF1_BCLK 29
49 #define LOCHNAGAR2_PIN_CDC_AIF1_RXDAT 30
50 #define LOCHNAGAR2_PIN_CDC_AIF1_LRCLK 31
51 #define LOCHNAGAR2_PIN_CDC_AIF1_TXDAT 32
52 #define LOCHNAGAR2_PIN_CDC_AIF2_BCLK 33
53 #define LOCHNAGAR2_PIN_CDC_AIF2_RXDAT 34
54 #define LOCHNAGAR2_PIN_CDC_AIF2_LRCLK 35
55 #define LOCHNAGAR2_PIN_CDC_AIF2_TXDAT 36
56 #define LOCHNAGAR2_PIN_CDC_AIF3_BCLK 37
57 #define LOCHNAGAR2_PIN_CDC_AIF3_RXDAT 38
58 #define LOCHNAGAR2_PIN_CDC_AIF3_LRCLK 39
59 #define LOCHNAGAR2_PIN_CDC_AIF3_TXDAT 40
60 #define LOCHNAGAR2_PIN_DSP_AIF1_BCLK 41
61 #define LOCHNAGAR2_PIN_DSP_AIF1_RXDAT 42
62 #define LOCHNAGAR2_PIN_DSP_AIF1_LRCLK 43
63 #define LOCHNAGAR2_PIN_DSP_AIF1_TXDAT 44
64 #define LOCHNAGAR2_PIN_DSP_AIF2_BCLK 45
65 #define LOCHNAGAR2_PIN_DSP_AIF2_RXDAT 46
66 #define LOCHNAGAR2_PIN_DSP_AIF2_LRCLK 47
67 #define LOCHNAGAR2_PIN_DSP_AIF2_TXDAT 48
68 #define LOCHNAGAR2_PIN_PSIA1_BCLK 49
69 #define LOCHNAGAR2_PIN_PSIA1_RXDAT 50
70 #define LOCHNAGAR2_PIN_PSIA1_LRCLK 51
71 #define LOCHNAGAR2_PIN_PSIA1_TXDAT 52
72 #define LOCHNAGAR2_PIN_PSIA2_BCLK 53
73 #define LOCHNAGAR2_PIN_PSIA2_RXDAT 54
74 #define LOCHNAGAR2_PIN_PSIA2_LRCLK 55
75 #define LOCHNAGAR2_PIN_PSIA2_TXDAT 56
76 #define LOCHNAGAR2_PIN_GF_AIF3_BCLK 57
77 #define LOCHNAGAR2_PIN_GF_AIF3_RXDAT 58
78 #define LOCHNAGAR2_PIN_GF_AIF3_LRCLK 59
79 #define LOCHNAGAR2_PIN_GF_AIF3_TXDAT 60
80 #define LOCHNAGAR2_PIN_GF_AIF4_BCLK 61
81 #define LOCHNAGAR2_PIN_GF_AIF4_RXDAT 62
82 #define LOCHNAGAR2_PIN_GF_AIF4_LRCLK 63
83 #define LOCHNAGAR2_PIN_GF_AIF4_TXDAT 64
84 #define LOCHNAGAR2_PIN_GF_AIF1_BCLK 65
85 #define LOCHNAGAR2_PIN_GF_AIF1_RXDAT 66
86 #define LOCHNAGAR2_PIN_GF_AIF1_LRCLK 67
87 #define LOCHNAGAR2_PIN_GF_AIF1_TXDAT 68
88 #define LOCHNAGAR2_PIN_GF_AIF2_BCLK 69
89 #define LOCHNAGAR2_PIN_GF_AIF2_RXDAT 70
90 #define LOCHNAGAR2_PIN_GF_AIF2_LRCLK 71
91 #define LOCHNAGAR2_PIN_GF_AIF2_TXDAT 72
92 #define LOCHNAGAR2_PIN_DSP_UART1_RX 73
93 #define LOCHNAGAR2_PIN_DSP_UART1_TX 74
94 #define LOCHNAGAR2_PIN_DSP_UART2_RX 75
95 #define LOCHNAGAR2_PIN_DSP_UART2_TX 76
96 #define LOCHNAGAR2_PIN_GF_UART2_RX 77
97 #define LOCHNAGAR2_PIN_GF_UART2_TX 78
98 #define LOCHNAGAR2_PIN_USB_UART_RX 79
99 #define LOCHNAGAR2_PIN_CDC_PDMCLK1 80
100 #define LOCHNAGAR2_PIN_CDC_PDMDAT1 81
101 #define LOCHNAGAR2_PIN_CDC_PDMCLK2 82
102 #define LOCHNAGAR2_PIN_CDC_PDMDAT2 83
103 #define LOCHNAGAR2_PIN_CDC_DMICCLK1 84
104 #define LOCHNAGAR2_PIN_CDC_DMICDAT1 85
105 #define LOCHNAGAR2_PIN_CDC_DMICCLK2 86
106 #define LOCHNAGAR2_PIN_CDC_DMICDAT2 87
107 #define LOCHNAGAR2_PIN_CDC_DMICCLK3 88
108 #define LOCHNAGAR2_PIN_CDC_DMICDAT3 89
109 #define LOCHNAGAR2_PIN_CDC_DMICCLK4 90
110 #define LOCHNAGAR2_PIN_CDC_DMICDAT4 91
111 #define LOCHNAGAR2_PIN_DSP_DMICCLK1 92
112 #define LOCHNAGAR2_PIN_DSP_DMICDAT1 93
113 #define LOCHNAGAR2_PIN_DSP_DMICCLK2 94
114 #define LOCHNAGAR2_PIN_DSP_DMICDAT2 95
115 #define LOCHNAGAR2_PIN_I2C2_SCL 96
116 #define LOCHNAGAR2_PIN_I2C2_SDA 97
117 #define LOCHNAGAR2_PIN_I2C3_SCL 98
118 #define LOCHNAGAR2_PIN_I2C3_SDA 99
119 #define LOCHNAGAR2_PIN_I2C4_SCL 100
120 #define LOCHNAGAR2_PIN_I2C4_SDA 101
121 #define LOCHNAGAR2_PIN_DSP_STANDBY 102
122 #define LOCHNAGAR2_PIN_CDC_MCLK1 103
123 #define LOCHNAGAR2_PIN_CDC_MCLK2 104
124 #define LOCHNAGAR2_PIN_DSP_CLKIN 105
125 #define LOCHNAGAR2_PIN_PSIA1_MCLK 106
126 #define LOCHNAGAR2_PIN_PSIA2_MCLK 107
127 #define LOCHNAGAR2_PIN_GF_GPIO1 108
128 #define LOCHNAGAR2_PIN_GF_GPIO5 109
129 #define LOCHNAGAR2_PIN_DSP_GPIO20 110
130 #define LOCHNAGAR2_PIN_NUM_GPIOS 111
132 #endif