include/uapi/drm/etnaviv_drm.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 /*
   3  * Copyright (C) 2015 Etnaviv Project
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __ETNAVIV_DRM_H__
  19 #define __ETNAVIV_DRM_H__
  20
  21 #include "drm.h"
  22
  23 #if defined(__cplusplus)
  24 extern "C" {
  25 #endif
  26
  27 /* Please note that modifications to all structs defined here are
  28  * subject to backwards-compatibility constraints:
  29  *  1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
  30  *     user/kernel compatibility
  31  *  2) Keep fields aligned to their size
  32  *  3) Because of how drm_ioctl() works, we can add new fields at
  33  *     the end of an ioctl if some care is taken: drm_ioctl() will
  34  *     zero out the new fields at the tail of the ioctl, so a zero
  35  *     value should have a backwards compatible meaning.  And for
  36  *     output params, userspace won't see the newly added output
  37  *     fields.. so that has to be somehow ok.
  38  */
  39
  40 /* timeouts are specified in clock-monotonic absolute times (to simplify
  41  * restarting interrupted ioctls).  The following struct is logically the
  42  * same as 'struct timespec' but 32/64b ABI safe.
  43  */
  44 struct drm_etnaviv_timespec {
  45         __s64 tv_sec;          /* seconds */
  46         __s64 tv_nsec;         /* nanoseconds */
  47 };
  48
  49 #define ETNAVIV_PARAM_GPU_MODEL                     0x01
  50 #define ETNAVIV_PARAM_GPU_REVISION                  0x02
  51 #define ETNAVIV_PARAM_GPU_FEATURES_0                0x03
  52 #define ETNAVIV_PARAM_GPU_FEATURES_1                0x04
  53 #define ETNAVIV_PARAM_GPU_FEATURES_2                0x05
  54 #define ETNAVIV_PARAM_GPU_FEATURES_3                0x06
  55 #define ETNAVIV_PARAM_GPU_FEATURES_4                0x07
  56 #define ETNAVIV_PARAM_GPU_FEATURES_5                0x08
  57 #define ETNAVIV_PARAM_GPU_FEATURES_6                0x09
  58 #define ETNAVIV_PARAM_GPU_FEATURES_7                0x0a
  59 #define ETNAVIV_PARAM_GPU_FEATURES_8                0x0b
  60 #define ETNAVIV_PARAM_GPU_FEATURES_9                0x0c
  61 #define ETNAVIV_PARAM_GPU_FEATURES_10               0x0d
  62 #define ETNAVIV_PARAM_GPU_FEATURES_11               0x0e
  63 #define ETNAVIV_PARAM_GPU_FEATURES_12               0x0f
  64
  65 #define ETNAVIV_PARAM_GPU_STREAM_COUNT              0x10
  66 #define ETNAVIV_PARAM_GPU_REGISTER_MAX              0x11
  67 #define ETNAVIV_PARAM_GPU_THREAD_COUNT              0x12
  68 #define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE         0x13
  69 #define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT         0x14
  70 #define ETNAVIV_PARAM_GPU_PIXEL_PIPES               0x15
  71 #define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
  72 #define ETNAVIV_PARAM_GPU_BUFFER_SIZE               0x17
  73 #define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT         0x18
  74 #define ETNAVIV_PARAM_GPU_NUM_CONSTANTS             0x19
  75 #define ETNAVIV_PARAM_GPU_NUM_VARYINGS              0x1a
  76 #define ETNAVIV_PARAM_SOFTPIN_START_ADDR            0x1b
  77
  78 #define ETNA_MAX_PIPES 4
  79
  80 struct drm_etnaviv_param {
  81         __u32 pipe;           /* in */
  82         __u32 param;          /* in, ETNAVIV_PARAM_x */
  83         __u64 value;          /* out (get_param) or in (set_param) */
  84 };
  85
  86 /*
  87  * GEM buffers:
  88  */
  89
  90 #define ETNA_BO_CACHE_MASK   0x000f0000
  91 /* cache modes */
  92 #define ETNA_BO_CACHED       0x00010000
  93 #define ETNA_BO_WC           0x00020000
  94 #define ETNA_BO_UNCACHED     0x00040000
  95 /* map flags */
  96 #define ETNA_BO_FORCE_MMU    0x00100000
  97
  98 struct drm_etnaviv_gem_new {
  99         __u64 size;           /* in */
 100         __u32 flags;          /* in, mask of ETNA_BO_x */
 101         __u32 handle;         /* out */
 102 };
 103
 104 struct drm_etnaviv_gem_info {
 105         __u32 handle;         /* in */
 106         __u32 pad;
 107         __u64 offset;         /* out, offset to pass to mmap() */
 108 };
 109
 110 #define ETNA_PREP_READ        0x01
 111 #define ETNA_PREP_WRITE       0x02
 112 #define ETNA_PREP_NOSYNC      0x04
 113
 114 struct drm_etnaviv_gem_cpu_prep {
 115         __u32 handle;         /* in */
 116         __u32 op;             /* in, mask of ETNA_PREP_x */
 117         struct drm_etnaviv_timespec timeout;   /* in */
 118 };
 119
 120 struct drm_etnaviv_gem_cpu_fini {
 121         __u32 handle;         /* in */
 122         __u32 flags;          /* in, placeholder for now, no defined values */
 123 };
 124
 125 /*
 126  * Cmdstream Submission:
 127  */
 128
 129 /* The value written into the cmdstream is logically:
 130  * relocbuf->gpuaddr + reloc_offset
 131  *
 132  * NOTE that reloc's must be sorted by order of increasing submit_offset,
 133  * otherwise EINVAL.
 134  */
 135 struct drm_etnaviv_gem_submit_reloc {
 136         __u32 submit_offset;  /* in, offset from submit_bo */
 137         __u32 reloc_idx;      /* in, index of reloc_bo buffer */
 138         __u64 reloc_offset;   /* in, offset from start of reloc_bo */
 139         __u32 flags;          /* in, placeholder for now, no defined values */
 140 };
 141
 142 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
 143  * cmdstream buffer(s) themselves or reloc entries) has one (and only
 144  * one) entry in the submit->bos[] table.
 145  *
 146  * As a optimization, the current buffer (gpu virtual address) can be
 147  * passed back through the 'presumed' field.  If on a subsequent reloc,
 148  * userspace passes back a 'presumed' address that is still valid,
 149  * then patching the cmdstream for this entry is skipped.  This can
 150  * avoid kernel needing to map/access the cmdstream bo in the common
 151  * case.
 152  * If the submit is a softpin submit (ETNA_SUBMIT_SOFTPIN) the 'presumed'
 153  * field is interpreted as the fixed location to map the bo into the gpu
 154  * virtual address space. If the kernel is unable to map the buffer at
 155  * this location the submit will fail. This means userspace is responsible
 156  * for the whole gpu virtual address management.
 157  */
 158 #define ETNA_SUBMIT_BO_READ             0x0001
 159 #define ETNA_SUBMIT_BO_WRITE            0x0002
 160 struct drm_etnaviv_gem_submit_bo {
 161         __u32 flags;          /* in, mask of ETNA_SUBMIT_BO_x */
 162         __u32 handle;         /* in, GEM handle */
 163         __u64 presumed;       /* in/out, presumed buffer address */
 164 };
 165
 166 /* performance monitor request (pmr) */
 167 #define ETNA_PM_PROCESS_PRE             0x0001
 168 #define ETNA_PM_PROCESS_POST            0x0002
 169 struct drm_etnaviv_gem_submit_pmr {
 170         __u32 flags;          /* in, when to process request (ETNA_PM_PROCESS_x) */
 171         __u8  domain;         /* in, pm domain */
 172         __u8  pad;
 173         __u16 signal;         /* in, pm signal */
 174         __u32 sequence;       /* in, sequence number */
 175         __u32 read_offset;    /* in, offset from read_bo */
 176         __u32 read_idx;       /* in, index of read_bo buffer */
 177 };
 178
 179 /* Each cmdstream submit consists of a table of buffers involved, and
 180  * one or more cmdstream buffers.  This allows for conditional execution
 181  * (context-restore), and IB buffers needed for per tile/bin draw cmds.
 182  */
 183 #define ETNA_SUBMIT_NO_IMPLICIT         0x0001
 184 #define ETNA_SUBMIT_FENCE_FD_IN         0x0002
 185 #define ETNA_SUBMIT_FENCE_FD_OUT        0x0004
 186 #define ETNA_SUBMIT_SOFTPIN             0x0008
 187 #define ETNA_SUBMIT_FLAGS               (ETNA_SUBMIT_NO_IMPLICIT | \
 188                                          ETNA_SUBMIT_FENCE_FD_IN | \
 189                                          ETNA_SUBMIT_FENCE_FD_OUT| \
 190                                          ETNA_SUBMIT_SOFTPIN)
 191 #define ETNA_PIPE_3D      0x00
 192 #define ETNA_PIPE_2D      0x01
 193 #define ETNA_PIPE_VG      0x02
 194 struct drm_etnaviv_gem_submit {
 195         __u32 fence;          /* out */
 196         __u32 pipe;           /* in */
 197         __u32 exec_state;     /* in, initial execution state (ETNA_PIPE_x) */
 198         __u32 nr_bos;         /* in, number of submit_bo's */
 199         __u32 nr_relocs;      /* in, number of submit_reloc's */
 200         __u32 stream_size;    /* in, cmdstream size */
 201         __u64 bos;            /* in, ptr to array of submit_bo's */
 202         __u64 relocs;         /* in, ptr to array of submit_reloc's */
 203         __u64 stream;         /* in, ptr to cmdstream */
 204         __u32 flags;          /* in, mask of ETNA_SUBMIT_x */
 205         __s32 fence_fd;       /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
 206         __u64 pmrs;           /* in, ptr to array of submit_pmr's */
 207         __u32 nr_pmrs;        /* in, number of submit_pmr's */
 208         __u32 pad;
 209 };
 210
 211 /* The normal way to synchronize with the GPU is just to CPU_PREP on
 212  * a buffer if you need to access it from the CPU (other cmdstream
 213  * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
 214  * handle the required synchronization under the hood).  This ioctl
 215  * mainly just exists as a way to implement the gallium pipe_fence
 216  * APIs without requiring a dummy bo to synchronize on.
 217  */
 218 #define ETNA_WAIT_NONBLOCK      0x01
 219 struct drm_etnaviv_wait_fence {
 220         __u32 pipe;           /* in */
 221         __u32 fence;          /* in */
 222         __u32 flags;          /* in, mask of ETNA_WAIT_x */
 223         __u32 pad;
 224         struct drm_etnaviv_timespec timeout;   /* in */
 225 };
 226
 227 #define ETNA_USERPTR_READ       0x01
 228 #define ETNA_USERPTR_WRITE      0x02
 229 struct drm_etnaviv_gem_userptr {
 230         __u64 user_ptr; /* in, page aligned user pointer */
 231         __u64 user_size;        /* in, page aligned user size */
 232         __u32 flags;            /* in, flags */
 233         __u32 handle;   /* out, non-zero handle */
 234 };
 235
 236 struct drm_etnaviv_gem_wait {
 237         __u32 pipe;                             /* in */
 238         __u32 handle;                           /* in, bo to be waited for */
 239         __u32 flags;                            /* in, mask of ETNA_WAIT_x  */
 240         __u32 pad;
 241         struct drm_etnaviv_timespec timeout;    /* in */
 242 };
 243
 244 /*
 245  * Performance Monitor (PM):
 246  */
 247
 248 struct drm_etnaviv_pm_domain {
 249         __u32 pipe;       /* in */
 250         __u8  iter;       /* in/out, select pm domain at index iter */
 251         __u8  id;         /* out, id of domain */
 252         __u16 nr_signals; /* out, how many signals does this domain provide */
 253         char  name[64];   /* out, name of domain */
 254 };
 255
 256 struct drm_etnaviv_pm_signal {
 257         __u32 pipe;       /* in */
 258         __u8  domain;     /* in, pm domain index */
 259         __u8  pad;
 260         __u16 iter;       /* in/out, select pm source at index iter */
 261         __u16 id;         /* out, id of signal */
 262         char  name[64];   /* out, name of domain */
 263 };
 264
 265 #define DRM_ETNAVIV_GET_PARAM          0x00
 266 /* placeholder:
 267 #define DRM_ETNAVIV_SET_PARAM          0x01
 268  */
 269 #define DRM_ETNAVIV_GEM_NEW            0x02
 270 #define DRM_ETNAVIV_GEM_INFO           0x03
 271 #define DRM_ETNAVIV_GEM_CPU_PREP       0x04
 272 #define DRM_ETNAVIV_GEM_CPU_FINI       0x05
 273 #define DRM_ETNAVIV_GEM_SUBMIT         0x06
 274 #define DRM_ETNAVIV_WAIT_FENCE         0x07
 275 #define DRM_ETNAVIV_GEM_USERPTR        0x08
 276 #define DRM_ETNAVIV_GEM_WAIT           0x09
 277 #define DRM_ETNAVIV_PM_QUERY_DOM       0x0a
 278 #define DRM_ETNAVIV_PM_QUERY_SIG       0x0b
 279 #define DRM_ETNAVIV_NUM_IOCTLS         0x0c
 280
 281 #define DRM_IOCTL_ETNAVIV_GET_PARAM    DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
 282 #define DRM_IOCTL_ETNAVIV_GEM_NEW      DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
 283 #define DRM_IOCTL_ETNAVIV_GEM_INFO     DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
 284 #define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
 285 #define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
 286 #define DRM_IOCTL_ETNAVIV_GEM_SUBMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
 287 #define DRM_IOCTL_ETNAVIV_WAIT_FENCE   DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
 288 #define DRM_IOCTL_ETNAVIV_GEM_USERPTR  DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
 289 #define DRM_IOCTL_ETNAVIV_GEM_WAIT     DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
 290 #define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
 291 #define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
 292
 293 #if defined(__cplusplus)
 294 }
 295 #endif
 296
 297 #endif /* __ETNAVIV_DRM_H__ */