include/uapi/misc/habanalabs.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
   2  *
   3  * Copyright 2016-2020 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 #ifndef HABANALABS_H_
   9 #define HABANALABS_H_
  10
  11 #include <linux/types.h>
  12 #include <linux/ioctl.h>
  13
  14 /*
  15  * Defines that are asic-specific but constitutes as ABI between kernel driver
  16  * and userspace
  17  */
  18 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START          0x8000  /* 32KB */
  19 #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START      0x80    /* 128 bytes */
  20
  21 /*
  22  * 128 SOBs reserved for collective wait
  23  * 16 SOBs reserved for sync stream
  24  */
  25 #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT           144
  26
  27 /*
  28  * 64 monitors reserved for collective wait
  29  * 8 monitors reserved for sync stream
  30  */
  31 #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR               72
  32
  33 /*
  34  * Goya queue Numbering
  35  *
  36  * The external queues (PCI DMA channels) MUST be before the internal queues
  37  * and each group (PCI DMA channels and internal) must be contiguous inside
  38  * itself but there can be a gap between the two groups (although not
  39  * recommended)
  40  */
  41
  42 enum goya_queue_id {
  43         GOYA_QUEUE_ID_DMA_0 = 0,
  44         GOYA_QUEUE_ID_DMA_1 = 1,
  45         GOYA_QUEUE_ID_DMA_2 = 2,
  46         GOYA_QUEUE_ID_DMA_3 = 3,
  47         GOYA_QUEUE_ID_DMA_4 = 4,
  48         GOYA_QUEUE_ID_CPU_PQ = 5,
  49         GOYA_QUEUE_ID_MME = 6,  /* Internal queues start here */
  50         GOYA_QUEUE_ID_TPC0 = 7,
  51         GOYA_QUEUE_ID_TPC1 = 8,
  52         GOYA_QUEUE_ID_TPC2 = 9,
  53         GOYA_QUEUE_ID_TPC3 = 10,
  54         GOYA_QUEUE_ID_TPC4 = 11,
  55         GOYA_QUEUE_ID_TPC5 = 12,
  56         GOYA_QUEUE_ID_TPC6 = 13,
  57         GOYA_QUEUE_ID_TPC7 = 14,
  58         GOYA_QUEUE_ID_SIZE
  59 };
  60
  61 /*
  62  * Gaudi queue Numbering
  63  * External queues (PCI DMA channels) are DMA_0_*, DMA_1_* and DMA_5_*.
  64  * Except one CPU queue, all the rest are internal queues.
  65  */
  66
  67 enum gaudi_queue_id {
  68         GAUDI_QUEUE_ID_DMA_0_0 = 0,     /* external */
  69         GAUDI_QUEUE_ID_DMA_0_1 = 1,     /* external */
  70         GAUDI_QUEUE_ID_DMA_0_2 = 2,     /* external */
  71         GAUDI_QUEUE_ID_DMA_0_3 = 3,     /* external */
  72         GAUDI_QUEUE_ID_DMA_1_0 = 4,     /* external */
  73         GAUDI_QUEUE_ID_DMA_1_1 = 5,     /* external */
  74         GAUDI_QUEUE_ID_DMA_1_2 = 6,     /* external */
  75         GAUDI_QUEUE_ID_DMA_1_3 = 7,     /* external */
  76         GAUDI_QUEUE_ID_CPU_PQ = 8,      /* CPU */
  77         GAUDI_QUEUE_ID_DMA_2_0 = 9,     /* internal */
  78         GAUDI_QUEUE_ID_DMA_2_1 = 10,    /* internal */
  79         GAUDI_QUEUE_ID_DMA_2_2 = 11,    /* internal */
  80         GAUDI_QUEUE_ID_DMA_2_3 = 12,    /* internal */
  81         GAUDI_QUEUE_ID_DMA_3_0 = 13,    /* internal */
  82         GAUDI_QUEUE_ID_DMA_3_1 = 14,    /* internal */
  83         GAUDI_QUEUE_ID_DMA_3_2 = 15,    /* internal */
  84         GAUDI_QUEUE_ID_DMA_3_3 = 16,    /* internal */
  85         GAUDI_QUEUE_ID_DMA_4_0 = 17,    /* internal */
  86         GAUDI_QUEUE_ID_DMA_4_1 = 18,    /* internal */
  87         GAUDI_QUEUE_ID_DMA_4_2 = 19,    /* internal */
  88         GAUDI_QUEUE_ID_DMA_4_3 = 20,    /* internal */
  89         GAUDI_QUEUE_ID_DMA_5_0 = 21,    /* internal */
  90         GAUDI_QUEUE_ID_DMA_5_1 = 22,    /* internal */
  91         GAUDI_QUEUE_ID_DMA_5_2 = 23,    /* internal */
  92         GAUDI_QUEUE_ID_DMA_5_3 = 24,    /* internal */
  93         GAUDI_QUEUE_ID_DMA_6_0 = 25,    /* internal */
  94         GAUDI_QUEUE_ID_DMA_6_1 = 26,    /* internal */
  95         GAUDI_QUEUE_ID_DMA_6_2 = 27,    /* internal */
  96         GAUDI_QUEUE_ID_DMA_6_3 = 28,    /* internal */
  97         GAUDI_QUEUE_ID_DMA_7_0 = 29,    /* internal */
  98         GAUDI_QUEUE_ID_DMA_7_1 = 30,    /* internal */
  99         GAUDI_QUEUE_ID_DMA_7_2 = 31,    /* internal */
 100         GAUDI_QUEUE_ID_DMA_7_3 = 32,    /* internal */
 101         GAUDI_QUEUE_ID_MME_0_0 = 33,    /* internal */
 102         GAUDI_QUEUE_ID_MME_0_1 = 34,    /* internal */
 103         GAUDI_QUEUE_ID_MME_0_2 = 35,    /* internal */
 104         GAUDI_QUEUE_ID_MME_0_3 = 36,    /* internal */
 105         GAUDI_QUEUE_ID_MME_1_0 = 37,    /* internal */
 106         GAUDI_QUEUE_ID_MME_1_1 = 38,    /* internal */
 107         GAUDI_QUEUE_ID_MME_1_2 = 39,    /* internal */
 108         GAUDI_QUEUE_ID_MME_1_3 = 40,    /* internal */
 109         GAUDI_QUEUE_ID_TPC_0_0 = 41,    /* internal */
 110         GAUDI_QUEUE_ID_TPC_0_1 = 42,    /* internal */
 111         GAUDI_QUEUE_ID_TPC_0_2 = 43,    /* internal */
 112         GAUDI_QUEUE_ID_TPC_0_3 = 44,    /* internal */
 113         GAUDI_QUEUE_ID_TPC_1_0 = 45,    /* internal */
 114         GAUDI_QUEUE_ID_TPC_1_1 = 46,    /* internal */
 115         GAUDI_QUEUE_ID_TPC_1_2 = 47,    /* internal */
 116         GAUDI_QUEUE_ID_TPC_1_3 = 48,    /* internal */
 117         GAUDI_QUEUE_ID_TPC_2_0 = 49,    /* internal */
 118         GAUDI_QUEUE_ID_TPC_2_1 = 50,    /* internal */
 119         GAUDI_QUEUE_ID_TPC_2_2 = 51,    /* internal */
 120         GAUDI_QUEUE_ID_TPC_2_3 = 52,    /* internal */
 121         GAUDI_QUEUE_ID_TPC_3_0 = 53,    /* internal */
 122         GAUDI_QUEUE_ID_TPC_3_1 = 54,    /* internal */
 123         GAUDI_QUEUE_ID_TPC_3_2 = 55,    /* internal */
 124         GAUDI_QUEUE_ID_TPC_3_3 = 56,    /* internal */
 125         GAUDI_QUEUE_ID_TPC_4_0 = 57,    /* internal */
 126         GAUDI_QUEUE_ID_TPC_4_1 = 58,    /* internal */
 127         GAUDI_QUEUE_ID_TPC_4_2 = 59,    /* internal */
 128         GAUDI_QUEUE_ID_TPC_4_3 = 60,    /* internal */
 129         GAUDI_QUEUE_ID_TPC_5_0 = 61,    /* internal */
 130         GAUDI_QUEUE_ID_TPC_5_1 = 62,    /* internal */
 131         GAUDI_QUEUE_ID_TPC_5_2 = 63,    /* internal */
 132         GAUDI_QUEUE_ID_TPC_5_3 = 64,    /* internal */
 133         GAUDI_QUEUE_ID_TPC_6_0 = 65,    /* internal */
 134         GAUDI_QUEUE_ID_TPC_6_1 = 66,    /* internal */
 135         GAUDI_QUEUE_ID_TPC_6_2 = 67,    /* internal */
 136         GAUDI_QUEUE_ID_TPC_6_3 = 68,    /* internal */
 137         GAUDI_QUEUE_ID_TPC_7_0 = 69,    /* internal */
 138         GAUDI_QUEUE_ID_TPC_7_1 = 70,    /* internal */
 139         GAUDI_QUEUE_ID_TPC_7_2 = 71,    /* internal */
 140         GAUDI_QUEUE_ID_TPC_7_3 = 72,    /* internal */
 141         GAUDI_QUEUE_ID_NIC_0_0 = 73,    /* internal */
 142         GAUDI_QUEUE_ID_NIC_0_1 = 74,    /* internal */
 143         GAUDI_QUEUE_ID_NIC_0_2 = 75,    /* internal */
 144         GAUDI_QUEUE_ID_NIC_0_3 = 76,    /* internal */
 145         GAUDI_QUEUE_ID_NIC_1_0 = 77,    /* internal */
 146         GAUDI_QUEUE_ID_NIC_1_1 = 78,    /* internal */
 147         GAUDI_QUEUE_ID_NIC_1_2 = 79,    /* internal */
 148         GAUDI_QUEUE_ID_NIC_1_3 = 80,    /* internal */
 149         GAUDI_QUEUE_ID_NIC_2_0 = 81,    /* internal */
 150         GAUDI_QUEUE_ID_NIC_2_1 = 82,    /* internal */
 151         GAUDI_QUEUE_ID_NIC_2_2 = 83,    /* internal */
 152         GAUDI_QUEUE_ID_NIC_2_3 = 84,    /* internal */
 153         GAUDI_QUEUE_ID_NIC_3_0 = 85,    /* internal */
 154         GAUDI_QUEUE_ID_NIC_3_1 = 86,    /* internal */
 155         GAUDI_QUEUE_ID_NIC_3_2 = 87,    /* internal */
 156         GAUDI_QUEUE_ID_NIC_3_3 = 88,    /* internal */
 157         GAUDI_QUEUE_ID_NIC_4_0 = 89,    /* internal */
 158         GAUDI_QUEUE_ID_NIC_4_1 = 90,    /* internal */
 159         GAUDI_QUEUE_ID_NIC_4_2 = 91,    /* internal */
 160         GAUDI_QUEUE_ID_NIC_4_3 = 92,    /* internal */
 161         GAUDI_QUEUE_ID_NIC_5_0 = 93,    /* internal */
 162         GAUDI_QUEUE_ID_NIC_5_1 = 94,    /* internal */
 163         GAUDI_QUEUE_ID_NIC_5_2 = 95,    /* internal */
 164         GAUDI_QUEUE_ID_NIC_5_3 = 96,    /* internal */
 165         GAUDI_QUEUE_ID_NIC_6_0 = 97,    /* internal */
 166         GAUDI_QUEUE_ID_NIC_6_1 = 98,    /* internal */
 167         GAUDI_QUEUE_ID_NIC_6_2 = 99,    /* internal */
 168         GAUDI_QUEUE_ID_NIC_6_3 = 100,   /* internal */
 169         GAUDI_QUEUE_ID_NIC_7_0 = 101,   /* internal */
 170         GAUDI_QUEUE_ID_NIC_7_1 = 102,   /* internal */
 171         GAUDI_QUEUE_ID_NIC_7_2 = 103,   /* internal */
 172         GAUDI_QUEUE_ID_NIC_7_3 = 104,   /* internal */
 173         GAUDI_QUEUE_ID_NIC_8_0 = 105,   /* internal */
 174         GAUDI_QUEUE_ID_NIC_8_1 = 106,   /* internal */
 175         GAUDI_QUEUE_ID_NIC_8_2 = 107,   /* internal */
 176         GAUDI_QUEUE_ID_NIC_8_3 = 108,   /* internal */
 177         GAUDI_QUEUE_ID_NIC_9_0 = 109,   /* internal */
 178         GAUDI_QUEUE_ID_NIC_9_1 = 110,   /* internal */
 179         GAUDI_QUEUE_ID_NIC_9_2 = 111,   /* internal */
 180         GAUDI_QUEUE_ID_NIC_9_3 = 112,   /* internal */
 181         GAUDI_QUEUE_ID_SIZE
 182 };
 183
 184 /*
 185  * Engine Numbering
 186  *
 187  * Used in the "busy_engines_mask" field in `struct hl_info_hw_idle'
 188  */
 189
 190 enum goya_engine_id {
 191         GOYA_ENGINE_ID_DMA_0 = 0,
 192         GOYA_ENGINE_ID_DMA_1,
 193         GOYA_ENGINE_ID_DMA_2,
 194         GOYA_ENGINE_ID_DMA_3,
 195         GOYA_ENGINE_ID_DMA_4,
 196         GOYA_ENGINE_ID_MME_0,
 197         GOYA_ENGINE_ID_TPC_0,
 198         GOYA_ENGINE_ID_TPC_1,
 199         GOYA_ENGINE_ID_TPC_2,
 200         GOYA_ENGINE_ID_TPC_3,
 201         GOYA_ENGINE_ID_TPC_4,
 202         GOYA_ENGINE_ID_TPC_5,
 203         GOYA_ENGINE_ID_TPC_6,
 204         GOYA_ENGINE_ID_TPC_7,
 205         GOYA_ENGINE_ID_SIZE
 206 };
 207
 208 enum gaudi_engine_id {
 209         GAUDI_ENGINE_ID_DMA_0 = 0,
 210         GAUDI_ENGINE_ID_DMA_1,
 211         GAUDI_ENGINE_ID_DMA_2,
 212         GAUDI_ENGINE_ID_DMA_3,
 213         GAUDI_ENGINE_ID_DMA_4,
 214         GAUDI_ENGINE_ID_DMA_5,
 215         GAUDI_ENGINE_ID_DMA_6,
 216         GAUDI_ENGINE_ID_DMA_7,
 217         GAUDI_ENGINE_ID_MME_0,
 218         GAUDI_ENGINE_ID_MME_1,
 219         GAUDI_ENGINE_ID_MME_2,
 220         GAUDI_ENGINE_ID_MME_3,
 221         GAUDI_ENGINE_ID_TPC_0,
 222         GAUDI_ENGINE_ID_TPC_1,
 223         GAUDI_ENGINE_ID_TPC_2,
 224         GAUDI_ENGINE_ID_TPC_3,
 225         GAUDI_ENGINE_ID_TPC_4,
 226         GAUDI_ENGINE_ID_TPC_5,
 227         GAUDI_ENGINE_ID_TPC_6,
 228         GAUDI_ENGINE_ID_TPC_7,
 229         GAUDI_ENGINE_ID_NIC_0,
 230         GAUDI_ENGINE_ID_NIC_1,
 231         GAUDI_ENGINE_ID_NIC_2,
 232         GAUDI_ENGINE_ID_NIC_3,
 233         GAUDI_ENGINE_ID_NIC_4,
 234         GAUDI_ENGINE_ID_NIC_5,
 235         GAUDI_ENGINE_ID_NIC_6,
 236         GAUDI_ENGINE_ID_NIC_7,
 237         GAUDI_ENGINE_ID_NIC_8,
 238         GAUDI_ENGINE_ID_NIC_9,
 239         GAUDI_ENGINE_ID_SIZE
 240 };
 241
 242 enum hl_device_status {
 243         HL_DEVICE_STATUS_OPERATIONAL,
 244         HL_DEVICE_STATUS_IN_RESET,
 245         HL_DEVICE_STATUS_MALFUNCTION,
 246         HL_DEVICE_STATUS_NEEDS_RESET
 247 };
 248
 249 /* Opcode for management ioctl
 250  *
 251  * HW_IP_INFO            - Receive information about different IP blocks in the
 252  *                         device.
 253  * HL_INFO_HW_EVENTS     - Receive an array describing how many times each event
 254  *                         occurred since the last hard reset.
 255  * HL_INFO_DRAM_USAGE    - Retrieve the dram usage inside the device and of the
 256  *                         specific context. This is relevant only for devices
 257  *                         where the dram is managed by the kernel driver
 258  * HL_INFO_HW_IDLE       - Retrieve information about the idle status of each
 259  *                         internal engine.
 260  * HL_INFO_DEVICE_STATUS - Retrieve the device's status. This opcode doesn't
 261  *                         require an open context.
 262  * HL_INFO_DEVICE_UTILIZATION  - Retrieve the total utilization of the device
 263  *                               over the last period specified by the user.
 264  *                               The period can be between 100ms to 1s, in
 265  *                               resolution of 100ms. The return value is a
 266  *                               percentage of the utilization rate.
 267  * HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each
 268  *                               event occurred since the driver was loaded.
 269  * HL_INFO_CLK_RATE            - Retrieve the current and maximum clock rate
 270  *                               of the device in MHz. The maximum clock rate is
 271  *                               configurable via sysfs parameter
 272  * HL_INFO_RESET_COUNT   - Retrieve the counts of the soft and hard reset
 273  *                         operations performed on the device since the last
 274  *                         time the driver was loaded.
 275  * HL_INFO_TIME_SYNC     - Retrieve the device's time alongside the host's time
 276  *                         for synchronization.
 277  * HL_INFO_CS_COUNTERS   - Retrieve command submission counters
 278  * HL_INFO_PCI_COUNTERS  - Retrieve PCI counters
 279  * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason
 280  * HL_INFO_SYNC_MANAGER  - Retrieve sync manager info per dcore
 281  * HL_INFO_TOTAL_ENERGY  - Retrieve total energy consumption
 282  * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency
 283  */
 284 #define HL_INFO_HW_IP_INFO              0
 285 #define HL_INFO_HW_EVENTS               1
 286 #define HL_INFO_DRAM_USAGE              2
 287 #define HL_INFO_HW_IDLE                 3
 288 #define HL_INFO_DEVICE_STATUS           4
 289 #define HL_INFO_DEVICE_UTILIZATION      6
 290 #define HL_INFO_HW_EVENTS_AGGREGATE     7
 291 #define HL_INFO_CLK_RATE                8
 292 #define HL_INFO_RESET_COUNT             9
 293 #define HL_INFO_TIME_SYNC               10
 294 #define HL_INFO_CS_COUNTERS             11
 295 #define HL_INFO_PCI_COUNTERS            12
 296 #define HL_INFO_CLK_THROTTLE_REASON     13
 297 #define HL_INFO_SYNC_MANAGER            14
 298 #define HL_INFO_TOTAL_ENERGY            15
 299 #define HL_INFO_PLL_FREQUENCY           16
 300
 301 #define HL_INFO_VERSION_MAX_LEN 128
 302 #define HL_INFO_CARD_NAME_MAX_LEN       16
 303
 304 struct hl_info_hw_ip_info {
 305         __u64 sram_base_address;
 306         __u64 dram_base_address;
 307         __u64 dram_size;
 308         __u32 sram_size;
 309         __u32 num_of_events;
 310         __u32 device_id; /* PCI Device ID */
 311         __u32 module_id; /* For mezzanine cards in servers (From OCP spec.) */
 312         __u32 reserved[2];
 313         __u32 cpld_version;
 314         __u32 psoc_pci_pll_nr;
 315         __u32 psoc_pci_pll_nf;
 316         __u32 psoc_pci_pll_od;
 317         __u32 psoc_pci_pll_div_factor;
 318         __u8 tpc_enabled_mask;
 319         __u8 dram_enabled;
 320         __u8 pad[2];
 321         __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN];
 322         __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN];
 323 };
 324
 325 struct hl_info_dram_usage {
 326         __u64 dram_free_mem;
 327         __u64 ctx_dram_mem;
 328 };
 329
 330 struct hl_info_hw_idle {
 331         __u32 is_idle;
 332         /*
 333          * Bitmask of busy engines.
 334          * Bits definition is according to `enum <chip>_enging_id'.
 335          */
 336         __u32 busy_engines_mask;
 337
 338         /*
 339          * Extended Bitmask of busy engines.
 340          * Bits definition is according to `enum <chip>_enging_id'.
 341          */
 342         __u64 busy_engines_mask_ext;
 343 };
 344
 345 struct hl_info_device_status {
 346         __u32 status;
 347         __u32 pad;
 348 };
 349
 350 struct hl_info_device_utilization {
 351         __u32 utilization;
 352         __u32 pad;
 353 };
 354
 355 struct hl_info_clk_rate {
 356         __u32 cur_clk_rate_mhz;
 357         __u32 max_clk_rate_mhz;
 358 };
 359
 360 struct hl_info_reset_count {
 361         __u32 hard_reset_cnt;
 362         __u32 soft_reset_cnt;
 363 };
 364
 365 struct hl_info_time_sync {
 366         __u64 device_time;
 367         __u64 host_time;
 368 };
 369
 370 /**
 371  * struct hl_info_pci_counters - pci counters
 372  * @rx_throughput: PCI rx throughput KBps
 373  * @tx_throughput: PCI tx throughput KBps
 374  * @replay_cnt: PCI replay counter
 375  */
 376 struct hl_info_pci_counters {
 377         __u64 rx_throughput;
 378         __u64 tx_throughput;
 379         __u64 replay_cnt;
 380 };
 381
 382 #define HL_CLK_THROTTLE_POWER   0x1
 383 #define HL_CLK_THROTTLE_THERMAL 0x2
 384
 385 /**
 386  * struct hl_info_clk_throttle - clock throttling reason
 387  * @clk_throttling_reason: each bit represents a clk throttling reason
 388  */
 389 struct hl_info_clk_throttle {
 390         __u32 clk_throttling_reason;
 391 };
 392
 393 /**
 394  * struct hl_info_energy - device energy information
 395  * @total_energy_consumption: total device energy consumption
 396  */
 397 struct hl_info_energy {
 398         __u64 total_energy_consumption;
 399 };
 400
 401 #define HL_PLL_NUM_OUTPUTS 4
 402
 403 struct hl_pll_frequency_info {
 404         __u16 output[HL_PLL_NUM_OUTPUTS];
 405 };
 406
 407 /**
 408  * struct hl_info_sync_manager - sync manager information
 409  * @first_available_sync_object: first available sob
 410  * @first_available_monitor: first available monitor
 411  */
 412 struct hl_info_sync_manager {
 413         __u32 first_available_sync_object;
 414         __u32 first_available_monitor;
 415 };
 416
 417 /**
 418  * struct hl_info_cs_counters - command submission counters
 419  * @total_out_of_mem_drop_cnt: total dropped due to memory allocation issue
 420  * @ctx_out_of_mem_drop_cnt: context dropped due to memory allocation issue
 421  * @total_parsing_drop_cnt: total dropped due to error in packet parsing
 422  * @ctx_parsing_drop_cnt: context dropped due to error in packet parsing
 423  * @total_queue_full_drop_cnt: total dropped due to queue full
 424  * @ctx_queue_full_drop_cnt: context dropped due to queue full
 425  * @total_device_in_reset_drop_cnt: total dropped due to device in reset
 426  * @ctx_device_in_reset_drop_cnt: context dropped due to device in reset
 427  * @total_max_cs_in_flight_drop_cnt: total dropped due to maximum CS in-flight
 428  * @ctx_max_cs_in_flight_drop_cnt: context dropped due to maximum CS in-flight
 429  * @total_validation_drop_cnt: total dropped due to validation error
 430  * @ctx_validation_drop_cnt: context dropped due to validation error
 431  */
 432 struct hl_info_cs_counters {
 433         __u64 total_out_of_mem_drop_cnt;
 434         __u64 ctx_out_of_mem_drop_cnt;
 435         __u64 total_parsing_drop_cnt;
 436         __u64 ctx_parsing_drop_cnt;
 437         __u64 total_queue_full_drop_cnt;
 438         __u64 ctx_queue_full_drop_cnt;
 439         __u64 total_device_in_reset_drop_cnt;
 440         __u64 ctx_device_in_reset_drop_cnt;
 441         __u64 total_max_cs_in_flight_drop_cnt;
 442         __u64 ctx_max_cs_in_flight_drop_cnt;
 443         __u64 total_validation_drop_cnt;
 444         __u64 ctx_validation_drop_cnt;
 445 };
 446
 447 enum gaudi_dcores {
 448         HL_GAUDI_WS_DCORE,
 449         HL_GAUDI_WN_DCORE,
 450         HL_GAUDI_EN_DCORE,
 451         HL_GAUDI_ES_DCORE
 452 };
 453
 454 struct hl_info_args {
 455         /* Location of relevant struct in userspace */
 456         __u64 return_pointer;
 457         /*
 458          * The size of the return value. Just like "size" in "snprintf",
 459          * it limits how many bytes the kernel can write
 460          *
 461          * For hw_events array, the size should be
 462          * hl_info_hw_ip_info.num_of_events * sizeof(__u32)
 463          */
 464         __u32 return_size;
 465
 466         /* HL_INFO_* */
 467         __u32 op;
 468
 469         union {
 470                 /* Dcore id for which the information is relevant.
 471                  * For Gaudi refer to 'enum gaudi_dcores'
 472                  */
 473                 __u32 dcore_id;
 474                 /* Context ID - Currently not in use */
 475                 __u32 ctx_id;
 476                 /* Period value for utilization rate (100ms - 1000ms, in 100ms
 477                  * resolution.
 478                  */
 479                 __u32 period_ms;
 480                 /* PLL frequency retrieval */
 481                 __u32 pll_index;
 482         };
 483
 484         __u32 pad;
 485 };
 486
 487 /* Opcode to create a new command buffer */
 488 #define HL_CB_OP_CREATE         0
 489 /* Opcode to destroy previously created command buffer */
 490 #define HL_CB_OP_DESTROY        1
 491 /* Opcode to retrieve information about a command buffer */
 492 #define HL_CB_OP_INFO           2
 493
 494 /* 2MB minus 32 bytes for 2xMSG_PROT */
 495 #define HL_MAX_CB_SIZE          (0x200000 - 32)
 496
 497 /* Indicates whether the command buffer should be mapped to the device's MMU */
 498 #define HL_CB_FLAGS_MAP         0x1
 499
 500 struct hl_cb_in {
 501         /* Handle of CB or 0 if we want to create one */
 502         __u64 cb_handle;
 503         /* HL_CB_OP_* */
 504         __u32 op;
 505         /* Size of CB. Maximum size is HL_MAX_CB_SIZE. The minimum size that
 506          * will be allocated, regardless of this parameter's value, is PAGE_SIZE
 507          */
 508         __u32 cb_size;
 509         /* Context ID - Currently not in use */
 510         __u32 ctx_id;
 511         /* HL_CB_FLAGS_* */
 512         __u32 flags;
 513 };
 514
 515 struct hl_cb_out {
 516         union {
 517                 /* Handle of CB */
 518                 __u64 cb_handle;
 519
 520                 /* Information about CB */
 521                 struct {
 522                         /* Usage count of CB */
 523                         __u32 usage_cnt;
 524                         __u32 pad;
 525                 };
 526         };
 527 };
 528
 529 union hl_cb_args {
 530         struct hl_cb_in in;
 531         struct hl_cb_out out;
 532 };
 533
 534 /* HL_CS_CHUNK_FLAGS_ values
 535  *
 536  * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB:
 537  *      Indicates if the CB was allocated and mapped by userspace.
 538  *      User allocated CB is a command buffer allocated by the user, via malloc
 539  *      (or similar). After allocating the CB, the user invokes “memory ioctl”
 540  *      to map the user memory into a device virtual address. The user provides
 541  *      this address via the cb_handle field. The interface provides the
 542  *      ability to create a large CBs, Which aren’t limited to
 543  *      “HL_MAX_CB_SIZE”. Therefore, it increases the PCI-DMA queues
 544  *      throughput. This CB allocation method also reduces the use of Linux
 545  *      DMA-able memory pool. Which are limited and used by other Linux
 546  *      sub-systems.
 547  */
 548 #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1
 549
 550 /*
 551  * This structure size must always be fixed to 64-bytes for backward
 552  * compatibility
 553  */
 554 struct hl_cs_chunk {
 555         union {
 556                 /* For external queue, this represents a Handle of CB on the
 557                  * Host.
 558                  * For internal queue in Goya, this represents an SRAM or
 559                  * a DRAM address of the internal CB. In Gaudi, this might also
 560                  * represent a mapped host address of the CB.
 561                  *
 562                  * A mapped host address is in the device address space, after
 563                  * a host address was mapped by the device MMU.
 564                  */
 565                 __u64 cb_handle;
 566
 567                 /* Relevant only when HL_CS_FLAGS_WAIT or
 568                  * HL_CS_FLAGS_COLLECTIVE_WAIT is set.
 569                  * This holds address of array of u64 values that contain
 570                  * signal CS sequence numbers. The wait described by this job
 571                  * will listen on all those signals (wait event per signal)
 572                  */
 573                 __u64 signal_seq_arr;
 574         };
 575
 576         /* Index of queue to put the CB on */
 577         __u32 queue_index;
 578
 579         union {
 580                 /*
 581                  * Size of command buffer with valid packets
 582                  * Can be smaller then actual CB size
 583                  */
 584                 __u32 cb_size;
 585
 586                 /* Relevant only when HL_CS_FLAGS_WAIT or
 587                  * HL_CS_FLAGS_COLLECTIVE_WAIT is set.
 588                  * Number of entries in signal_seq_arr
 589                  */
 590                 __u32 num_signal_seq_arr;
 591         };
 592
 593         /* HL_CS_CHUNK_FLAGS_* */
 594         __u32 cs_chunk_flags;
 595
 596         /* Relevant only when HL_CS_FLAGS_COLLECTIVE_WAIT is set.
 597          * This holds the collective engine ID. The wait described by this job
 598          * will sync with this engine and with all NICs before completion.
 599          */
 600         __u32 collective_engine_id;
 601
 602         /* Align structure to 64 bytes */
 603         __u32 pad[10];
 604 };
 605
 606 /* SIGNAL and WAIT/COLLECTIVE_WAIT flags are mutually exclusive */
 607 #define HL_CS_FLAGS_FORCE_RESTORE       0x1
 608 #define HL_CS_FLAGS_SIGNAL              0x2
 609 #define HL_CS_FLAGS_WAIT                0x4
 610 #define HL_CS_FLAGS_COLLECTIVE_WAIT     0x8
 611 #define HL_CS_FLAGS_TIMESTAMP           0x20
 612
 613 #define HL_CS_STATUS_SUCCESS            0
 614
 615 #define HL_MAX_JOBS_PER_CS              512
 616
 617 struct hl_cs_in {
 618
 619         /* this holds address of array of hl_cs_chunk for restore phase */
 620         __u64 chunks_restore;
 621
 622         /* holds address of array of hl_cs_chunk for execution phase */
 623         __u64 chunks_execute;
 624
 625         /* this holds address of array of hl_cs_chunk for store phase -
 626          * Currently not in use
 627          */
 628         __u64 chunks_store;
 629
 630         /* Number of chunks in restore phase array. Maximum number is
 631          * HL_MAX_JOBS_PER_CS
 632          */
 633         __u32 num_chunks_restore;
 634
 635         /* Number of chunks in execution array. Maximum number is
 636          * HL_MAX_JOBS_PER_CS
 637          */
 638         __u32 num_chunks_execute;
 639
 640         /* Number of chunks in restore phase array - Currently not in use */
 641         __u32 num_chunks_store;
 642
 643         /* HL_CS_FLAGS_* */
 644         __u32 cs_flags;
 645
 646         /* Context ID - Currently not in use */
 647         __u32 ctx_id;
 648 };
 649
 650 struct hl_cs_out {
 651         /*
 652          * seq holds the sequence number of the CS to pass to wait ioctl. All
 653          * values are valid except for 0 and ULLONG_MAX
 654          */
 655         __u64 seq;
 656         /* HL_CS_STATUS_* */
 657         __u32 status;
 658         __u32 pad;
 659 };
 660
 661 union hl_cs_args {
 662         struct hl_cs_in in;
 663         struct hl_cs_out out;
 664 };
 665
 666 struct hl_wait_cs_in {
 667         /* Command submission sequence number */
 668         __u64 seq;
 669         /* Absolute timeout to wait in microseconds */
 670         __u64 timeout_us;
 671         /* Context ID - Currently not in use */
 672         __u32 ctx_id;
 673         __u32 pad;
 674 };
 675
 676 #define HL_WAIT_CS_STATUS_COMPLETED     0
 677 #define HL_WAIT_CS_STATUS_BUSY          1
 678 #define HL_WAIT_CS_STATUS_TIMEDOUT      2
 679 #define HL_WAIT_CS_STATUS_ABORTED       3
 680 #define HL_WAIT_CS_STATUS_INTERRUPTED   4
 681
 682 #define HL_WAIT_CS_STATUS_FLAG_GONE             0x1
 683 #define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD    0x2
 684
 685 struct hl_wait_cs_out {
 686         /* HL_WAIT_CS_STATUS_* */
 687         __u32 status;
 688         /* HL_WAIT_CS_STATUS_FLAG* */
 689         __u32 flags;
 690         /* valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set */
 691         __s64 timestamp_nsec;
 692 };
 693
 694 union hl_wait_cs_args {
 695         struct hl_wait_cs_in in;
 696         struct hl_wait_cs_out out;
 697 };
 698
 699 /* Opcode to allocate device memory */
 700 #define HL_MEM_OP_ALLOC                 0
 701 /* Opcode to free previously allocated device memory */
 702 #define HL_MEM_OP_FREE                  1
 703 /* Opcode to map host and device memory */
 704 #define HL_MEM_OP_MAP                   2
 705 /* Opcode to unmap previously mapped host and device memory */
 706 #define HL_MEM_OP_UNMAP                 3
 707
 708 /* Memory flags */
 709 #define HL_MEM_CONTIGUOUS       0x1
 710 #define HL_MEM_SHARED           0x2
 711 #define HL_MEM_USERPTR          0x4
 712
 713 struct hl_mem_in {
 714         union {
 715                 /* HL_MEM_OP_ALLOC- allocate device memory */
 716                 struct {
 717                         /* Size to alloc */
 718                         __u64 mem_size;
 719                 } alloc;
 720
 721                 /* HL_MEM_OP_FREE - free device memory */
 722                 struct {
 723                         /* Handle returned from HL_MEM_OP_ALLOC */
 724                         __u64 handle;
 725                 } free;
 726
 727                 /* HL_MEM_OP_MAP - map device memory */
 728                 struct {
 729                         /*
 730                          * Requested virtual address of mapped memory.
 731                          * The driver will try to map the requested region to
 732                          * this hint address, as long as the address is valid
 733                          * and not already mapped. The user should check the
 734                          * returned address of the IOCTL to make sure he got
 735                          * the hint address. Passing 0 here means that the
 736                          * driver will choose the address itself.
 737                          */
 738                         __u64 hint_addr;
 739                         /* Handle returned from HL_MEM_OP_ALLOC */
 740                         __u64 handle;
 741                 } map_device;
 742
 743                 /* HL_MEM_OP_MAP - map host memory */
 744                 struct {
 745                         /* Address of allocated host memory */
 746                         __u64 host_virt_addr;
 747                         /*
 748                          * Requested virtual address of mapped memory.
 749                          * The driver will try to map the requested region to
 750                          * this hint address, as long as the address is valid
 751                          * and not already mapped. The user should check the
 752                          * returned address of the IOCTL to make sure he got
 753                          * the hint address. Passing 0 here means that the
 754                          * driver will choose the address itself.
 755                          */
 756                         __u64 hint_addr;
 757                         /* Size of allocated host memory */
 758                         __u64 mem_size;
 759                 } map_host;
 760
 761                 /* HL_MEM_OP_UNMAP - unmap host memory */
 762                 struct {
 763                         /* Virtual address returned from HL_MEM_OP_MAP */
 764                         __u64 device_virt_addr;
 765                 } unmap;
 766         };
 767
 768         /* HL_MEM_OP_* */
 769         __u32 op;
 770         /* HL_MEM_* flags */
 771         __u32 flags;
 772         /* Context ID - Currently not in use */
 773         __u32 ctx_id;
 774         __u32 pad;
 775 };
 776
 777 struct hl_mem_out {
 778         union {
 779                 /*
 780                  * Used for HL_MEM_OP_MAP as the virtual address that was
 781                  * assigned in the device VA space.
 782                  * A value of 0 means the requested operation failed.
 783                  */
 784                 __u64 device_virt_addr;
 785
 786                 /*
 787                  * Used for HL_MEM_OP_ALLOC. This is the assigned
 788                  * handle for the allocated memory
 789                  */
 790                 __u64 handle;
 791         };
 792 };
 793
 794 union hl_mem_args {
 795         struct hl_mem_in in;
 796         struct hl_mem_out out;
 797 };
 798
 799 #define HL_DEBUG_MAX_AUX_VALUES         10
 800
 801 struct hl_debug_params_etr {
 802         /* Address in memory to allocate buffer */
 803         __u64 buffer_address;
 804
 805         /* Size of buffer to allocate */
 806         __u64 buffer_size;
 807
 808         /* Sink operation mode: SW fifo, HW fifo, Circular buffer */
 809         __u32 sink_mode;
 810         __u32 pad;
 811 };
 812
 813 struct hl_debug_params_etf {
 814         /* Address in memory to allocate buffer */
 815         __u64 buffer_address;
 816
 817         /* Size of buffer to allocate */
 818         __u64 buffer_size;
 819
 820         /* Sink operation mode: SW fifo, HW fifo, Circular buffer */
 821         __u32 sink_mode;
 822         __u32 pad;
 823 };
 824
 825 struct hl_debug_params_stm {
 826         /* Two bit masks for HW event and Stimulus Port */
 827         __u64 he_mask;
 828         __u64 sp_mask;
 829
 830         /* Trace source ID */
 831         __u32 id;
 832
 833         /* Frequency for the timestamp register */
 834         __u32 frequency;
 835 };
 836
 837 struct hl_debug_params_bmon {
 838         /* Two address ranges that the user can request to filter */
 839         __u64 start_addr0;
 840         __u64 addr_mask0;
 841
 842         __u64 start_addr1;
 843         __u64 addr_mask1;
 844
 845         /* Capture window configuration */
 846         __u32 bw_win;
 847         __u32 win_capture;
 848
 849         /* Trace source ID */
 850         __u32 id;
 851         __u32 pad;
 852 };
 853
 854 struct hl_debug_params_spmu {
 855         /* Event types selection */
 856         __u64 event_types[HL_DEBUG_MAX_AUX_VALUES];
 857
 858         /* Number of event types selection */
 859         __u32 event_types_num;
 860         __u32 pad;
 861 };
 862
 863 /* Opcode for ETR component */
 864 #define HL_DEBUG_OP_ETR         0
 865 /* Opcode for ETF component */
 866 #define HL_DEBUG_OP_ETF         1
 867 /* Opcode for STM component */
 868 #define HL_DEBUG_OP_STM         2
 869 /* Opcode for FUNNEL component */
 870 #define HL_DEBUG_OP_FUNNEL      3
 871 /* Opcode for BMON component */
 872 #define HL_DEBUG_OP_BMON        4
 873 /* Opcode for SPMU component */
 874 #define HL_DEBUG_OP_SPMU        5
 875 /* Opcode for timestamp (deprecated) */
 876 #define HL_DEBUG_OP_TIMESTAMP   6
 877 /* Opcode for setting the device into or out of debug mode. The enable
 878  * variable should be 1 for enabling debug mode and 0 for disabling it
 879  */
 880 #define HL_DEBUG_OP_SET_MODE    7
 881
 882 struct hl_debug_args {
 883         /*
 884          * Pointer to user input structure.
 885          * This field is relevant to specific opcodes.
 886          */
 887         __u64 input_ptr;
 888         /* Pointer to user output structure */
 889         __u64 output_ptr;
 890         /* Size of user input structure */
 891         __u32 input_size;
 892         /* Size of user output structure */
 893         __u32 output_size;
 894         /* HL_DEBUG_OP_* */
 895         __u32 op;
 896         /*
 897          * Register index in the component, taken from the debug_regs_index enum
 898          * in the various ASIC header files
 899          */
 900         __u32 reg_idx;
 901         /* Enable/disable */
 902         __u32 enable;
 903         /* Context ID - Currently not in use */
 904         __u32 ctx_id;
 905 };
 906
 907 /*
 908  * Various information operations such as:
 909  * - H/W IP information
 910  * - Current dram usage
 911  *
 912  * The user calls this IOCTL with an opcode that describes the required
 913  * information. The user should supply a pointer to a user-allocated memory
 914  * chunk, which will be filled by the driver with the requested information.
 915  *
 916  * The user supplies the maximum amount of size to copy into the user's memory,
 917  * in order to prevent data corruption in case of differences between the
 918  * definitions of structures in kernel and userspace, e.g. in case of old
 919  * userspace and new kernel driver
 920  */
 921 #define HL_IOCTL_INFO   \
 922                 _IOWR('H', 0x01, struct hl_info_args)
 923
 924 /*
 925  * Command Buffer
 926  * - Request a Command Buffer
 927  * - Destroy a Command Buffer
 928  *
 929  * The command buffers are memory blocks that reside in DMA-able address
 930  * space and are physically contiguous so they can be accessed by the device
 931  * directly. They are allocated using the coherent DMA API.
 932  *
 933  * When creating a new CB, the IOCTL returns a handle of it, and the user-space
 934  * process needs to use that handle to mmap the buffer so it can access them.
 935  *
 936  * In some instances, the device must access the command buffer through the
 937  * device's MMU, and thus its memory should be mapped. In these cases, user can
 938  * indicate the driver that such a mapping is required.
 939  * The resulting device virtual address will be used internally by the driver,
 940  * and won't be returned to user.
 941  *
 942  */
 943 #define HL_IOCTL_CB             \
 944                 _IOWR('H', 0x02, union hl_cb_args)
 945
 946 /*
 947  * Command Submission
 948  *
 949  * To submit work to the device, the user need to call this IOCTL with a set
 950  * of JOBS. That set of JOBS constitutes a CS object.
 951  * Each JOB will be enqueued on a specific queue, according to the user's input.
 952  * There can be more then one JOB per queue.
 953  *
 954  * The CS IOCTL will receive three sets of JOBS. One set is for "restore" phase,
 955  * a second set is for "execution" phase and a third set is for "store" phase.
 956  * The JOBS on the "restore" phase are enqueued only after context-switch
 957  * (or if its the first CS for this context). The user can also order the
 958  * driver to run the "restore" phase explicitly
 959  *
 960  * There are two types of queues - external and internal. External queues
 961  * are DMA queues which transfer data from/to the Host. All other queues are
 962  * internal. The driver will get completion notifications from the device only
 963  * on JOBS which are enqueued in the external queues.
 964  *
 965  * For jobs on external queues, the user needs to create command buffers
 966  * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on
 967  * internal queues, the user needs to prepare a "command buffer" with packets
 968  * on either the device SRAM/DRAM or the host, and give the device address of
 969  * that buffer to the CS ioctl.
 970  *
 971  * This IOCTL is asynchronous in regard to the actual execution of the CS. This
 972  * means it returns immediately after ALL the JOBS were enqueued on their
 973  * relevant queues. Therefore, the user mustn't assume the CS has been completed
 974  * or has even started to execute.
 975  *
 976  * Upon successful enqueue, the IOCTL returns a sequence number which the user
 977  * can use with the "Wait for CS" IOCTL to check whether the handle's CS
 978  * external JOBS have been completed. Note that if the CS has internal JOBS
 979  * which can execute AFTER the external JOBS have finished, the driver might
 980  * report that the CS has finished executing BEFORE the internal JOBS have
 981  * actually finished executing.
 982  *
 983  * Even though the sequence number increments per CS, the user can NOT
 984  * automatically assume that if CS with sequence number N finished, then CS
 985  * with sequence number N-1 also finished. The user can make this assumption if
 986  * and only if CS N and CS N-1 are exactly the same (same CBs for the same
 987  * queues).
 988  */
 989 #define HL_IOCTL_CS                     \
 990                 _IOWR('H', 0x03, union hl_cs_args)
 991
 992 /*
 993  * Wait for Command Submission
 994  *
 995  * The user can call this IOCTL with a handle it received from the CS IOCTL
 996  * to wait until the handle's CS has finished executing. The user will wait
 997  * inside the kernel until the CS has finished or until the user-requested
 998  * timeout has expired.
 999  *
1000  * If the timeout value is 0, the driver won't sleep at all. It will check
1001  * the status of the CS and return immediately
1002  *
1003  * The return value of the IOCTL is a standard Linux error code. The possible
1004  * values are:
1005  *
1006  * EINTR     - Kernel waiting has been interrupted, e.g. due to OS signal
1007  *             that the user process received
1008  * ETIMEDOUT - The CS has caused a timeout on the device
1009  * EIO       - The CS was aborted (usually because the device was reset)
1010  * ENODEV    - The device wants to do hard-reset (so user need to close FD)
1011  *
1012  * The driver also returns a custom define inside the IOCTL which can be:
1013  *
1014  * HL_WAIT_CS_STATUS_COMPLETED   - The CS has been completed successfully (0)
1015  * HL_WAIT_CS_STATUS_BUSY        - The CS is still executing (0)
1016  * HL_WAIT_CS_STATUS_TIMEDOUT    - The CS has caused a timeout on the device
1017  *                                 (ETIMEDOUT)
1018  * HL_WAIT_CS_STATUS_ABORTED     - The CS was aborted, usually because the
1019  *                                 device was reset (EIO)
1020  * HL_WAIT_CS_STATUS_INTERRUPTED - Waiting for the CS was interrupted (EINTR)
1021  *
1022  */
1023
1024 #define HL_IOCTL_WAIT_CS                        \
1025                 _IOWR('H', 0x04, union hl_wait_cs_args)
1026
1027 /*
1028  * Memory
1029  * - Map host memory to device MMU
1030  * - Unmap host memory from device MMU
1031  *
1032  * This IOCTL allows the user to map host memory to the device MMU
1033  *
1034  * For host memory, the IOCTL doesn't allocate memory. The user is supposed
1035  * to allocate the memory in user-space (malloc/new). The driver pins the
1036  * physical pages (up to the allowed limit by the OS), assigns a virtual
1037  * address in the device VA space and initializes the device MMU.
1038  *
1039  * There is an option for the user to specify the requested virtual address.
1040  *
1041  */
1042 #define HL_IOCTL_MEMORY         \
1043                 _IOWR('H', 0x05, union hl_mem_args)
1044
1045 /*
1046  * Debug
1047  * - Enable/disable the ETR/ETF/FUNNEL/STM/BMON/SPMU debug traces
1048  *
1049  * This IOCTL allows the user to get debug traces from the chip.
1050  *
1051  * Before the user can send configuration requests of the various
1052  * debug/profile engines, it needs to set the device into debug mode.
1053  * This is because the debug/profile infrastructure is shared component in the
1054  * device and we can't allow multiple users to access it at the same time.
1055  *
1056  * Once a user set the device into debug mode, the driver won't allow other
1057  * users to "work" with the device, i.e. open a FD. If there are multiple users
1058  * opened on the device, the driver won't allow any user to debug the device.
1059  *
1060  * For each configuration request, the user needs to provide the register index
1061  * and essential data such as buffer address and size.
1062  *
1063  * Once the user has finished using the debug/profile engines, he should
1064  * set the device into non-debug mode, i.e. disable debug mode.
1065  *
1066  * The driver can decide to "kick out" the user if he abuses this interface.
1067  *
1068  */
1069 #define HL_IOCTL_DEBUG          \
1070                 _IOWR('H', 0x06, struct hl_debug_args)
1071
1072 #define HL_COMMAND_START        0x01
1073 #define HL_COMMAND_END          0x07
1074
1075 #endif /* HABANALABS_H_ */