1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the fpga framework and fpga manager drivers.
6 # Core FPGA Manager Framework
7 obj-
$(CONFIG_FPGA
) += fpga-mgr.o
10 obj-
$(CONFIG_FPGA_MGR_ALTERA_CVP
) += altera-cvp.o
11 obj-
$(CONFIG_FPGA_MGR_ALTERA_PS_SPI
) += altera-ps-spi.o
12 obj-
$(CONFIG_FPGA_MGR_ICE40_SPI
) += ice40-spi.o
13 obj-
$(CONFIG_FPGA_MGR_MACHXO2_SPI
) += machxo2-spi.o
14 obj-
$(CONFIG_FPGA_MGR_SOCFPGA
) += socfpga.o
15 obj-
$(CONFIG_FPGA_MGR_SOCFPGA_A10
) += socfpga-a10.o
16 obj-
$(CONFIG_FPGA_MGR_TS73XX
) += ts73xx-fpga.o
17 obj-
$(CONFIG_FPGA_MGR_XILINX_SPI
) += xilinx-spi.o
18 obj-
$(CONFIG_FPGA_MGR_ZYNQ_FPGA
) += zynq-fpga.o
19 obj-
$(CONFIG_ALTERA_PR_IP_CORE
) += altera-pr-ip-core.o
20 obj-
$(CONFIG_ALTERA_PR_IP_CORE_PLAT
) += altera-pr-ip-core-plat.o
23 obj-
$(CONFIG_FPGA_BRIDGE
) += fpga-bridge.o
24 obj-
$(CONFIG_SOCFPGA_FPGA_BRIDGE
) += altera-hps2fpga.o altera-fpga2sdram.o
25 obj-
$(CONFIG_ALTERA_FREEZE_BRIDGE
) += altera-freeze-bridge.o
26 obj-
$(CONFIG_XILINX_PR_DECOUPLER
) += xilinx-pr-decoupler.o
28 # High Level Interfaces
29 obj-
$(CONFIG_FPGA_REGION
) += fpga-region.o
30 obj-
$(CONFIG_OF_FPGA_REGION
) += of-fpga-region.o
32 # FPGA Device Feature List Support
33 obj-
$(CONFIG_FPGA_DFL
) += dfl.o
34 obj-
$(CONFIG_FPGA_DFL_FME
) += dfl-fme.o
35 obj-
$(CONFIG_FPGA_DFL_FME_MGR
) += dfl-fme-mgr.o
36 obj-
$(CONFIG_FPGA_DFL_FME_BRIDGE
) += dfl-fme-br.o
37 obj-
$(CONFIG_FPGA_DFL_FME_REGION
) += dfl-fme-region.o
38 obj-
$(CONFIG_FPGA_DFL_AFU
) += dfl-afu.o
40 dfl-fme-objs
:= dfl-fme-main.o dfl-fme-pr.o
41 dfl-afu-objs
:= dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
43 # Drivers for FPGAs which implement DFL
44 obj-
$(CONFIG_FPGA_DFL_PCI
) += dfl-pci.o