2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Flora Fu, MediaTek
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/regmap.h>
20 #include <linux/mfd/core.h>
21 #include <linux/mfd/mt6397/core.h>
22 #include <linux/mfd/mt6323/core.h>
23 #include <linux/mfd/mt6397/registers.h>
24 #include <linux/mfd/mt6323/registers.h>
26 #define MT6397_RTC_BASE 0xe000
27 #define MT6397_RTC_SIZE 0x3e
29 #define MT6323_CID_CODE 0x23
30 #define MT6391_CID_CODE 0x91
31 #define MT6397_CID_CODE 0x97
33 static const struct resource mt6397_rtc_resources
[] = {
35 .start
= MT6397_RTC_BASE
,
36 .end
= MT6397_RTC_BASE
+ MT6397_RTC_SIZE
,
37 .flags
= IORESOURCE_MEM
,
40 .start
= MT6397_IRQ_RTC
,
41 .end
= MT6397_IRQ_RTC
,
42 .flags
= IORESOURCE_IRQ
,
46 static const struct resource mt6323_keys_resources
[] = {
47 DEFINE_RES_IRQ(MT6323_IRQ_STATUS_PWRKEY
),
48 DEFINE_RES_IRQ(MT6323_IRQ_STATUS_FCHRKEY
),
51 static const struct resource mt6397_keys_resources
[] = {
52 DEFINE_RES_IRQ(MT6397_IRQ_PWRKEY
),
53 DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY
),
56 static const struct mfd_cell mt6323_devs
[] = {
58 .name
= "mt6323-regulator",
59 .of_compatible
= "mediatek,mt6323-regulator"
62 .of_compatible
= "mediatek,mt6323-led"
64 .name
= "mtk-pmic-keys",
65 .num_resources
= ARRAY_SIZE(mt6323_keys_resources
),
66 .resources
= mt6323_keys_resources
,
67 .of_compatible
= "mediatek,mt6323-keys"
71 static const struct mfd_cell mt6397_devs
[] = {
74 .num_resources
= ARRAY_SIZE(mt6397_rtc_resources
),
75 .resources
= mt6397_rtc_resources
,
76 .of_compatible
= "mediatek,mt6397-rtc",
78 .name
= "mt6397-regulator",
79 .of_compatible
= "mediatek,mt6397-regulator",
81 .name
= "mt6397-codec",
82 .of_compatible
= "mediatek,mt6397-codec",
85 .of_compatible
= "mediatek,mt6397-clk",
87 .name
= "mt6397-pinctrl",
88 .of_compatible
= "mediatek,mt6397-pinctrl",
90 .name
= "mtk-pmic-keys",
91 .num_resources
= ARRAY_SIZE(mt6397_keys_resources
),
92 .resources
= mt6397_keys_resources
,
93 .of_compatible
= "mediatek,mt6397-keys"
97 static void mt6397_irq_lock(struct irq_data
*data
)
99 struct mt6397_chip
*mt6397
= irq_data_get_irq_chip_data(data
);
101 mutex_lock(&mt6397
->irqlock
);
104 static void mt6397_irq_sync_unlock(struct irq_data
*data
)
106 struct mt6397_chip
*mt6397
= irq_data_get_irq_chip_data(data
);
108 regmap_write(mt6397
->regmap
, mt6397
->int_con
[0],
109 mt6397
->irq_masks_cur
[0]);
110 regmap_write(mt6397
->regmap
, mt6397
->int_con
[1],
111 mt6397
->irq_masks_cur
[1]);
113 mutex_unlock(&mt6397
->irqlock
);
116 static void mt6397_irq_disable(struct irq_data
*data
)
118 struct mt6397_chip
*mt6397
= irq_data_get_irq_chip_data(data
);
119 int shift
= data
->hwirq
& 0xf;
120 int reg
= data
->hwirq
>> 4;
122 mt6397
->irq_masks_cur
[reg
] &= ~BIT(shift
);
125 static void mt6397_irq_enable(struct irq_data
*data
)
127 struct mt6397_chip
*mt6397
= irq_data_get_irq_chip_data(data
);
128 int shift
= data
->hwirq
& 0xf;
129 int reg
= data
->hwirq
>> 4;
131 mt6397
->irq_masks_cur
[reg
] |= BIT(shift
);
134 #ifdef CONFIG_PM_SLEEP
135 static int mt6397_irq_set_wake(struct irq_data
*irq_data
, unsigned int on
)
137 struct mt6397_chip
*mt6397
= irq_data_get_irq_chip_data(irq_data
);
138 int shift
= irq_data
->hwirq
& 0xf;
139 int reg
= irq_data
->hwirq
>> 4;
142 mt6397
->wake_mask
[reg
] |= BIT(shift
);
144 mt6397
->wake_mask
[reg
] &= ~BIT(shift
);
149 #define mt6397_irq_set_wake NULL
152 static struct irq_chip mt6397_irq_chip
= {
153 .name
= "mt6397-irq",
154 .irq_bus_lock
= mt6397_irq_lock
,
155 .irq_bus_sync_unlock
= mt6397_irq_sync_unlock
,
156 .irq_enable
= mt6397_irq_enable
,
157 .irq_disable
= mt6397_irq_disable
,
158 .irq_set_wake
= mt6397_irq_set_wake
,
161 static void mt6397_irq_handle_reg(struct mt6397_chip
*mt6397
, int reg
,
167 ret
= regmap_read(mt6397
->regmap
, reg
, &status
);
169 dev_err(mt6397
->dev
, "Failed to read irq status: %d\n", ret
);
173 for (i
= 0; i
< 16; i
++) {
174 if (status
& BIT(i
)) {
175 irq
= irq_find_mapping(mt6397
->irq_domain
, irqbase
+ i
);
177 handle_nested_irq(irq
);
181 regmap_write(mt6397
->regmap
, reg
, status
);
184 static irqreturn_t
mt6397_irq_thread(int irq
, void *data
)
186 struct mt6397_chip
*mt6397
= data
;
188 mt6397_irq_handle_reg(mt6397
, mt6397
->int_status
[0], 0);
189 mt6397_irq_handle_reg(mt6397
, mt6397
->int_status
[1], 16);
194 static int mt6397_irq_domain_map(struct irq_domain
*d
, unsigned int irq
,
197 struct mt6397_chip
*mt6397
= d
->host_data
;
199 irq_set_chip_data(irq
, mt6397
);
200 irq_set_chip_and_handler(irq
, &mt6397_irq_chip
, handle_level_irq
);
201 irq_set_nested_thread(irq
, 1);
202 irq_set_noprobe(irq
);
207 static const struct irq_domain_ops mt6397_irq_domain_ops
= {
208 .map
= mt6397_irq_domain_map
,
211 static int mt6397_irq_init(struct mt6397_chip
*mt6397
)
215 mutex_init(&mt6397
->irqlock
);
217 /* Mask all interrupt sources */
218 regmap_write(mt6397
->regmap
, mt6397
->int_con
[0], 0x0);
219 regmap_write(mt6397
->regmap
, mt6397
->int_con
[1], 0x0);
221 mt6397
->irq_domain
= irq_domain_add_linear(mt6397
->dev
->of_node
,
222 MT6397_IRQ_NR
, &mt6397_irq_domain_ops
, mt6397
);
223 if (!mt6397
->irq_domain
) {
224 dev_err(mt6397
->dev
, "could not create irq domain\n");
228 ret
= devm_request_threaded_irq(mt6397
->dev
, mt6397
->irq
, NULL
,
229 mt6397_irq_thread
, IRQF_ONESHOT
, "mt6397-pmic", mt6397
);
231 dev_err(mt6397
->dev
, "failed to register irq=%d; err: %d\n",
239 #ifdef CONFIG_PM_SLEEP
240 static int mt6397_irq_suspend(struct device
*dev
)
242 struct mt6397_chip
*chip
= dev_get_drvdata(dev
);
244 regmap_write(chip
->regmap
, chip
->int_con
[0], chip
->wake_mask
[0]);
245 regmap_write(chip
->regmap
, chip
->int_con
[1], chip
->wake_mask
[1]);
247 enable_irq_wake(chip
->irq
);
252 static int mt6397_irq_resume(struct device
*dev
)
254 struct mt6397_chip
*chip
= dev_get_drvdata(dev
);
256 regmap_write(chip
->regmap
, chip
->int_con
[0], chip
->irq_masks_cur
[0]);
257 regmap_write(chip
->regmap
, chip
->int_con
[1], chip
->irq_masks_cur
[1]);
259 disable_irq_wake(chip
->irq
);
265 static SIMPLE_DEV_PM_OPS(mt6397_pm_ops
, mt6397_irq_suspend
,
268 static int mt6397_probe(struct platform_device
*pdev
)
272 struct mt6397_chip
*pmic
;
274 pmic
= devm_kzalloc(&pdev
->dev
, sizeof(*pmic
), GFP_KERNEL
);
278 pmic
->dev
= &pdev
->dev
;
281 * mt6397 MFD is child device of soc pmic wrapper.
282 * Regmap is set from its parent.
284 pmic
->regmap
= dev_get_regmap(pdev
->dev
.parent
, NULL
);
288 platform_set_drvdata(pdev
, pmic
);
290 ret
= regmap_read(pmic
->regmap
, MT6397_CID
, &id
);
292 dev_err(pmic
->dev
, "Failed to read chip id: %d\n", ret
);
296 pmic
->irq
= platform_get_irq(pdev
, 0);
301 case MT6323_CID_CODE
:
302 pmic
->int_con
[0] = MT6323_INT_CON0
;
303 pmic
->int_con
[1] = MT6323_INT_CON1
;
304 pmic
->int_status
[0] = MT6323_INT_STATUS0
;
305 pmic
->int_status
[1] = MT6323_INT_STATUS1
;
306 ret
= mt6397_irq_init(pmic
);
310 ret
= devm_mfd_add_devices(&pdev
->dev
, -1, mt6323_devs
,
311 ARRAY_SIZE(mt6323_devs
), NULL
,
312 0, pmic
->irq_domain
);
315 case MT6397_CID_CODE
:
316 case MT6391_CID_CODE
:
317 pmic
->int_con
[0] = MT6397_INT_CON0
;
318 pmic
->int_con
[1] = MT6397_INT_CON1
;
319 pmic
->int_status
[0] = MT6397_INT_STATUS0
;
320 pmic
->int_status
[1] = MT6397_INT_STATUS1
;
321 ret
= mt6397_irq_init(pmic
);
325 ret
= devm_mfd_add_devices(&pdev
->dev
, -1, mt6397_devs
,
326 ARRAY_SIZE(mt6397_devs
), NULL
,
327 0, pmic
->irq_domain
);
331 dev_err(&pdev
->dev
, "unsupported chip: %d\n", id
);
337 irq_domain_remove(pmic
->irq_domain
);
338 dev_err(&pdev
->dev
, "failed to add child devices: %d\n", ret
);
344 static const struct of_device_id mt6397_of_match
[] = {
345 { .compatible
= "mediatek,mt6397" },
346 { .compatible
= "mediatek,mt6323" },
349 MODULE_DEVICE_TABLE(of
, mt6397_of_match
);
351 static const struct platform_device_id mt6397_id
[] = {
355 MODULE_DEVICE_TABLE(platform
, mt6397_id
);
357 static struct platform_driver mt6397_driver
= {
358 .probe
= mt6397_probe
,
361 .of_match_table
= of_match_ptr(mt6397_of_match
),
362 .pm
= &mt6397_pm_ops
,
364 .id_table
= mt6397_id
,
367 module_platform_driver(mt6397_driver
);
369 MODULE_AUTHOR("Flora Fu, MediaTek");
370 MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
371 MODULE_LICENSE("GPL");