arch/mips/rb532/devices.c

   1 /*
   2  *  RouterBoard 500 Platform devices
   3  *
   4  *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
   5  *  Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  *  GNU General Public License for more details.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/export.h>
  19 #include <linux/init.h>
  20 #include <linux/ctype.h>
  21 #include <linux/string.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/mtd/platnand.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/gpio.h>
  26 #include <linux/gpio/machine.h>
  27 #include <linux/gpio_keys.h>
  28 #include <linux/input.h>
  29 #include <linux/serial_8250.h>
  30
  31 #include <asm/bootinfo.h>
  32
  33 #include <asm/mach-rc32434/rc32434.h>
  34 #include <asm/mach-rc32434/dma.h>
  35 #include <asm/mach-rc32434/dma_v.h>
  36 #include <asm/mach-rc32434/eth.h>
  37 #include <asm/mach-rc32434/rb.h>
  38 #include <asm/mach-rc32434/integ.h>
  39 #include <asm/mach-rc32434/gpio.h>
  40 #include <asm/mach-rc32434/irq.h>
  41
  42 #define ETH0_RX_DMA_ADDR  (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
  43 #define ETH0_TX_DMA_ADDR  (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
  44
  45 extern unsigned int idt_cpu_freq;
  46
  47 static struct mpmc_device dev3;
  48
  49 void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
  50 {
  51         unsigned long flags;
  52
  53         spin_lock_irqsave(&dev3.lock, flags);
  54
  55         dev3.state = (dev3.state | or_mask) & ~nand_mask;
  56         writeb(dev3.state, dev3.base);
  57
  58         spin_unlock_irqrestore(&dev3.lock, flags);
  59 }
  60 EXPORT_SYMBOL(set_latch_u5);
  61
  62 unsigned char get_latch_u5(void)
  63 {
  64         return dev3.state;
  65 }
  66 EXPORT_SYMBOL(get_latch_u5);
  67
  68 static struct resource korina_dev0_res[] = {
  69         {
  70                 .name = "korina_regs",
  71                 .start = ETH0_BASE_ADDR,
  72                 .end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
  73                 .flags = IORESOURCE_MEM,
  74          }, {
  75                 .name = "korina_rx",
  76                 .start = ETH0_DMA_RX_IRQ,
  77                 .end = ETH0_DMA_RX_IRQ,
  78                 .flags = IORESOURCE_IRQ
  79         }, {
  80                 .name = "korina_tx",
  81                 .start = ETH0_DMA_TX_IRQ,
  82                 .end = ETH0_DMA_TX_IRQ,
  83                 .flags = IORESOURCE_IRQ
  84         }, {
  85                 .name = "korina_ovr",
  86                 .start = ETH0_RX_OVR_IRQ,
  87                 .end = ETH0_RX_OVR_IRQ,
  88                 .flags = IORESOURCE_IRQ
  89         }, {
  90                 .name = "korina_und",
  91                 .start = ETH0_TX_UND_IRQ,
  92                 .end = ETH0_TX_UND_IRQ,
  93                 .flags = IORESOURCE_IRQ
  94         }, {
  95                 .name = "korina_dma_rx",
  96                 .start = ETH0_RX_DMA_ADDR,
  97                 .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
  98                 .flags = IORESOURCE_MEM,
  99          }, {
 100                 .name = "korina_dma_tx",
 101                 .start = ETH0_TX_DMA_ADDR,
 102                 .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
 103                 .flags = IORESOURCE_MEM,
 104          }
 105 };
 106
 107 static struct korina_device korina_dev0_data = {
 108         .name = "korina0",
 109         .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
 110 };
 111
 112 static struct platform_device korina_dev0 = {
 113         .id = -1,
 114         .name = "korina",
 115         .resource = korina_dev0_res,
 116         .num_resources = ARRAY_SIZE(korina_dev0_res),
 117 };
 118
 119 static struct resource cf_slot0_res[] = {
 120         {
 121                 .name = "cf_membase",
 122                 .flags = IORESOURCE_MEM
 123         }, {
 124                 .name = "cf_irq",
 125                 .start = (8 + 4 * 32 + CF_GPIO_NUM),    /* 149 */
 126                 .end = (8 + 4 * 32 + CF_GPIO_NUM),
 127                 .flags = IORESOURCE_IRQ
 128         }
 129 };
 130
 131 static struct gpiod_lookup_table cf_slot0_gpio_table = {
 132         .dev_id = "pata-rb532-cf",
 133         .table = {
 134                 GPIO_LOOKUP("gpio0", CF_GPIO_NUM,
 135                             NULL, GPIO_ACTIVE_HIGH),
 136                 { },
 137         },
 138 };
 139
 140 static struct platform_device cf_slot0 = {
 141         .id = -1,
 142         .name = "pata-rb532-cf",
 143         .resource = cf_slot0_res,
 144         .num_resources = ARRAY_SIZE(cf_slot0_res),
 145 };
 146
 147 /* Resources and device for NAND */
 148 static int rb532_dev_ready(struct nand_chip *chip)
 149 {
 150         return gpio_get_value(GPIO_RDY);
 151 }
 152
 153 static void rb532_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl)
 154 {
 155         unsigned char orbits, nandbits;
 156
 157         if (ctrl & NAND_CTRL_CHANGE) {
 158                 orbits = (ctrl & NAND_CLE) << 1;
 159                 orbits |= (ctrl & NAND_ALE) >> 1;
 160
 161                 nandbits = (~ctrl & NAND_CLE) << 1;
 162                 nandbits |= (~ctrl & NAND_ALE) >> 1;
 163
 164                 set_latch_u5(orbits, nandbits);
 165         }
 166         if (cmd != NAND_CMD_NONE)
 167                 writeb(cmd, chip->legacy.IO_ADDR_W);
 168 }
 169
 170 static struct resource nand_slot0_res[] = {
 171         [0] = {
 172                 .name = "nand_membase",
 173                 .flags = IORESOURCE_MEM
 174         }
 175 };
 176
 177 static struct platform_nand_data rb532_nand_data = {
 178         .ctrl.dev_ready = rb532_dev_ready,
 179         .ctrl.cmd_ctrl  = rb532_cmd_ctrl,
 180 };
 181
 182 static struct platform_device nand_slot0 = {
 183         .name = "gen_nand",
 184         .id = -1,
 185         .resource = nand_slot0_res,
 186         .num_resources = ARRAY_SIZE(nand_slot0_res),
 187         .dev.platform_data = &rb532_nand_data,
 188 };
 189
 190 static struct mtd_partition rb532_partition_info[] = {
 191         {
 192                 .name = "Routerboard NAND boot",
 193                 .offset = 0,
 194                 .size = 4 * 1024 * 1024,
 195         }, {
 196                 .name = "rootfs",
 197                 .offset = MTDPART_OFS_NXTBLK,
 198                 .size = MTDPART_SIZ_FULL,
 199         }
 200 };
 201
 202 static struct platform_device rb532_led = {
 203         .name = "rb532-led",
 204         .id = -1,
 205 };
 206
 207 static struct platform_device rb532_button = {
 208         .name   = "rb532-button",
 209         .id     = -1,
 210 };
 211
 212 static struct resource rb532_wdt_res[] = {
 213         {
 214                 .name = "rb532_wdt_res",
 215                 .start = INTEG0_BASE_ADDR,
 216                 .end = INTEG0_BASE_ADDR + sizeof(struct integ),
 217                 .flags = IORESOURCE_MEM,
 218         }
 219 };
 220
 221 static struct platform_device rb532_wdt = {
 222         .name           = "rc32434_wdt",
 223         .id             = -1,
 224         .resource       = rb532_wdt_res,
 225         .num_resources  = ARRAY_SIZE(rb532_wdt_res),
 226 };
 227
 228 static struct plat_serial8250_port rb532_uart_res[] = {
 229         {
 230                 .type           = PORT_16550A,
 231                 .membase        = (char *)KSEG1ADDR(REGBASE + UART0BASE),
 232                 .irq            = UART0_IRQ,
 233                 .regshift       = 2,
 234                 .iotype         = UPIO_MEM,
 235                 .flags          = UPF_BOOT_AUTOCONF,
 236         },
 237         {
 238                 .flags          = 0,
 239         }
 240 };
 241
 242 static struct platform_device rb532_uart = {
 243         .name              = "serial8250",
 244         .id                = PLAT8250_DEV_PLATFORM,
 245         .dev.platform_data = &rb532_uart_res,
 246 };
 247
 248 static struct platform_device *rb532_devs[] = {
 249         &korina_dev0,
 250         &nand_slot0,
 251         &cf_slot0,
 252         &rb532_led,
 253         &rb532_button,
 254         &rb532_uart,
 255         &rb532_wdt
 256 };
 257
 258 /* NAND definitions */
 259 #define NAND_CHIP_DELAY 25
 260
 261 static void __init rb532_nand_setup(void)
 262 {
 263         switch (mips_machtype) {
 264         case MACH_MIKROTIK_RB532A:
 265                 set_latch_u5(LO_FOFF | LO_CEX,
 266                                 LO_ULED | LO_ALE | LO_CLE | LO_WPX);
 267                 break;
 268         default:
 269                 set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
 270                                 LO_ULED | LO_ALE | LO_CLE);
 271                 break;
 272         }
 273
 274         /* Setup NAND specific settings */
 275         rb532_nand_data.chip.nr_chips = 1;
 276         rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
 277         rb532_nand_data.chip.partitions = rb532_partition_info;
 278         rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
 279 }
 280
 281
 282 static int __init plat_setup_devices(void)
 283 {
 284         /* Look for the CF card reader */
 285         if (!readl(IDT434_REG_BASE + DEV1MASK))
 286                 rb532_devs[2] = NULL;   /* disable cf_slot0 at index 2 */
 287         else {
 288                 cf_slot0_res[0].start =
 289                     readl(IDT434_REG_BASE + DEV1BASE);
 290                 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
 291         }
 292
 293         /* Read the NAND resources from the device controller */
 294         nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
 295         nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
 296
 297         /* Read and map device controller 3 */
 298         dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1);
 299
 300         if (!dev3.base) {
 301                 printk(KERN_ERR "rb532: cannot remap device controller 3\n");
 302                 return -ENXIO;
 303         }
 304
 305         /* Initialise the NAND device */
 306         rb532_nand_setup();
 307
 308         /* set the uart clock to the current cpu frequency */
 309         rb532_uart_res[0].uartclk = idt_cpu_freq;
 310
 311         dev_set_drvdata(&korina_dev0.dev, &korina_dev0_data);
 312
 313         gpiod_add_lookup_table(&cf_slot0_gpio_table);
 314         return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
 315 }
 316
 317 #ifdef CONFIG_NET
 318
 319 static int __init setup_kmac(char *s)
 320 {
 321         printk(KERN_INFO "korina mac = %s\n", s);
 322         if (!mac_pton(s, korina_dev0_data.mac)) {
 323                 printk(KERN_ERR "Invalid mac\n");
 324                 return -EINVAL;
 325         }
 326         return 0;
 327 }
 328
 329 __setup("kmac=", setup_kmac);
 330
 331 #endif /* CONFIG_NET */
 332
 333 arch_initcall(plat_setup_devices);