4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
8 * Modifications for the OpenRISC architecture:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
18 #include <linux/signal.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/string.h>
23 #include <linux/types.h>
24 #include <linux/ptrace.h>
25 #include <linux/mman.h>
27 #include <linux/swap.h>
28 #include <linux/smp.h>
29 #include <linux/memblock.h>
30 #include <linux/init.h>
31 #include <linux/delay.h>
32 #include <linux/blkdev.h> /* for initrd_* */
33 #include <linux/pagemap.h>
35 #include <asm/segment.h>
36 #include <asm/pgalloc.h>
37 #include <asm/pgtable.h>
41 #include <asm/mmu_context.h>
42 #include <asm/kmap_types.h>
43 #include <asm/fixmap.h>
44 #include <asm/tlbflush.h>
45 #include <asm/sections.h>
49 DEFINE_PER_CPU(struct mmu_gather
, mmu_gathers
);
51 static void __init
zone_sizes_init(void)
53 unsigned long zones_size
[MAX_NR_ZONES
];
55 /* Clear the zone sizes */
56 memset(zones_size
, 0, sizeof(zones_size
));
59 * We use only ZONE_NORMAL
61 zones_size
[ZONE_NORMAL
] = max_low_pfn
;
63 free_area_init(zones_size
);
66 extern const char _s_kernel_ro
[], _e_kernel_ro
[];
69 * Map all physical memory into kernel's address space.
71 * This is explicitly coded for two-level page tables, so if you need
72 * something else then this needs to change.
74 static void __init
map_ram(void)
76 unsigned long v
, p
, e
;
82 /* These mark extents of read-only kernel pages...
83 * ...from vmlinux.lds.S
85 struct memblock_region
*region
;
89 for_each_memblock(memory
, region
) {
90 p
= (u32
) region
->base
& PAGE_MASK
;
91 e
= p
+ (u32
) region
->size
;
94 pge
= pgd_offset_k(v
);
98 pue
= pud_offset(pge
, v
);
99 pme
= pmd_offset(pue
, v
);
101 if ((u32
) pue
!= (u32
) pge
|| (u32
) pme
!= (u32
) pge
) {
102 panic("%s: OR1K kernel hardcoded for "
103 "two-level page tables",
107 /* Alloc one page for holding PTE's... */
108 pte
= (pte_t
*) __va(memblock_phys_alloc(PAGE_SIZE
, PAGE_SIZE
));
109 set_pmd(pme
, __pmd(_KERNPG_TABLE
+ __pa(pte
)));
111 /* Fill the newly allocated page with PTE'S */
112 for (j
= 0; p
< e
&& j
< PTRS_PER_PTE
;
113 v
+= PAGE_SIZE
, p
+= PAGE_SIZE
, j
++, pte
++) {
114 if (v
>= (u32
) _e_kernel_ro
||
115 v
< (u32
) _s_kernel_ro
)
118 prot
= PAGE_KERNEL_RO
;
120 set_pte(pte
, mk_pte_phys(p
, prot
));
126 printk(KERN_INFO
"%s: Memory: 0x%x-0x%x\n", __func__
,
127 region
->base
, region
->base
+ region
->size
);
131 void __init
paging_init(void)
133 extern void tlb_init(void);
138 printk(KERN_INFO
"Setting up paging and PTEs.\n");
140 /* clear out the init_mm.pgd that will contain the kernel's mappings */
142 for (i
= 0; i
< PTRS_PER_PGD
; i
++)
143 swapper_pg_dir
[i
] = __pgd(0);
145 /* make sure the current pgd table points to something sane
146 * (even if it is most probably not used until the next
149 current_pgd
[smp_processor_id()] = init_mm
.pgd
;
151 end
= (unsigned long)__va(max_low_pfn
* PAGE_SIZE
);
157 /* self modifying code ;) */
158 /* Since the old TLB miss handler has been running up until now,
159 * the kernel pages are still all RW, so we can still modify the
160 * text directly... after this change and a TLB flush, the kernel
161 * pages will become RO.
164 extern unsigned long dtlb_miss_handler
;
165 extern unsigned long itlb_miss_handler
;
167 unsigned long *dtlb_vector
= __va(0x900);
168 unsigned long *itlb_vector
= __va(0xa00);
170 printk(KERN_INFO
"itlb_miss_handler %p\n", &itlb_miss_handler
);
171 *itlb_vector
= ((unsigned long)&itlb_miss_handler
-
172 (unsigned long)itlb_vector
) >> 2;
174 /* Soft ordering constraint to ensure that dtlb_vector is
175 * the last thing updated
179 printk(KERN_INFO
"dtlb_miss_handler %p\n", &dtlb_miss_handler
);
180 *dtlb_vector
= ((unsigned long)&dtlb_miss_handler
-
181 (unsigned long)dtlb_vector
) >> 2;
185 /* Soft ordering constraint to ensure that cache invalidation and
186 * TLB flush really happen _after_ code has been modified.
190 /* Invalidate instruction caches after code modification */
191 mtspr(SPR_ICBIR
, 0x900);
192 mtspr(SPR_ICBIR
, 0xa00);
194 /* New TLB miss handlers and kernel page tables are in now place.
195 * Make sure that page flags get updated for all pages in TLB by
196 * flushing the TLB and forcing all TLB entries to be recreated
197 * from their page table flags.
202 /* References to section boundaries */
204 void __init
mem_init(void)
208 max_mapnr
= max_low_pfn
;
209 high_memory
= (void *)__va(max_low_pfn
* PAGE_SIZE
);
211 /* clear the zero-page */
212 memset((void *)empty_zero_page
, 0, PAGE_SIZE
);
214 /* this will put all low memory onto the freelists */
217 mem_init_print_info(NULL
);
219 printk("mem_init_done ...........................................\n");
224 #ifdef CONFIG_BLK_DEV_INITRD
225 void free_initrd_mem(unsigned long start
, unsigned long end
)
227 free_reserved_area((void *)start
, (void *)end
, -1, "initrd");
231 void free_initmem(void)
233 free_initmem_default(-1);