arch/s390/kernel/irq.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *    Copyright IBM Corp. 2004, 2011
   4  *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
   5  *               Holger Smolinski <Holger.Smolinski@de.ibm.com>,
   6  *               Thomas Spatzier <tspat@de.ibm.com>,
   7  *
   8  * This file contains interrupt related functions.
   9  */
  10
  11 #include <linux/kernel_stat.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/seq_file.h>
  14 #include <linux/proc_fs.h>
  15 #include <linux/profile.h>
  16 #include <linux/export.h>
  17 #include <linux/kernel.h>
  18 #include <linux/ftrace.h>
  19 #include <linux/errno.h>
  20 #include <linux/slab.h>
  21 #include <linux/init.h>
  22 #include <linux/cpu.h>
  23 #include <linux/irq.h>
  24 #include <asm/irq_regs.h>
  25 #include <asm/cputime.h>
  26 #include <asm/lowcore.h>
  27 #include <asm/irq.h>
  28 #include <asm/hw_irq.h>
  29 #include "entry.h"
  30
  31 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
  32 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
  33
  34 struct irq_class {
  35         int irq;
  36         char *name;
  37         char *desc;
  38 };
  39
  40 /*
  41  * The list of "main" irq classes on s390. This is the list of interrupts
  42  * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
  43  * Historically only external and I/O interrupts have been part of /proc/stat.
  44  * We can't add the split external and I/O sub classes since the first field
  45  * in the "intr" line in /proc/stat is supposed to be the sum of all other
  46  * fields.
  47  * Since the external and I/O interrupt fields are already sums we would end
  48  * up with having a sum which accounts each interrupt twice.
  49  */
  50 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
  51         {.irq = EXT_INTERRUPT,  .name = "EXT"},
  52         {.irq = IO_INTERRUPT,   .name = "I/O"},
  53         {.irq = THIN_INTERRUPT, .name = "AIO"},
  54 };
  55
  56 /*
  57  * The list of split external and I/O interrupts that appear only in
  58  * /proc/interrupts.
  59  * In addition this list contains non external / I/O events like NMIs.
  60  */
  61 static const struct irq_class irqclass_sub_desc[] = {
  62         {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"},
  63         {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"},
  64         {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"},
  65         {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"},
  66         {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"},
  67         {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
  68         {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"},
  69         {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"},
  70         {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"},
  71         {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"},
  72         {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
  73         {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
  74         {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"},
  75         {.irq = IRQIO_CIO,  .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
  76         {.irq = IRQIO_QAI,  .name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt"},
  77         {.irq = IRQIO_DAS,  .name = "DAS", .desc = "[I/O] DASD"},
  78         {.irq = IRQIO_C15,  .name = "C15", .desc = "[I/O] 3215"},
  79         {.irq = IRQIO_C70,  .name = "C70", .desc = "[I/O] 3270"},
  80         {.irq = IRQIO_TAP,  .name = "TAP", .desc = "[I/O] Tape"},
  81         {.irq = IRQIO_VMR,  .name = "VMR", .desc = "[I/O] Unit Record Devices"},
  82         {.irq = IRQIO_LCS,  .name = "LCS", .desc = "[I/O] LCS"},
  83         {.irq = IRQIO_CTC,  .name = "CTC", .desc = "[I/O] CTC"},
  84         {.irq = IRQIO_APB,  .name = "APB", .desc = "[I/O] AP Bus"},
  85         {.irq = IRQIO_ADM,  .name = "ADM", .desc = "[I/O] EADM Subchannel"},
  86         {.irq = IRQIO_CSC,  .name = "CSC", .desc = "[I/O] CHSC Subchannel"},
  87         {.irq = IRQIO_PCI,  .name = "PCI", .desc = "[I/O] PCI Interrupt" },
  88         {.irq = IRQIO_MSI,  .name = "MSI", .desc = "[I/O] MSI Interrupt" },
  89         {.irq = IRQIO_VIR,  .name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
  90         {.irq = IRQIO_VAI,  .name = "VAI", .desc = "[I/O] Virtual I/O Devices AI"},
  91         {.irq = NMI_NMI,    .name = "NMI", .desc = "[NMI] Machine Check"},
  92         {.irq = CPU_RST,    .name = "RST", .desc = "[CPU] CPU Restart"},
  93 };
  94
  95 void __init init_IRQ(void)
  96 {
  97         BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS);
  98         init_cio_interrupts();
  99         init_airq_interrupts();
 100         init_ext_interrupts();
 101 }
 102
 103 void do_IRQ(struct pt_regs *regs, int irq)
 104 {
 105         struct pt_regs *old_regs;
 106
 107         old_regs = set_irq_regs(regs);
 108         irq_enter();
 109         if (tod_after_eq(S390_lowcore.int_clock,
 110                          S390_lowcore.clock_comparator))
 111                 /* Serve timer interrupts first. */
 112                 clock_comparator_work();
 113         generic_handle_irq(irq);
 114         irq_exit();
 115         set_irq_regs(old_regs);
 116 }
 117
 118 /*
 119  * show_interrupts is needed by /proc/interrupts.
 120  */
 121 int show_interrupts(struct seq_file *p, void *v)
 122 {
 123         int index = *(loff_t *) v;
 124         int cpu, irq;
 125
 126         get_online_cpus();
 127         if (index == 0) {
 128                 seq_puts(p, "           ");
 129                 for_each_online_cpu(cpu)
 130                         seq_printf(p, "CPU%d       ", cpu);
 131                 seq_putc(p, '\n');
 132         }
 133         if (index < NR_IRQS_BASE) {
 134                 seq_printf(p, "%s: ", irqclass_main_desc[index].name);
 135                 irq = irqclass_main_desc[index].irq;
 136                 for_each_online_cpu(cpu)
 137                         seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
 138                 seq_putc(p, '\n');
 139                 goto out;
 140         }
 141         if (index > NR_IRQS_BASE)
 142                 goto out;
 143
 144         for (index = 0; index < NR_ARCH_IRQS; index++) {
 145                 seq_printf(p, "%s: ", irqclass_sub_desc[index].name);
 146                 irq = irqclass_sub_desc[index].irq;
 147                 for_each_online_cpu(cpu)
 148                         seq_printf(p, "%10u ",
 149                                    per_cpu(irq_stat, cpu).irqs[irq]);
 150                 if (irqclass_sub_desc[index].desc)
 151                         seq_printf(p, "  %s", irqclass_sub_desc[index].desc);
 152                 seq_putc(p, '\n');
 153         }
 154 out:
 155         put_online_cpus();
 156         return 0;
 157 }
 158
 159 unsigned int arch_dynirq_lower_bound(unsigned int from)
 160 {
 161         return from < NR_IRQS_BASE ? NR_IRQS_BASE : from;
 162 }
 163
 164 /*
 165  * Switch to the asynchronous interrupt stack for softirq execution.
 166  */
 167 void do_softirq_own_stack(void)
 168 {
 169         unsigned long old, new;
 170
 171         old = current_stack_pointer();
 172         /* Check against async. stack address range. */
 173         new = S390_lowcore.async_stack;
 174         if (((new - old) >> (PAGE_SHIFT + THREAD_SIZE_ORDER)) != 0) {
 175                 CALL_ON_STACK(__do_softirq, new, 0);
 176         } else {
 177                 /* We are already on the async stack. */
 178                 __do_softirq();
 179         }
 180 }
 181
 182 /*
 183  * ext_int_hash[index] is the list head for all external interrupts that hash
 184  * to this index.
 185  */
 186 static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
 187
 188 struct ext_int_info {
 189         ext_int_handler_t handler;
 190         struct hlist_node entry;
 191         struct rcu_head rcu;
 192         u16 code;
 193 };
 194
 195 /* ext_int_hash_lock protects the handler lists for external interrupts */
 196 static DEFINE_SPINLOCK(ext_int_hash_lock);
 197
 198 static inline int ext_hash(u16 code)
 199 {
 200         BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
 201
 202         return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
 203 }
 204
 205 int register_external_irq(u16 code, ext_int_handler_t handler)
 206 {
 207         struct ext_int_info *p;
 208         unsigned long flags;
 209         int index;
 210
 211         p = kmalloc(sizeof(*p), GFP_ATOMIC);
 212         if (!p)
 213                 return -ENOMEM;
 214         p->code = code;
 215         p->handler = handler;
 216         index = ext_hash(code);
 217
 218         spin_lock_irqsave(&ext_int_hash_lock, flags);
 219         hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
 220         spin_unlock_irqrestore(&ext_int_hash_lock, flags);
 221         return 0;
 222 }
 223 EXPORT_SYMBOL(register_external_irq);
 224
 225 int unregister_external_irq(u16 code, ext_int_handler_t handler)
 226 {
 227         struct ext_int_info *p;
 228         unsigned long flags;
 229         int index = ext_hash(code);
 230
 231         spin_lock_irqsave(&ext_int_hash_lock, flags);
 232         hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
 233                 if (p->code == code && p->handler == handler) {
 234                         hlist_del_rcu(&p->entry);
 235                         kfree_rcu(p, rcu);
 236                 }
 237         }
 238         spin_unlock_irqrestore(&ext_int_hash_lock, flags);
 239         return 0;
 240 }
 241 EXPORT_SYMBOL(unregister_external_irq);
 242
 243 static irqreturn_t do_ext_interrupt(int irq, void *dummy)
 244 {
 245         struct pt_regs *regs = get_irq_regs();
 246         struct ext_code ext_code;
 247         struct ext_int_info *p;
 248         int index;
 249
 250         ext_code = *(struct ext_code *) &regs->int_code;
 251         if (ext_code.code != EXT_IRQ_CLK_COMP)
 252                 set_cpu_flag(CIF_NOHZ_DELAY);
 253
 254         index = ext_hash(ext_code.code);
 255         rcu_read_lock();
 256         hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
 257                 if (unlikely(p->code != ext_code.code))
 258                         continue;
 259                 p->handler(ext_code, regs->int_parm, regs->int_parm_long);
 260         }
 261         rcu_read_unlock();
 262         return IRQ_HANDLED;
 263 }
 264
 265 static struct irqaction external_interrupt = {
 266         .name    = "EXT",
 267         .handler = do_ext_interrupt,
 268 };
 269
 270 void __init init_ext_interrupts(void)
 271 {
 272         int idx;
 273
 274         for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
 275                 INIT_HLIST_HEAD(&ext_int_hash[idx]);
 276
 277         irq_set_chip_and_handler(EXT_INTERRUPT,
 278                                  &dummy_irq_chip, handle_percpu_irq);
 279         setup_irq(EXT_INTERRUPT, &external_interrupt);
 280 }
 281
 282 static DEFINE_SPINLOCK(irq_subclass_lock);
 283 static unsigned char irq_subclass_refcount[64];
 284
 285 void irq_subclass_register(enum irq_subclass subclass)
 286 {
 287         spin_lock(&irq_subclass_lock);
 288         if (!irq_subclass_refcount[subclass])
 289                 ctl_set_bit(0, subclass);
 290         irq_subclass_refcount[subclass]++;
 291         spin_unlock(&irq_subclass_lock);
 292 }
 293 EXPORT_SYMBOL(irq_subclass_register);
 294
 295 void irq_subclass_unregister(enum irq_subclass subclass)
 296 {
 297         spin_lock(&irq_subclass_lock);
 298         irq_subclass_refcount[subclass]--;
 299         if (!irq_subclass_refcount[subclass])
 300                 ctl_clear_bit(0, subclass);
 301         spin_unlock(&irq_subclass_lock);
 302 }
 303 EXPORT_SYMBOL(irq_subclass_unregister);