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ecryptfs: fix use with tmpfs by removing d_drop from ecryptfs_destroy_inode
[linux/fpc-iii.git] / drivers / scsi / mpt2sas / mpi / mpi2_cnfg.h
blobcf0ac9f40c97f360d1946610576212de247bba3f
1 /*
2 * Copyright (c) 2000-2009 LSI Corporation.
3 *
4 *
5 * Name: mpi2_cnfg.h
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
8 *
9 * mpi2_cnfg.h Version: 02.00.13
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
18 * Added Manufacturing Page 11.
19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
20 * define.
21 * 06-26-07 02.00.02 Adding generic structure for product-specific
22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
23 * Rework of BIOS Page 2 configuration page.
24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
25 * forms.
26 * Added configuration pages IOC Page 8 and Driver
27 * Persistent Mapping Page 0.
28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
30 * RAID Physical Disk Pages 0 and 1, RAID Configuration
31 * Page 0).
32 * Added new value for AccessStatus field of SAS Device
33 * Page 0 (_SATA_NEEDS_INITIALIZATION).
34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
37 * NVDATA.
38 * Modified IOC Page 7 to use masks and added field for
39 * SASBroadcastPrimitiveMasks.
40 * Added MPI2_CONFIG_PAGE_BIOS_4.
41 * Added MPI2_CONFIG_PAGE_LOG_0.
42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
43 * Added SAS Device IDs.
44 * Updated Integrated RAID configuration pages including
45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
46 * Page 0.
47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
50 * Added missing MaxNumRoutedSasAddresses field to
51 * MPI2_CONFIG_PAGE_EXPANDER_0.
52 * Added SAS Port Page 0.
53 * Modified structure layout for
54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
58 * to 0x000000FF.
59 * Added two new values for the Physical Disk Coercion Size
60 * bits in the Flags field of Manufacturing Page 4.
61 * Added product-specific Manufacturing pages 16 to 31.
62 * Modified Flags bits for controlling write cache on SATA
63 * drives in IO Unit Page 1.
64 * Added new bit to AdditionalControlFlags of SAS IO Unit
65 * Page 1 to control Invalid Topology Correction.
66 * Added additional defines for RAID Volume Page 0
67 * VolumeStatusFlags field.
68 * Modified meaning of RAID Volume Page 0 VolumeSettings
69 * define for auto-configure of hot-swap drives.
70 * Added SupportedPhysDisks field to RAID Volume Page 1 and
71 * added related defines.
72 * Added PhysDiskAttributes field (and related defines) to
73 * RAID Physical Disk Page 0.
74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
75 * Added three new DiscoveryStatus bits for SAS IO Unit
76 * Page 0 and SAS Expander Page 0.
77 * Removed multiplexing information from SAS IO Unit pages.
78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
79 * Removed Zone Address Resolved bit from PhyInfo and from
80 * Expander Page 0 Flags field.
81 * Added two new AccessStatus values to SAS Device Page 0
82 * for indicating routing problems. Added 3 reserved words
83 * to this page.
84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
85 * Inserted missing reserved field into structure for IOC
86 * Page 6.
87 * Added more pending task bits to RAID Volume Page 0
88 * VolumeStatusFlags defines.
89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
91 * and SAS Expander Page 0 to flag a downstream initiator
92 * when in simplified routing mode.
93 * Removed SATA Init Failure defines for DiscoveryStatus
94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
96 * Added PortGroups, DmaGroup, and ControlGroup fields to
97 * SAS Device Page 0.
98 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
99 * Unit Page 6.
100 * Added expander reduced functionality data to SAS
101 * Expander Page 0.
102 * Added SAS PHY Page 2 and SAS PHY Page 3.
103 * 07-30-09 02.00.12 Added IO Unit Page 7.
104 * Added new device ids.
105 * Added SAS IO Unit Page 5.
106 * Added partial and slumber power management capable flags
107 * to SAS Device Page 0 Flags field.
108 * Added PhyInfo defines for power condition.
109 * Added Ethernet configuration pages.
110 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
111 * Added SAS PHY Page 4 structure and defines.
112 * --------------------------------------------------------------------------
113 */
114
115 #ifndef MPI2_CNFG_H
116 #define MPI2_CNFG_H
117
118 /*****************************************************************************
119 * Configuration Page Header and defines
120 *****************************************************************************/
121
122 /* Config Page Header */
123 typedef struct _MPI2_CONFIG_PAGE_HEADER
124 {
125 U8 PageVersion; /* 0x00 */
126 U8 PageLength; /* 0x01 */
127 U8 PageNumber; /* 0x02 */
128 U8 PageType; /* 0x03 */
129 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
130 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
131
132 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
133 {
134 MPI2_CONFIG_PAGE_HEADER Struct;
135 U8 Bytes[4];
136 U16 Word16[2];
137 U32 Word32;
138 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
139 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
140
141 /* Extended Config Page Header */
142 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
143 {
144 U8 PageVersion; /* 0x00 */
145 U8 Reserved1; /* 0x01 */
146 U8 PageNumber; /* 0x02 */
147 U8 PageType; /* 0x03 */
148 U16 ExtPageLength; /* 0x04 */
149 U8 ExtPageType; /* 0x06 */
150 U8 Reserved2; /* 0x07 */
151 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
152 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
153 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
154
155 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
156 {
157 MPI2_CONFIG_PAGE_HEADER Struct;
158 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
159 U8 Bytes[8];
160 U16 Word16[4];
161 U32 Word32[2];
162 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
163 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
164
165
166 /* PageType field values */
167 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
168 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
169 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
170 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
171
172 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
173 #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
174 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
175 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
176 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
177 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
178 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
179 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
180
181 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
182
183
184 /* ExtPageType field values */
185 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
186 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
187 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
188 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
189 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
190 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
191 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
192 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
193 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
194 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
195
196
197 /*****************************************************************************
198 * PageAddress defines
199 *****************************************************************************/
200
201 /* RAID Volume PageAddress format */
202 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
203 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
204 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
205
206 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
207
208
209 /* RAID Physical Disk PageAddress format */
210 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
211 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
212 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
213 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
214
215 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
216 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
217
218
219 /* SAS Expander PageAddress format */
220 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
221 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
222 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
223 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
224
225 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
226 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
227 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
228
229
230 /* SAS Device PageAddress format */
231 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
232 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
233 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
234
235 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
236
237
238 /* SAS PHY PageAddress format */
239 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
240 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
241 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
242
243 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
244 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
245
246
247 /* SAS Port PageAddress format */
248 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
249 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
250 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
251
252 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
253
254
255 /* SAS Enclosure PageAddress format */
256 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
257 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
258 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
259
260 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
261
262
263 /* RAID Configuration PageAddress format */
264 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
265 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
266 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
267 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
268
269 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
270
271
272 /* Driver Persistent Mapping PageAddress format */
273 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
274 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
275
276 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
277 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
278 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
279
280
281 /* Ethernet PageAddress format */
282 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
283 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
284
285 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
286
287
288
289 /****************************************************************************
290 * Configuration messages
291 ****************************************************************************/
292
293 /* Configuration Request Message */
294 typedef struct _MPI2_CONFIG_REQUEST
295 {
296 U8 Action; /* 0x00 */
297 U8 SGLFlags; /* 0x01 */
298 U8 ChainOffset; /* 0x02 */
299 U8 Function; /* 0x03 */
300 U16 ExtPageLength; /* 0x04 */
301 U8 ExtPageType; /* 0x06 */
302 U8 MsgFlags; /* 0x07 */
303 U8 VP_ID; /* 0x08 */
304 U8 VF_ID; /* 0x09 */
305 U16 Reserved1; /* 0x0A */
306 U32 Reserved2; /* 0x0C */
307 U32 Reserved3; /* 0x10 */
308 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
309 U32 PageAddress; /* 0x18 */
310 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
311 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
312 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
313
314 /* values for the Action field */
315 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
316 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
317 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
318 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
319 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
320 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
321 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
322 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
323
324 /* values for SGLFlags field are in the SGL section of mpi2.h */
325
326
327 /* Config Reply Message */
328 typedef struct _MPI2_CONFIG_REPLY
329 {
330 U8 Action; /* 0x00 */
331 U8 SGLFlags; /* 0x01 */
332 U8 MsgLength; /* 0x02 */
333 U8 Function; /* 0x03 */
334 U16 ExtPageLength; /* 0x04 */
335 U8 ExtPageType; /* 0x06 */
336 U8 MsgFlags; /* 0x07 */
337 U8 VP_ID; /* 0x08 */
338 U8 VF_ID; /* 0x09 */
339 U16 Reserved1; /* 0x0A */
340 U16 Reserved2; /* 0x0C */
341 U16 IOCStatus; /* 0x0E */
342 U32 IOCLogInfo; /* 0x10 */
343 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
344 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
345 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
346
347
348
349 /*****************************************************************************
350 *
351 * C o n f i g u r a t i o n P a g e s
352 *
353 *****************************************************************************/
354
355 /****************************************************************************
356 * Manufacturing Config pages
357 ****************************************************************************/
358
359 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
360
361 /* SAS */
362 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
363 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
364 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
365 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
366 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
367 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
368 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
369
370 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
371 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
372 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
373 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
374 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
375 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
376 #define MPI2_MFGPAGE_DEVID_SAS2208_7 (0x0086)
377 #define MPI2_MFGPAGE_DEVID_SAS2208_8 (0x0087)
378
379
380 /* Manufacturing Page 0 */
381
382 typedef struct _MPI2_CONFIG_PAGE_MAN_0
383 {
384 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
385 U8 ChipName[16]; /* 0x04 */
386 U8 ChipRevision[8]; /* 0x14 */
387 U8 BoardName[16]; /* 0x1C */
388 U8 BoardAssembly[16]; /* 0x2C */
389 U8 BoardTracerNumber[16]; /* 0x3C */
390 } MPI2_CONFIG_PAGE_MAN_0,
391 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
392 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
393
394 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
395
396
397 /* Manufacturing Page 1 */
398
399 typedef struct _MPI2_CONFIG_PAGE_MAN_1
400 {
401 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
402 U8 VPD[256]; /* 0x04 */
403 } MPI2_CONFIG_PAGE_MAN_1,
404 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
405 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
406
407 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
408
409
410 typedef struct _MPI2_CHIP_REVISION_ID
411 {
412 U16 DeviceID; /* 0x00 */
413 U8 PCIRevisionID; /* 0x02 */
414 U8 Reserved; /* 0x03 */
415 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
416 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
417
418
419 /* Manufacturing Page 2 */
420
421 /*
422 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
423 * one and check Header.PageLength at runtime.
424 */
425 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
426 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
427 #endif
428
429 typedef struct _MPI2_CONFIG_PAGE_MAN_2
430 {
431 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
432 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
433 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
434 } MPI2_CONFIG_PAGE_MAN_2,
435 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
436 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
437
438 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
439
440
441 /* Manufacturing Page 3 */
442
443 /*
444 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
445 * one and check Header.PageLength at runtime.
446 */
447 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
448 #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
449 #endif
450
451 typedef struct _MPI2_CONFIG_PAGE_MAN_3
452 {
453 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
454 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
455 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
456 } MPI2_CONFIG_PAGE_MAN_3,
457 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
458 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
459
460 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
461
462
463 /* Manufacturing Page 4 */
464
465 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
466 {
467 U8 PowerSaveFlags; /* 0x00 */
468 U8 InternalOperationsSleepTime; /* 0x01 */
469 U8 InternalOperationsRunTime; /* 0x02 */
470 U8 HostIdleTime; /* 0x03 */
471 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
472 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
473 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
474
475 /* defines for the PowerSaveFlags field */
476 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
477 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
478 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
479 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
480
481 typedef struct _MPI2_CONFIG_PAGE_MAN_4
482 {
483 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
484 U32 Reserved1; /* 0x04 */
485 U32 Flags; /* 0x08 */
486 U8 InquirySize; /* 0x0C */
487 U8 Reserved2; /* 0x0D */
488 U16 Reserved3; /* 0x0E */
489 U8 InquiryData[56]; /* 0x10 */
490 U32 RAID0VolumeSettings; /* 0x48 */
491 U32 RAID1EVolumeSettings; /* 0x4C */
492 U32 RAID1VolumeSettings; /* 0x50 */
493 U32 RAID10VolumeSettings; /* 0x54 */
494 U32 Reserved4; /* 0x58 */
495 U32 Reserved5; /* 0x5C */
496 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
497 U8 MaxOCEDisks; /* 0x64 */
498 U8 ResyncRate; /* 0x65 */
499 U16 DataScrubDuration; /* 0x66 */
500 U8 MaxHotSpares; /* 0x68 */
501 U8 MaxPhysDisksPerVol; /* 0x69 */
502 U8 MaxPhysDisks; /* 0x6A */
503 U8 MaxVolumes; /* 0x6B */
504 } MPI2_CONFIG_PAGE_MAN_4,
505 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
506 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
507
508 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
509
510 /* Manufacturing Page 4 Flags field */
511 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
512 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
513
514 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
515 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
516 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
517
518 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
519 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
520 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
521 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
522 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
523
524 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
525 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
526 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
527 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
528
529 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
530 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
531 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
532 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
533 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
534 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
535 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
536 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
537
538
539 /* Manufacturing Page 5 */
540
541 /*
542 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
543 * one and check Header.PageLength or NumPhys at runtime.
544 */
545 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
546 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
547 #endif
548
549 typedef struct _MPI2_MANUFACTURING5_ENTRY
550 {
551 U64 WWID; /* 0x00 */
552 U64 DeviceName; /* 0x08 */
553 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
554 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
555
556 typedef struct _MPI2_CONFIG_PAGE_MAN_5
557 {
558 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
559 U8 NumPhys; /* 0x04 */
560 U8 Reserved1; /* 0x05 */
561 U16 Reserved2; /* 0x06 */
562 U32 Reserved3; /* 0x08 */
563 U32 Reserved4; /* 0x0C */
564 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
565 } MPI2_CONFIG_PAGE_MAN_5,
566 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
567 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
568
569 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
570
571
572 /* Manufacturing Page 6 */
573
574 typedef struct _MPI2_CONFIG_PAGE_MAN_6
575 {
576 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
577 U32 ProductSpecificInfo;/* 0x04 */
578 } MPI2_CONFIG_PAGE_MAN_6,
579 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
580 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
581
582 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
583
584
585 /* Manufacturing Page 7 */
586
587 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
588 {
589 U32 Pinout; /* 0x00 */
590 U8 Connector[16]; /* 0x04 */
591 U8 Location; /* 0x14 */
592 U8 Reserved1; /* 0x15 */
593 U16 Slot; /* 0x16 */
594 U32 Reserved2; /* 0x18 */
595 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
596 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
597
598 /* defines for the Pinout field */
599 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)
600 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)
601 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)
602 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)
603 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)
604 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)
605 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)
606 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)
607 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002)
608 #define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)
609
610 /* defines for the Location field */
611 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
612 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
613 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
614 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
615 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
616 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
617 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
618
619 /*
620 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
621 * one and check NumPhys at runtime.
622 */
623 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
624 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
625 #endif
626
627 typedef struct _MPI2_CONFIG_PAGE_MAN_7
628 {
629 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
630 U32 Reserved1; /* 0x04 */
631 U32 Reserved2; /* 0x08 */
632 U32 Flags; /* 0x0C */
633 U8 EnclosureName[16]; /* 0x10 */
634 U8 NumPhys; /* 0x20 */
635 U8 Reserved3; /* 0x21 */
636 U16 Reserved4; /* 0x22 */
637 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
638 } MPI2_CONFIG_PAGE_MAN_7,
639 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
640 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
641
642 #define MPI2_MANUFACTURING7_PAGEVERSION (0x00)
643
644 /* defines for the Flags field */
645 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
646
647
648 /*
649 * Generic structure to use for product-specific manufacturing pages
650 * (currently Manufacturing Page 8 through Manufacturing Page 31).
651 */
652
653 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
654 {
655 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
656 U32 ProductSpecificInfo;/* 0x04 */
657 } MPI2_CONFIG_PAGE_MAN_PS,
658 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
659 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
660
661 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
662 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
663 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
664 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
665 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
666 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
667 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
668 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
669 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
670 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
671 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
672 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
673 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
674 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
675 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
676 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
677 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
678 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
679 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
680 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
681 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
682 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
683 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
684 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
685
686
687 /****************************************************************************
688 * IO Unit Config Pages
689 ****************************************************************************/
690
691 /* IO Unit Page 0 */
692
693 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
694 {
695 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
696 U64 UniqueValue; /* 0x04 */
697 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
698 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
699 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
700 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
701
702 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
703
704
705 /* IO Unit Page 1 */
706
707 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
708 {
709 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
710 U32 Flags; /* 0x04 */
711 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
712 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
713
714 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
715
716 /* IO Unit Page 1 Flags defines */
717 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
718 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
719 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
720 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
721 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
722 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
723 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
724 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
725 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
726 #define MPI2_IOUNITPAGE1_MULTI_PATHING (0x00000002)
727 #define MPI2_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
728
729
730 /* IO Unit Page 3 */
731
732 /*
733 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
734 * one and check Header.PageLength at runtime.
735 */
736 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
737 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
738 #endif
739
740 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
741 {
742 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
743 U8 GPIOCount; /* 0x04 */
744 U8 Reserved1; /* 0x05 */
745 U16 Reserved2; /* 0x06 */
746 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
747 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
748 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
749
750 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
751
752 /* defines for IO Unit Page 3 GPIOVal field */
753 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
754 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
755 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
756 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
757
758
759 /* IO Unit Page 5 */
760
761 /*
762 * Upper layer code (drivers, utilities, etc.) should leave this define set to
763 * one and check Header.PageLength or NumDmaEngines at runtime.
764 */
765 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
766 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
767 #endif
768
769 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
770 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
771 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
772 U64 RaidAcceleratorBufferSize; /* 0x0C */
773 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
774 U8 RAControlSize; /* 0x1C */
775 U8 NumDmaEngines; /* 0x1D */
776 U8 RAMinControlSize; /* 0x1E */
777 U8 RAMaxControlSize; /* 0x1F */
778 U32 Reserved1; /* 0x20 */
779 U32 Reserved2; /* 0x24 */
780 U32 Reserved3; /* 0x28 */
781 U32 DmaEngineCapabilities
782 [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
783 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
784 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
785
786 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
787
788 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
789 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
790 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
791
792 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
793 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
794 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
795 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
796
797
798 /* IO Unit Page 6 */
799
800 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
801 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
802 U16 Flags; /* 0x04 */
803 U8 RAHostControlSize; /* 0x06 */
804 U8 Reserved0; /* 0x07 */
805 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
806 U32 Reserved1; /* 0x10 */
807 U32 Reserved2; /* 0x14 */
808 U32 Reserved3; /* 0x18 */
809 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
810 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
811
812 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
813
814 /* defines for IO Unit Page 6 Flags field */
815 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
816
817
818 /* IO Unit Page 7 */
819
820 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
821 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
822 U16 Reserved1; /* 0x04 */
823 U8 PCIeWidth; /* 0x06 */
824 U8 PCIeSpeed; /* 0x07 */
825 U32 ProcessorState; /* 0x08 */
826 U32 Reserved2; /* 0x0C */
827 U16 IOCTemperature; /* 0x10 */
828 U8 IOCTemperatureUnits; /* 0x12 */
829 U8 IOCSpeed; /* 0x13 */
830 U32 Reserved3; /* 0x14 */
831 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
832 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
833
834 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x00)
835
836 /* defines for IO Unit Page 7 PCIeWidth field */
837 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
838 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
839 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
840 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
841
842 /* defines for IO Unit Page 7 PCIeSpeed field */
843 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
844 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
845 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
846
847 /* defines for IO Unit Page 7 ProcessorState field */
848 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
849 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
850
851 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
852 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
853 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
854
855 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
856 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
857 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
858 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
859
860 /* defines for IO Unit Page 7 IOCSpeed field */
861 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
862 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
863 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
864 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
865
866
867
868 /****************************************************************************
869 * IOC Config Pages
870 ****************************************************************************/
871
872 /* IOC Page 0 */
873
874 typedef struct _MPI2_CONFIG_PAGE_IOC_0
875 {
876 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
877 U32 Reserved1; /* 0x04 */
878 U32 Reserved2; /* 0x08 */
879 U16 VendorID; /* 0x0C */
880 U16 DeviceID; /* 0x0E */
881 U8 RevisionID; /* 0x10 */
882 U8 Reserved3; /* 0x11 */
883 U16 Reserved4; /* 0x12 */
884 U32 ClassCode; /* 0x14 */
885 U16 SubsystemVendorID; /* 0x18 */
886 U16 SubsystemID; /* 0x1A */
887 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
888 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
889
890 #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
891
892
893 /* IOC Page 1 */
894
895 typedef struct _MPI2_CONFIG_PAGE_IOC_1
896 {
897 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
898 U32 Flags; /* 0x04 */
899 U32 CoalescingTimeout; /* 0x08 */
900 U8 CoalescingDepth; /* 0x0C */
901 U8 PCISlotNum; /* 0x0D */
902 U8 PCIBusNum; /* 0x0E */
903 U8 PCIDomainSegment; /* 0x0F */
904 U32 Reserved1; /* 0x10 */
905 U32 Reserved2; /* 0x14 */
906 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
907 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
908
909 #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
910
911 /* defines for IOC Page 1 Flags field */
912 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
913
914 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
915 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
916 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
917
918 /* IOC Page 6 */
919
920 typedef struct _MPI2_CONFIG_PAGE_IOC_6
921 {
922 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
923 U32 CapabilitiesFlags; /* 0x04 */
924 U8 MaxDrivesRAID0; /* 0x08 */
925 U8 MaxDrivesRAID1; /* 0x09 */
926 U8 MaxDrivesRAID1E; /* 0x0A */
927 U8 MaxDrivesRAID10; /* 0x0B */
928 U8 MinDrivesRAID0; /* 0x0C */
929 U8 MinDrivesRAID1; /* 0x0D */
930 U8 MinDrivesRAID1E; /* 0x0E */
931 U8 MinDrivesRAID10; /* 0x0F */
932 U32 Reserved1; /* 0x10 */
933 U8 MaxGlobalHotSpares; /* 0x14 */
934 U8 MaxPhysDisks; /* 0x15 */
935 U8 MaxVolumes; /* 0x16 */
936 U8 MaxConfigs; /* 0x17 */
937 U8 MaxOCEDisks; /* 0x18 */
938 U8 Reserved2; /* 0x19 */
939 U16 Reserved3; /* 0x1A */
940 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
941 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
942 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
943 U32 Reserved4; /* 0x28 */
944 U32 Reserved5; /* 0x2C */
945 U16 DefaultMetadataSize; /* 0x30 */
946 U16 Reserved6; /* 0x32 */
947 U16 MaxBadBlockTableEntries; /* 0x34 */
948 U16 Reserved7; /* 0x36 */
949 U32 IRNvsramVersion; /* 0x38 */
950 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
951 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
952
953 #define MPI2_IOCPAGE6_PAGEVERSION (0x04)
954
955 /* defines for IOC Page 6 CapabilitiesFlags */
956 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
957 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
958 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
959 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
960 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
961
962
963 /* IOC Page 7 */
964
965 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
966
967 typedef struct _MPI2_CONFIG_PAGE_IOC_7
968 {
969 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
970 U32 Reserved1; /* 0x04 */
971 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
972 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
973 U16 Reserved2; /* 0x1A */
974 U32 Reserved3; /* 0x1C */
975 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
976 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
977
978 #define MPI2_IOCPAGE7_PAGEVERSION (0x01)
979
980
981 /* IOC Page 8 */
982
983 typedef struct _MPI2_CONFIG_PAGE_IOC_8
984 {
985 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
986 U8 NumDevsPerEnclosure; /* 0x04 */
987 U8 Reserved1; /* 0x05 */
988 U16 Reserved2; /* 0x06 */
989 U16 MaxPersistentEntries; /* 0x08 */
990 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
991 U16 Flags; /* 0x0C */
992 U16 Reserved3; /* 0x0E */
993 U16 IRVolumeMappingFlags; /* 0x10 */
994 U16 Reserved4; /* 0x12 */
995 U32 Reserved5; /* 0x14 */
996 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
997 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
998
999 #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1000
1001 /* defines for IOC Page 8 Flags field */
1002 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1003 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1004
1005 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1006 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1007 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1008
1009 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1010 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1011
1012 /* defines for IOC Page 8 IRVolumeMappingFlags */
1013 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1014 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1015 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1016
1017
1018 /****************************************************************************
1019 * BIOS Config Pages
1020 ****************************************************************************/
1021
1022 /* BIOS Page 1 */
1023
1024 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1025 {
1026 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1027 U32 BiosOptions; /* 0x04 */
1028 U32 IOCSettings; /* 0x08 */
1029 U32 Reserved1; /* 0x0C */
1030 U32 DeviceSettings; /* 0x10 */
1031 U16 NumberOfDevices; /* 0x14 */
1032 U16 Reserved2; /* 0x16 */
1033 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
1034 U16 IOTimeoutSequential; /* 0x1A */
1035 U16 IOTimeoutOther; /* 0x1C */
1036 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
1037 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1038 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1039
1040 #define MPI2_BIOSPAGE1_PAGEVERSION (0x04)
1041
1042 /* values for BIOS Page 1 BiosOptions field */
1043 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1044
1045 /* values for BIOS Page 1 IOCSettings field */
1046 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1047 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1048 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1049
1050 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1051 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1052 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1053 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1054
1055 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1056 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1057 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1058 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1059 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1060
1061 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1062
1063 /* values for BIOS Page 1 DeviceSettings field */
1064 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1065 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1066 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1067 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1068 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1069
1070
1071 /* BIOS Page 2 */
1072
1073 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1074 {
1075 U32 Reserved1; /* 0x00 */
1076 U32 Reserved2; /* 0x04 */
1077 U32 Reserved3; /* 0x08 */
1078 U32 Reserved4; /* 0x0C */
1079 U32 Reserved5; /* 0x10 */
1080 U32 Reserved6; /* 0x14 */
1081 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1082 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1083 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1084
1085 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1086 {
1087 U64 SASAddress; /* 0x00 */
1088 U8 LUN[8]; /* 0x08 */
1089 U32 Reserved1; /* 0x10 */
1090 U32 Reserved2; /* 0x14 */
1091 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1092 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1093
1094 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1095 {
1096 U64 EnclosureLogicalID; /* 0x00 */
1097 U32 Reserved1; /* 0x08 */
1098 U32 Reserved2; /* 0x0C */
1099 U16 SlotNumber; /* 0x10 */
1100 U16 Reserved3; /* 0x12 */
1101 U32 Reserved4; /* 0x14 */
1102 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1103 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1104 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1105
1106 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1107 {
1108 U64 DeviceName; /* 0x00 */
1109 U8 LUN[8]; /* 0x08 */
1110 U32 Reserved1; /* 0x10 */
1111 U32 Reserved2; /* 0x14 */
1112 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1113 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1114
1115 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1116 {
1117 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1118 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1119 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1120 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1121 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1122 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1123
1124 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1125 {
1126 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1127 U32 Reserved1; /* 0x04 */
1128 U32 Reserved2; /* 0x08 */
1129 U32 Reserved3; /* 0x0C */
1130 U32 Reserved4; /* 0x10 */
1131 U32 Reserved5; /* 0x14 */
1132 U32 Reserved6; /* 0x18 */
1133 U8 ReqBootDeviceForm; /* 0x1C */
1134 U8 Reserved7; /* 0x1D */
1135 U16 Reserved8; /* 0x1E */
1136 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1137 U8 ReqAltBootDeviceForm; /* 0x38 */
1138 U8 Reserved9; /* 0x39 */
1139 U16 Reserved10; /* 0x3A */
1140 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1141 U8 CurrentBootDeviceForm; /* 0x58 */
1142 U8 Reserved11; /* 0x59 */
1143 U16 Reserved12; /* 0x5A */
1144 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1145 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1146 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1147
1148 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1149
1150 /* values for BIOS Page 2 BootDeviceForm fields */
1151 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1152 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1153 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1154 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1155 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1156
1157
1158 /* BIOS Page 3 */
1159
1160 typedef struct _MPI2_ADAPTER_INFO
1161 {
1162 U8 PciBusNumber; /* 0x00 */
1163 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1164 U16 AdapterFlags; /* 0x02 */
1165 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1166 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1167
1168 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1169 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1170
1171 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1172 {
1173 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1174 U32 GlobalFlags; /* 0x04 */
1175 U32 BiosVersion; /* 0x08 */
1176 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1177 U32 Reserved1; /* 0x1C */
1178 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1179 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1180
1181 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1182
1183 /* values for BIOS Page 3 GlobalFlags */
1184 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1185 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1186 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1187
1188 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1189 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1190 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1191 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1192
1193
1194 /* BIOS Page 4 */
1195
1196 /*
1197 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1198 * one and check Header.PageLength or NumPhys at runtime.
1199 */
1200 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1201 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1202 #endif
1203
1204 typedef struct _MPI2_BIOS4_ENTRY
1205 {
1206 U64 ReassignmentWWID; /* 0x00 */
1207 U64 ReassignmentDeviceName; /* 0x08 */
1208 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1209 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1210
1211 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1212 {
1213 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1214 U8 NumPhys; /* 0x04 */
1215 U8 Reserved1; /* 0x05 */
1216 U16 Reserved2; /* 0x06 */
1217 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1218 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1219 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1220
1221 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1222
1223
1224 /****************************************************************************
1225 * RAID Volume Config Pages
1226 ****************************************************************************/
1227
1228 /* RAID Volume Page 0 */
1229
1230 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1231 {
1232 U8 RAIDSetNum; /* 0x00 */
1233 U8 PhysDiskMap; /* 0x01 */
1234 U8 PhysDiskNum; /* 0x02 */
1235 U8 Reserved; /* 0x03 */
1236 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1237 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1238
1239 /* defines for the PhysDiskMap field */
1240 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1241 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1242
1243 typedef struct _MPI2_RAIDVOL0_SETTINGS
1244 {
1245 U16 Settings; /* 0x00 */
1246 U8 HotSparePool; /* 0x01 */
1247 U8 Reserved; /* 0x02 */
1248 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1249 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1250
1251 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1252 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1253 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1254 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1255 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1256 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1257 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1258 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1259 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1260
1261 /* RAID Volume Page 0 VolumeSettings defines */
1262 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1263 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1264
1265 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1266 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1267 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1268 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1269
1270 /*
1271 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1272 * one and check Header.PageLength at runtime.
1273 */
1274 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1275 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1276 #endif
1277
1278 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1279 {
1280 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1281 U16 DevHandle; /* 0x04 */
1282 U8 VolumeState; /* 0x06 */
1283 U8 VolumeType; /* 0x07 */
1284 U32 VolumeStatusFlags; /* 0x08 */
1285 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1286 U64 MaxLBA; /* 0x10 */
1287 U32 StripeSize; /* 0x18 */
1288 U16 BlockSize; /* 0x1C */
1289 U16 Reserved1; /* 0x1E */
1290 U8 SupportedPhysDisks; /* 0x20 */
1291 U8 ResyncRate; /* 0x21 */
1292 U16 DataScrubDuration; /* 0x22 */
1293 U8 NumPhysDisks; /* 0x24 */
1294 U8 Reserved2; /* 0x25 */
1295 U8 Reserved3; /* 0x26 */
1296 U8 InactiveStatus; /* 0x27 */
1297 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1298 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1299 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1300
1301 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1302
1303 /* values for RAID VolumeState */
1304 #define MPI2_RAID_VOL_STATE_MISSING (0x00)
1305 #define MPI2_RAID_VOL_STATE_FAILED (0x01)
1306 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1307 #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1308 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1309 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1310
1311 /* values for RAID VolumeType */
1312 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1313 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1314 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1315 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1316 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1317
1318 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1319 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1320 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1321 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1322 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1323 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1324 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1325 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1326 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1327 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1328 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1329 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1330 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1331 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1332 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1333 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1334 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1335 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1336 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1337
1338 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1339 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1340 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1341 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1342 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1343
1344 /* values for RAID Volume Page 0 InactiveStatus field */
1345 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1346 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1347 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1348 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1349 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1350 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1351 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1352
1353
1354 /* RAID Volume Page 1 */
1355
1356 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1357 {
1358 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1359 U16 DevHandle; /* 0x04 */
1360 U16 Reserved0; /* 0x06 */
1361 U8 GUID[24]; /* 0x08 */
1362 U8 Name[16]; /* 0x20 */
1363 U64 WWID; /* 0x30 */
1364 U32 Reserved1; /* 0x38 */
1365 U32 Reserved2; /* 0x3C */
1366 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1367 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1368
1369 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1370
1371
1372 /****************************************************************************
1373 * RAID Physical Disk Config Pages
1374 ****************************************************************************/
1375
1376 /* RAID Physical Disk Page 0 */
1377
1378 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1379 {
1380 U16 Reserved1; /* 0x00 */
1381 U8 HotSparePool; /* 0x02 */
1382 U8 Reserved2; /* 0x03 */
1383 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1384 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1385
1386 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1387
1388 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1389 {
1390 U8 VendorID[8]; /* 0x00 */
1391 U8 ProductID[16]; /* 0x08 */
1392 U8 ProductRevLevel[4]; /* 0x18 */
1393 U8 SerialNum[32]; /* 0x1C */
1394 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1395 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1396 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1397
1398 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1399 {
1400 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1401 U16 DevHandle; /* 0x04 */
1402 U8 Reserved1; /* 0x06 */
1403 U8 PhysDiskNum; /* 0x07 */
1404 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1405 U32 Reserved2; /* 0x0C */
1406 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1407 U32 Reserved3; /* 0x4C */
1408 U8 PhysDiskState; /* 0x50 */
1409 U8 OfflineReason; /* 0x51 */
1410 U8 IncompatibleReason; /* 0x52 */
1411 U8 PhysDiskAttributes; /* 0x53 */
1412 U32 PhysDiskStatusFlags; /* 0x54 */
1413 U64 DeviceMaxLBA; /* 0x58 */
1414 U64 HostMaxLBA; /* 0x60 */
1415 U64 CoercedMaxLBA; /* 0x68 */
1416 U16 BlockSize; /* 0x70 */
1417 U16 Reserved5; /* 0x72 */
1418 U32 Reserved6; /* 0x74 */
1419 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1420 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1421 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1422
1423 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1424
1425 /* PhysDiskState defines */
1426 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1427 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1428 #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1429 #define MPI2_RAID_PD_STATE_ONLINE (0x03)
1430 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1431 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1432 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1433 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1434
1435 /* OfflineReason defines */
1436 #define MPI2_PHYSDISK0_ONLINE (0x00)
1437 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1438 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1439 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1440 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1441 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1442 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1443
1444 /* IncompatibleReason defines */
1445 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1446 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1447 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1448 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1449 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1450 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1451 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1452
1453 /* PhysDiskAttributes defines */
1454 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1455 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1456 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1457 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1458
1459 /* PhysDiskStatusFlags defines */
1460 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1461 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1462 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1463 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1464 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1465 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1466 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1467 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1468
1469
1470 /* RAID Physical Disk Page 1 */
1471
1472 /*
1473 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1474 * one and check Header.PageLength or NumPhysDiskPaths at runtime.
1475 */
1476 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1477 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1478 #endif
1479
1480 typedef struct _MPI2_RAIDPHYSDISK1_PATH
1481 {
1482 U16 DevHandle; /* 0x00 */
1483 U16 Reserved1; /* 0x02 */
1484 U64 WWID; /* 0x04 */
1485 U64 OwnerWWID; /* 0x0C */
1486 U8 OwnerIdentifier; /* 0x14 */
1487 U8 Reserved2; /* 0x15 */
1488 U16 Flags; /* 0x16 */
1489 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1490 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1491
1492 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1493 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1494 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1495 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1496
1497 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1498 {
1499 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1500 U8 NumPhysDiskPaths; /* 0x04 */
1501 U8 PhysDiskNum; /* 0x05 */
1502 U16 Reserved1; /* 0x06 */
1503 U32 Reserved2; /* 0x08 */
1504 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1505 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1506 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1507 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1508
1509 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1510
1511
1512 /****************************************************************************
1513 * values for fields used by several types of SAS Config Pages
1514 ****************************************************************************/
1515
1516 /* values for NegotiatedLinkRates fields */
1517 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1518 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1519 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1520 /* link rates used for Negotiated Physical and Logical Link Rate */
1521 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1522 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1523 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1524 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1525 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1526 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1527 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1528 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1529 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1530
1531
1532 /* values for AttachedPhyInfo fields */
1533 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1534 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1535 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1536
1537 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1538 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1539 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1540 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1541 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1542 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1543 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1544 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1545 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1546 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1547
1548
1549 /* values for PhyInfo fields */
1550 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1551
1552 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1553 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1554 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1555 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1556
1557 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1558 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1559 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1560 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1561 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1562 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1563
1564 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1565 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1566 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1567 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1568 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1569 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1570 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1571 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1572 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1573 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1574
1575 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1576 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1577 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1578 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1579
1580 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1581 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1582
1583 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1584 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1585 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1586 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1587
1588
1589 /* values for SAS ProgrammedLinkRate fields */
1590 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1591 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1592 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1593 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1594 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1595 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1596 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1597 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1598 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1599 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1600
1601
1602 /* values for SAS HwLinkRate fields */
1603 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1604 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1605 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1606 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1607 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1608 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1609 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1610 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1611
1612
1613
1614 /****************************************************************************
1615 * SAS IO Unit Config Pages
1616 ****************************************************************************/
1617
1618 /* SAS IO Unit Page 0 */
1619
1620 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1621 {
1622 U8 Port; /* 0x00 */
1623 U8 PortFlags; /* 0x01 */
1624 U8 PhyFlags; /* 0x02 */
1625 U8 NegotiatedLinkRate; /* 0x03 */
1626 U32 ControllerPhyDeviceInfo;/* 0x04 */
1627 U16 AttachedDevHandle; /* 0x08 */
1628 U16 ControllerDevHandle; /* 0x0A */
1629 U32 DiscoveryStatus; /* 0x0C */
1630 U32 Reserved; /* 0x10 */
1631 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1632 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1633
1634 /*
1635 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1636 * one and check Header.ExtPageLength or NumPhys at runtime.
1637 */
1638 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1639 #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1640 #endif
1641
1642 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1643 {
1644 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1645 U32 Reserved1; /* 0x08 */
1646 U8 NumPhys; /* 0x0C */
1647 U8 Reserved2; /* 0x0D */
1648 U16 Reserved3; /* 0x0E */
1649 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1650 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1651 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1652 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1653
1654 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1655
1656 /* values for SAS IO Unit Page 0 PortFlags */
1657 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1658 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1659
1660 /* values for SAS IO Unit Page 0 PhyFlags */
1661 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1662 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1663
1664 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1665
1666 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1667
1668 /* values for SAS IO Unit Page 0 DiscoveryStatus */
1669 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1670 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1671 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1672 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1673 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1674 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1675 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1676 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1677 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1678 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1679 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1680 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1681 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1682 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1683 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1684 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1685 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1686 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1687 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1688 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1689
1690
1691 /* SAS IO Unit Page 1 */
1692
1693 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1694 {
1695 U8 Port; /* 0x00 */
1696 U8 PortFlags; /* 0x01 */
1697 U8 PhyFlags; /* 0x02 */
1698 U8 MaxMinLinkRate; /* 0x03 */
1699 U32 ControllerPhyDeviceInfo; /* 0x04 */
1700 U16 MaxTargetPortConnectTime; /* 0x08 */
1701 U16 Reserved1; /* 0x0A */
1702 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1703 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1704
1705 /*
1706 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1707 * one and check Header.ExtPageLength or NumPhys at runtime.
1708 */
1709 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1710 #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1711 #endif
1712
1713 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1714 {
1715 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1716 U16 ControlFlags; /* 0x08 */
1717 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1718 U16 AdditionalControlFlags; /* 0x0C */
1719 U16 SASWideMaxQueueDepth; /* 0x0E */
1720 U8 NumPhys; /* 0x10 */
1721 U8 SATAMaxQDepth; /* 0x11 */
1722 U8 ReportDeviceMissingDelay; /* 0x12 */
1723 U8 IODeviceMissingDelay; /* 0x13 */
1724 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1725 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
1726 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1727 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1728
1729 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1730
1731 /* values for SAS IO Unit Page 1 ControlFlags */
1732 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1733 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1734 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1735 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1736
1737 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1738 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1739 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1740 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1741 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1742
1743 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1744 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1745 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1746 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1747 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1748 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1749 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1750 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
1751
1752 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
1753 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1754 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1755 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1756 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1757 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1758 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1759 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1760 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1761
1762 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1763 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1764 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1765
1766 /* values for SAS IO Unit Page 1 PortFlags */
1767 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1768
1769 /* values for SAS IO Unit Page 1 PhyFlags */
1770 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1771 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1772
1773 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
1774 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1775 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1776 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1777 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1778 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1779 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1780 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1781 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1782
1783 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1784
1785
1786 /* SAS IO Unit Page 4 */
1787
1788 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1789 {
1790 U8 MaxTargetSpinup; /* 0x00 */
1791 U8 SpinupDelay; /* 0x01 */
1792 U16 Reserved1; /* 0x02 */
1793 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1794 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1795
1796 /*
1797 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1798 * four and check Header.ExtPageLength or NumPhys at runtime.
1799 */
1800 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1801 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
1802 #endif
1803
1804 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
1805 {
1806 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1807 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
1808 U32 Reserved1; /* 0x18 */
1809 U32 Reserved2; /* 0x1C */
1810 U32 Reserved3; /* 0x20 */
1811 U8 BootDeviceWaitTime; /* 0x24 */
1812 U8 Reserved4; /* 0x25 */
1813 U16 Reserved5; /* 0x26 */
1814 U8 NumPhys; /* 0x28 */
1815 U8 PEInitialSpinupDelay; /* 0x29 */
1816 U8 PEReplyDelay; /* 0x2A */
1817 U8 Flags; /* 0x2B */
1818 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
1819 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
1820 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
1821 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
1822
1823 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
1824
1825 /* defines for Flags field */
1826 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
1827
1828 /* defines for PHY field */
1829 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
1830
1831
1832 /* SAS IO Unit Page 5 */
1833
1834 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
1835 U8 ControlFlags; /* 0x00 */
1836 U8 Reserved1; /* 0x01 */
1837 U16 InactivityTimerExponent; /* 0x02 */
1838 U8 SATAPartialTimeout; /* 0x04 */
1839 U8 Reserved2; /* 0x05 */
1840 U8 SATASlumberTimeout; /* 0x06 */
1841 U8 Reserved3; /* 0x07 */
1842 U8 SASPartialTimeout; /* 0x08 */
1843 U8 Reserved4; /* 0x09 */
1844 U8 SASSlumberTimeout; /* 0x0A */
1845 U8 Reserved5; /* 0x0B */
1846 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1847 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1848 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
1849
1850 /* defines for ControlFlags field */
1851 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
1852 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
1853 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
1854 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
1855
1856 /* defines for InactivityTimerExponent field */
1857 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
1858 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
1859 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
1860 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
1861 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
1862 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
1863 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
1864 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
1865
1866 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
1867 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
1868 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
1869 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
1870 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
1871 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
1872 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
1873 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
1874
1875 /*
1876 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1877 * one and check Header.ExtPageLength or NumPhys at runtime.
1878 */
1879 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
1880 #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
1881 #endif
1882
1883 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
1884 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1885 U8 NumPhys; /* 0x08 */
1886 U8 Reserved1; /* 0x09 */
1887 U16 Reserved2; /* 0x0A */
1888 U32 Reserved3; /* 0x0C */
1889 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings
1890 [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
1891 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
1892 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
1893 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
1894
1895 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x00)
1896
1897
1898
1899
1900 /****************************************************************************
1901 * SAS Expander Config Pages
1902 ****************************************************************************/
1903
1904 /* SAS Expander Page 0 */
1905
1906 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
1907 {
1908 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1909 U8 PhysicalPort; /* 0x08 */
1910 U8 ReportGenLength; /* 0x09 */
1911 U16 EnclosureHandle; /* 0x0A */
1912 U64 SASAddress; /* 0x0C */
1913 U32 DiscoveryStatus; /* 0x14 */
1914 U16 DevHandle; /* 0x18 */
1915 U16 ParentDevHandle; /* 0x1A */
1916 U16 ExpanderChangeCount; /* 0x1C */
1917 U16 ExpanderRouteIndexes; /* 0x1E */
1918 U8 NumPhys; /* 0x20 */
1919 U8 SASLevel; /* 0x21 */
1920 U16 Flags; /* 0x22 */
1921 U16 STPBusInactivityTimeLimit; /* 0x24 */
1922 U16 STPMaxConnectTimeLimit; /* 0x26 */
1923 U16 STP_SMP_NexusLossTime; /* 0x28 */
1924 U16 MaxNumRoutedSasAddresses; /* 0x2A */
1925 U64 ActiveZoneManagerSASAddress;/* 0x2C */
1926 U16 ZoneLockInactivityLimit; /* 0x34 */
1927 U16 Reserved1; /* 0x36 */
1928 U8 TimeToReducedFunc; /* 0x38 */
1929 U8 InitialTimeToReducedFunc; /* 0x39 */
1930 U8 MaxReducedFuncTime; /* 0x3A */
1931 U8 Reserved2; /* 0x3B */
1932 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
1933 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
1934
1935 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
1936
1937 /* values for SAS Expander Page 0 DiscoveryStatus field */
1938 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1939 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1940 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
1941 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1942 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1943 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1944 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1945 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
1946 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1947 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
1948 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
1949 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
1950 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
1951 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
1952 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
1953 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1954 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
1955 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
1956 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1957 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
1958
1959 /* values for SAS Expander Page 0 Flags field */
1960 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
1961 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
1962 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
1963 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
1964 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
1965 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
1966 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
1967 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
1968 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
1969 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
1970 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
1971
1972
1973 /* SAS Expander Page 1 */
1974
1975 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
1976 {
1977 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1978 U8 PhysicalPort; /* 0x08 */
1979 U8 Reserved1; /* 0x09 */
1980 U16 Reserved2; /* 0x0A */
1981 U8 NumPhys; /* 0x0C */
1982 U8 Phy; /* 0x0D */
1983 U16 NumTableEntriesProgrammed; /* 0x0E */
1984 U8 ProgrammedLinkRate; /* 0x10 */
1985 U8 HwLinkRate; /* 0x11 */
1986 U16 AttachedDevHandle; /* 0x12 */
1987 U32 PhyInfo; /* 0x14 */
1988 U32 AttachedDeviceInfo; /* 0x18 */
1989 U16 ExpanderDevHandle; /* 0x1C */
1990 U8 ChangeCount; /* 0x1E */
1991 U8 NegotiatedLinkRate; /* 0x1F */
1992 U8 PhyIdentifier; /* 0x20 */
1993 U8 AttachedPhyIdentifier; /* 0x21 */
1994 U8 Reserved3; /* 0x22 */
1995 U8 DiscoveryInfo; /* 0x23 */
1996 U32 AttachedPhyInfo; /* 0x24 */
1997 U8 ZoneGroup; /* 0x28 */
1998 U8 SelfConfigStatus; /* 0x29 */
1999 U16 Reserved4; /* 0x2A */
2000 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2001 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2002
2003 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2004
2005 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2006
2007 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2008
2009 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2010
2011 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2012
2013 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2014
2015 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2016
2017 /* values for SAS Expander Page 1 DiscoveryInfo field */
2018 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2019 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2020 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2021
2022
2023 /****************************************************************************
2024 * SAS Device Config Pages
2025 ****************************************************************************/
2026
2027 /* SAS Device Page 0 */
2028
2029 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2030 {
2031 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2032 U16 Slot; /* 0x08 */
2033 U16 EnclosureHandle; /* 0x0A */
2034 U64 SASAddress; /* 0x0C */
2035 U16 ParentDevHandle; /* 0x14 */
2036 U8 PhyNum; /* 0x16 */
2037 U8 AccessStatus; /* 0x17 */
2038 U16 DevHandle; /* 0x18 */
2039 U8 AttachedPhyIdentifier; /* 0x1A */
2040 U8 ZoneGroup; /* 0x1B */
2041 U32 DeviceInfo; /* 0x1C */
2042 U16 Flags; /* 0x20 */
2043 U8 PhysicalPort; /* 0x22 */
2044 U8 MaxPortConnections; /* 0x23 */
2045 U64 DeviceName; /* 0x24 */
2046 U8 PortGroups; /* 0x2C */
2047 U8 DmaGroup; /* 0x2D */
2048 U8 ControlGroup; /* 0x2E */
2049 U8 Reserved1; /* 0x2F */
2050 U32 Reserved2; /* 0x30 */
2051 U32 Reserved3; /* 0x34 */
2052 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2053 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2054
2055 #define MPI2_SASDEVICE0_PAGEVERSION (0x08)
2056
2057 /* values for SAS Device Page 0 AccessStatus field */
2058 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2059 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2060 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2061 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2062 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2063 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2064 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2065 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2066 /* specific values for SATA Init failures */
2067 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2068 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2069 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2070 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2071 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2072 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2073 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2074 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2075 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2076 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2077 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2078
2079 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2080
2081 /* values for SAS Device Page 0 Flags field */
2082 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2083 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2084 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2085 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2086 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2087 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2088 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2089 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2090 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2091 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2092 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2093
2094
2095 /* SAS Device Page 1 */
2096
2097 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2098 {
2099 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2100 U32 Reserved1; /* 0x08 */
2101 U64 SASAddress; /* 0x0C */
2102 U32 Reserved2; /* 0x14 */
2103 U16 DevHandle; /* 0x18 */
2104 U16 Reserved3; /* 0x1A */
2105 U8 InitialRegDeviceFIS[20];/* 0x1C */
2106 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2107 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2108
2109 #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2110
2111
2112 /****************************************************************************
2113 * SAS PHY Config Pages
2114 ****************************************************************************/
2115
2116 /* SAS PHY Page 0 */
2117
2118 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2119 {
2120 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2121 U16 OwnerDevHandle; /* 0x08 */
2122 U16 Reserved1; /* 0x0A */
2123 U16 AttachedDevHandle; /* 0x0C */
2124 U8 AttachedPhyIdentifier; /* 0x0E */
2125 U8 Reserved2; /* 0x0F */
2126 U32 AttachedPhyInfo; /* 0x10 */
2127 U8 ProgrammedLinkRate; /* 0x14 */
2128 U8 HwLinkRate; /* 0x15 */
2129 U8 ChangeCount; /* 0x16 */
2130 U8 Flags; /* 0x17 */
2131 U32 PhyInfo; /* 0x18 */
2132 U8 NegotiatedLinkRate; /* 0x1C */
2133 U8 Reserved3; /* 0x1D */
2134 U16 Reserved4; /* 0x1E */
2135 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2136 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2137
2138 #define MPI2_SASPHY0_PAGEVERSION (0x03)
2139
2140 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2141
2142 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2143
2144 /* values for SAS PHY Page 0 Flags field */
2145 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2146
2147 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2148
2149 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2150
2151 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2152
2153
2154 /* SAS PHY Page 1 */
2155
2156 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2157 {
2158 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2159 U32 Reserved1; /* 0x08 */
2160 U32 InvalidDwordCount; /* 0x0C */
2161 U32 RunningDisparityErrorCount; /* 0x10 */
2162 U32 LossDwordSynchCount; /* 0x14 */
2163 U32 PhyResetProblemCount; /* 0x18 */
2164 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2165 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2166
2167 #define MPI2_SASPHY1_PAGEVERSION (0x01)
2168
2169
2170 /* SAS PHY Page 2 */
2171
2172 typedef struct _MPI2_SASPHY2_PHY_EVENT {
2173 U8 PhyEventCode; /* 0x00 */
2174 U8 Reserved1; /* 0x01 */
2175 U16 Reserved2; /* 0x02 */
2176 U32 PhyEventInfo; /* 0x04 */
2177 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2178 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2179
2180 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2181
2182
2183 /*
2184 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2185 * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2186 */
2187 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2188 #define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2189 #endif
2190
2191 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2192 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2193 U32 Reserved1; /* 0x08 */
2194 U8 NumPhyEvents; /* 0x0C */
2195 U8 Reserved2; /* 0x0D */
2196 U16 Reserved3; /* 0x0E */
2197 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX];
2198 /* 0x10 */
2199 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2200 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2201
2202 #define MPI2_SASPHY2_PAGEVERSION (0x00)
2203
2204
2205 /* SAS PHY Page 3 */
2206
2207 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2208 U8 PhyEventCode; /* 0x00 */
2209 U8 Reserved1; /* 0x01 */
2210 U16 Reserved2; /* 0x02 */
2211 U8 CounterType; /* 0x04 */
2212 U8 ThresholdWindow; /* 0x05 */
2213 U8 TimeUnits; /* 0x06 */
2214 U8 Reserved3; /* 0x07 */
2215 U32 EventThreshold; /* 0x08 */
2216 U16 ThresholdFlags; /* 0x0C */
2217 U16 Reserved4; /* 0x0E */
2218 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2219 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2220
2221 /* values for PhyEventCode field */
2222 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2223 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2224 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2225 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2226 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2227 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2228 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2229 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2230 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2231 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2232 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2233 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2234 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2235 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2236 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2237 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2238 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2239 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2240 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2241 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2242 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2243 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2244 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2245 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2246 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2247 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2248 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2249 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2250 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2251 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2252 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2253 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2254 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2255 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2256 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2257 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2258 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2259
2260 /* values for the CounterType field */
2261 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2262 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2263 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2264
2265 /* values for the TimeUnits field */
2266 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2267 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2268 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2269 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2270
2271 /* values for the ThresholdFlags field */
2272 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2273 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2274
2275 /*
2276 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2277 * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2278 */
2279 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2280 #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2281 #endif
2282
2283 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2284 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2285 U32 Reserved1; /* 0x08 */
2286 U8 NumPhyEvents; /* 0x0C */
2287 U8 Reserved2; /* 0x0D */
2288 U16 Reserved3; /* 0x0E */
2289 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig
2290 [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2291 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2292 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2293
2294 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2295
2296
2297 /* SAS PHY Page 4 */
2298
2299 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
2300 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2301 U16 Reserved1; /* 0x08 */
2302 U8 Reserved2; /* 0x0A */
2303 U8 Flags; /* 0x0B */
2304 U8 InitialFrame[28]; /* 0x0C */
2305 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2306 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2307
2308 #define MPI2_SASPHY4_PAGEVERSION (0x00)
2309
2310 /* values for the Flags field */
2311 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2312 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2313
2314
2315
2316
2317 /****************************************************************************
2318 * SAS Port Config Pages
2319 ****************************************************************************/
2320
2321 /* SAS Port Page 0 */
2322
2323 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2324 {
2325 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2326 U8 PortNumber; /* 0x08 */
2327 U8 PhysicalPort; /* 0x09 */
2328 U8 PortWidth; /* 0x0A */
2329 U8 PhysicalPortWidth; /* 0x0B */
2330 U8 ZoneGroup; /* 0x0C */
2331 U8 Reserved1; /* 0x0D */
2332 U16 Reserved2; /* 0x0E */
2333 U64 SASAddress; /* 0x10 */
2334 U32 DeviceInfo; /* 0x18 */
2335 U32 Reserved3; /* 0x1C */
2336 U32 Reserved4; /* 0x20 */
2337 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2338 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2339
2340 #define MPI2_SASPORT0_PAGEVERSION (0x00)
2341
2342 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2343
2344
2345 /****************************************************************************
2346 * SAS Enclosure Config Pages
2347 ****************************************************************************/
2348
2349 /* SAS Enclosure Page 0 */
2350
2351 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2352 {
2353 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2354 U32 Reserved1; /* 0x08 */
2355 U64 EnclosureLogicalID; /* 0x0C */
2356 U16 Flags; /* 0x14 */
2357 U16 EnclosureHandle; /* 0x16 */
2358 U16 NumSlots; /* 0x18 */
2359 U16 StartSlot; /* 0x1A */
2360 U16 Reserved2; /* 0x1C */
2361 U16 SEPDevHandle; /* 0x1E */
2362 U32 Reserved3; /* 0x20 */
2363 U32 Reserved4; /* 0x24 */
2364 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2365 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2366 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2367
2368 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
2369
2370 /* values for SAS Enclosure Page 0 Flags field */
2371 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2372 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2373 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2374 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2375 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2376 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2377 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2378
2379
2380 /****************************************************************************
2381 * Log Config Page
2382 ****************************************************************************/
2383
2384 /* Log Page 0 */
2385
2386 /*
2387 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2388 * one and check Header.ExtPageLength or NumPhys at runtime.
2389 */
2390 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2391 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2392 #endif
2393
2394 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2395
2396 typedef struct _MPI2_LOG_0_ENTRY
2397 {
2398 U64 TimeStamp; /* 0x00 */
2399 U32 Reserved1; /* 0x08 */
2400 U16 LogSequence; /* 0x0C */
2401 U16 LogEntryQualifier; /* 0x0E */
2402 U8 VP_ID; /* 0x10 */
2403 U8 VF_ID; /* 0x11 */
2404 U16 Reserved2; /* 0x12 */
2405 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2406 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2407 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2408
2409 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2410 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2411 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2412 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2413 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2414 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2415
2416 typedef struct _MPI2_CONFIG_PAGE_LOG_0
2417 {
2418 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2419 U32 Reserved1; /* 0x08 */
2420 U32 Reserved2; /* 0x0C */
2421 U16 NumLogEntries; /* 0x10 */
2422 U16 Reserved3; /* 0x12 */
2423 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2424 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2425 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2426
2427 #define MPI2_LOG_0_PAGEVERSION (0x02)
2428
2429
2430 /****************************************************************************
2431 * RAID Config Page
2432 ****************************************************************************/
2433
2434 /* RAID Page 0 */
2435
2436 /*
2437 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2438 * one and check Header.ExtPageLength or NumPhys at runtime.
2439 */
2440 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2441 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2442 #endif
2443
2444 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2445 {
2446 U16 ElementFlags; /* 0x00 */
2447 U16 VolDevHandle; /* 0x02 */
2448 U8 HotSparePool; /* 0x04 */
2449 U8 PhysDiskNum; /* 0x05 */
2450 U16 PhysDiskDevHandle; /* 0x06 */
2451 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2452 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2453 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2454
2455 /* values for the ElementFlags field */
2456 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2457 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2458 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2459 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2460 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2461
2462
2463 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2464 {
2465 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2466 U8 NumHotSpares; /* 0x08 */
2467 U8 NumPhysDisks; /* 0x09 */
2468 U8 NumVolumes; /* 0x0A */
2469 U8 ConfigNum; /* 0x0B */
2470 U32 Flags; /* 0x0C */
2471 U8 ConfigGUID[24]; /* 0x10 */
2472 U32 Reserved1; /* 0x28 */
2473 U8 NumElements; /* 0x2C */
2474 U8 Reserved2; /* 0x2D */
2475 U16 Reserved3; /* 0x2E */
2476 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2477 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2478 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2479 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2480
2481 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2482
2483 /* values for RAID Configuration Page 0 Flags field */
2484 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2485
2486
2487 /****************************************************************************
2488 * Driver Persistent Mapping Config Pages
2489 ****************************************************************************/
2490
2491 /* Driver Persistent Mapping Page 0 */
2492
2493 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2494 {
2495 U64 PhysicalIdentifier; /* 0x00 */
2496 U16 MappingInformation; /* 0x08 */
2497 U16 DeviceIndex; /* 0x0A */
2498 U32 PhysicalBitsMapping; /* 0x0C */
2499 U32 Reserved1; /* 0x10 */
2500 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2501 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2502 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2503
2504 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2505 {
2506 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2507 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2508 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2509 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2510 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2511
2512 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2513
2514 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
2515 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2516 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2517 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2518
2519
2520 /****************************************************************************
2521 * Ethernet Config Pages
2522 ****************************************************************************/
2523
2524 /* Ethernet Page 0 */
2525
2526 /* IP address (union of IPv4 and IPv6) */
2527 typedef union _MPI2_ETHERNET_IP_ADDR {
2528 U32 IPv4Addr;
2529 U32 IPv6Addr[4];
2530 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2531 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2532
2533 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
2534
2535 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
2536 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2537 U8 NumInterfaces; /* 0x08 */
2538 U8 Reserved0; /* 0x09 */
2539 U16 Reserved1; /* 0x0A */
2540 U32 Status; /* 0x0C */
2541 U8 MediaState; /* 0x10 */
2542 U8 Reserved2; /* 0x11 */
2543 U16 Reserved3; /* 0x12 */
2544 U8 MacAddress[6]; /* 0x14 */
2545 U8 Reserved4; /* 0x1A */
2546 U8 Reserved5; /* 0x1B */
2547 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
2548 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
2549 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
2550 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
2551 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
2552 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
2553 U8 HostName
2554 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2555 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2556 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2557
2558 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
2559
2560 /* values for Ethernet Page 0 Status field */
2561 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
2562 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
2563 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
2564 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
2565 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
2566 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
2567 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
2568 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
2569 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
2570 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
2571 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
2572 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
2573
2574 /* values for Ethernet Page 0 MediaState field */
2575 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
2576 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
2577 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
2578
2579 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
2580 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
2581 #define MPI2_ETHPG0_MS_10MBIT (0x01)
2582 #define MPI2_ETHPG0_MS_100MBIT (0x02)
2583 #define MPI2_ETHPG0_MS_1GBIT (0x03)
2584
2585
2586 /* Ethernet Page 1 */
2587
2588 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
2589 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2590 U32 Reserved0; /* 0x08 */
2591 U32 Flags; /* 0x0C */
2592 U8 MediaState; /* 0x10 */
2593 U8 Reserved1; /* 0x11 */
2594 U16 Reserved2; /* 0x12 */
2595 U8 MacAddress[6]; /* 0x14 */
2596 U8 Reserved3; /* 0x1A */
2597 U8 Reserved4; /* 0x1B */
2598 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
2599 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
2600 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
2601 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
2602 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
2603 U32 Reserved5; /* 0x6C */
2604 U32 Reserved6; /* 0x70 */
2605 U32 Reserved7; /* 0x74 */
2606 U32 Reserved8; /* 0x78 */
2607 U8 HostName
2608 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2609 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
2610 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
2611
2612 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
2613
2614 /* values for Ethernet Page 1 Flags field */
2615 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
2616 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
2617 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
2618 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
2619 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
2620 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
2621 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
2622 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
2623 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
2624
2625 /* values for Ethernet Page 1 MediaState field */
2626 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
2627 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
2628 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
2629
2630 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
2631 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
2632 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
2633 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
2634 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
2635
2636
2637 #endif
2638
Linux with added FPC-III support