drivers/infiniband/hw/cxgb4/iw_cxgb4.h

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *      - Redistributions in binary form must reproduce the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer in the documentation and/or other materials
  20  *        provided with the distribution.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  23  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  25  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  26  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  27  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  28  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  29  * SOFTWARE.
  30  */
  31 #ifndef __IW_CXGB4_H__
  32 #define __IW_CXGB4_H__
  33
  34 #include <linux/mutex.h>
  35 #include <linux/list.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/idr.h>
  38 #include <linux/completion.h>
  39 #include <linux/netdevice.h>
  40 #include <linux/sched.h>
  41 #include <linux/pci.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/inet.h>
  44 #include <linux/wait.h>
  45 #include <linux/kref.h>
  46 #include <linux/timer.h>
  47 #include <linux/io.h>
  48 #include <linux/workqueue.h>
  49
  50 #include <asm/byteorder.h>
  51
  52 #include <net/net_namespace.h>
  53
  54 #include <rdma/ib_verbs.h>
  55 #include <rdma/iw_cm.h>
  56 #include <rdma/rdma_netlink.h>
  57 #include <rdma/iw_portmap.h>
  58
  59 #include "cxgb4.h"
  60 #include "cxgb4_uld.h"
  61 #include "l2t.h"
  62 #include <rdma/cxgb4-abi.h>
  63
  64 #define DRV_NAME "iw_cxgb4"
  65 #define MOD DRV_NAME ":"
  66
  67 extern int c4iw_debug;
  68 #define PDBG(fmt, args...) \
  69 do { \
  70         if (c4iw_debug) \
  71                 printk(MOD fmt, ## args); \
  72 } while (0)
  73
  74 #include "t4.h"
  75
  76 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
  77 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
  78
  79 static inline void *cplhdr(struct sk_buff *skb)
  80 {
  81         return skb->data;
  82 }
  83
  84 #define C4IW_ID_TABLE_F_RANDOM 1       /* Pseudo-randomize the id's returned */
  85 #define C4IW_ID_TABLE_F_EMPTY  2       /* Table is initially empty */
  86
  87 struct c4iw_id_table {
  88         u32 flags;
  89         u32 start;              /* logical minimal id */
  90         u32 last;               /* hint for find */
  91         u32 max;
  92         spinlock_t lock;
  93         unsigned long *table;
  94 };
  95
  96 struct c4iw_resource {
  97         struct c4iw_id_table tpt_table;
  98         struct c4iw_id_table qid_table;
  99         struct c4iw_id_table pdid_table;
 100 };
 101
 102 struct c4iw_qid_list {
 103         struct list_head entry;
 104         u32 qid;
 105 };
 106
 107 struct c4iw_dev_ucontext {
 108         struct list_head qpids;
 109         struct list_head cqids;
 110         struct mutex lock;
 111         struct kref kref;
 112 };
 113
 114 enum c4iw_rdev_flags {
 115         T4_FATAL_ERROR = (1<<0),
 116         T4_STATUS_PAGE_DISABLED = (1<<1),
 117 };
 118
 119 struct c4iw_stat {
 120         u64 total;
 121         u64 cur;
 122         u64 max;
 123         u64 fail;
 124 };
 125
 126 struct c4iw_stats {
 127         struct mutex lock;
 128         struct c4iw_stat qid;
 129         struct c4iw_stat pd;
 130         struct c4iw_stat stag;
 131         struct c4iw_stat pbl;
 132         struct c4iw_stat rqt;
 133         struct c4iw_stat ocqp;
 134         u64  db_full;
 135         u64  db_empty;
 136         u64  db_drop;
 137         u64  db_state_transitions;
 138         u64  db_fc_interruptions;
 139         u64  tcam_full;
 140         u64  act_ofld_conn_fails;
 141         u64  pas_ofld_conn_fails;
 142         u64  neg_adv;
 143 };
 144
 145 struct c4iw_hw_queue {
 146         int t4_eq_status_entries;
 147         int t4_max_eq_size;
 148         int t4_max_iq_size;
 149         int t4_max_rq_size;
 150         int t4_max_sq_size;
 151         int t4_max_qp_depth;
 152         int t4_max_cq_depth;
 153         int t4_stat_len;
 154 };
 155
 156 struct wr_log_entry {
 157         struct timespec post_host_ts;
 158         struct timespec poll_host_ts;
 159         u64 post_sge_ts;
 160         u64 cqe_sge_ts;
 161         u64 poll_sge_ts;
 162         u16 qid;
 163         u16 wr_id;
 164         u8 opcode;
 165         u8 valid;
 166 };
 167
 168 struct c4iw_rdev {
 169         struct c4iw_resource resource;
 170         u32 qpmask;
 171         u32 cqmask;
 172         struct c4iw_dev_ucontext uctx;
 173         struct gen_pool *pbl_pool;
 174         struct gen_pool *rqt_pool;
 175         struct gen_pool *ocqp_pool;
 176         u32 flags;
 177         struct cxgb4_lld_info lldi;
 178         unsigned long bar2_pa;
 179         void __iomem *bar2_kva;
 180         unsigned long oc_mw_pa;
 181         void __iomem *oc_mw_kva;
 182         struct c4iw_stats stats;
 183         struct c4iw_hw_queue hw_queue;
 184         struct t4_dev_status_page *status_page;
 185         atomic_t wr_log_idx;
 186         struct wr_log_entry *wr_log;
 187         int wr_log_size;
 188         struct workqueue_struct *free_workq;
 189         struct completion rqt_compl;
 190         struct completion pbl_compl;
 191         struct kref rqt_kref;
 192         struct kref pbl_kref;
 193 };
 194
 195 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
 196 {
 197         return rdev->flags & T4_FATAL_ERROR;
 198 }
 199
 200 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
 201 {
 202         return (int)(rdev->lldi.vr->stag.size >> 5);
 203 }
 204
 205 #define C4IW_WR_TO (60*HZ)
 206
 207 struct c4iw_wr_wait {
 208         struct completion completion;
 209         int ret;
 210 };
 211
 212 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
 213 {
 214         wr_waitp->ret = 0;
 215         init_completion(&wr_waitp->completion);
 216 }
 217
 218 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
 219 {
 220         wr_waitp->ret = ret;
 221         complete(&wr_waitp->completion);
 222 }
 223
 224 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
 225                                  struct c4iw_wr_wait *wr_waitp,
 226                                  u32 hwtid, u32 qpid,
 227                                  const char *func)
 228 {
 229         int ret;
 230
 231         if (c4iw_fatal_error(rdev)) {
 232                 wr_waitp->ret = -EIO;
 233                 goto out;
 234         }
 235
 236         ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO);
 237         if (!ret) {
 238                 PDBG("%s - Device %s not responding (disabling device) - tid %u qpid %u\n",
 239                      func, pci_name(rdev->lldi.pdev), hwtid, qpid);
 240                 rdev->flags |= T4_FATAL_ERROR;
 241                 wr_waitp->ret = -EIO;
 242         }
 243 out:
 244         if (wr_waitp->ret)
 245                 PDBG("%s: FW reply %d tid %u qpid %u\n",
 246                      pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
 247         return wr_waitp->ret;
 248 }
 249
 250 enum db_state {
 251         NORMAL = 0,
 252         FLOW_CONTROL = 1,
 253         RECOVERY = 2,
 254         STOPPED = 3
 255 };
 256
 257 struct c4iw_dev {
 258         struct ib_device ibdev;
 259         struct c4iw_rdev rdev;
 260         u32 device_cap_flags;
 261         struct idr cqidr;
 262         struct idr qpidr;
 263         struct idr mmidr;
 264         spinlock_t lock;
 265         struct mutex db_mutex;
 266         struct dentry *debugfs_root;
 267         enum db_state db_state;
 268         struct idr hwtid_idr;
 269         struct idr atid_idr;
 270         struct idr stid_idr;
 271         struct list_head db_fc_list;
 272         u32 avail_ird;
 273         wait_queue_head_t wait;
 274 };
 275
 276 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
 277 {
 278         return container_of(ibdev, struct c4iw_dev, ibdev);
 279 }
 280
 281 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
 282 {
 283         return container_of(rdev, struct c4iw_dev, rdev);
 284 }
 285
 286 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
 287 {
 288         return idr_find(&rhp->cqidr, cqid);
 289 }
 290
 291 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
 292 {
 293         return idr_find(&rhp->qpidr, qpid);
 294 }
 295
 296 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
 297 {
 298         return idr_find(&rhp->mmidr, mmid);
 299 }
 300
 301 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
 302                                  void *handle, u32 id, int lock)
 303 {
 304         int ret;
 305
 306         if (lock) {
 307                 idr_preload(GFP_KERNEL);
 308                 spin_lock_irq(&rhp->lock);
 309         }
 310
 311         ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC);
 312
 313         if (lock) {
 314                 spin_unlock_irq(&rhp->lock);
 315                 idr_preload_end();
 316         }
 317
 318         BUG_ON(ret == -ENOSPC);
 319         return ret < 0 ? ret : 0;
 320 }
 321
 322 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
 323                                 void *handle, u32 id)
 324 {
 325         return _insert_handle(rhp, idr, handle, id, 1);
 326 }
 327
 328 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
 329                                        void *handle, u32 id)
 330 {
 331         return _insert_handle(rhp, idr, handle, id, 0);
 332 }
 333
 334 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
 335                                    u32 id, int lock)
 336 {
 337         if (lock)
 338                 spin_lock_irq(&rhp->lock);
 339         idr_remove(idr, id);
 340         if (lock)
 341                 spin_unlock_irq(&rhp->lock);
 342 }
 343
 344 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
 345 {
 346         _remove_handle(rhp, idr, id, 1);
 347 }
 348
 349 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
 350                                          struct idr *idr, u32 id)
 351 {
 352         _remove_handle(rhp, idr, id, 0);
 353 }
 354
 355 extern uint c4iw_max_read_depth;
 356
 357 static inline int cur_max_read_depth(struct c4iw_dev *dev)
 358 {
 359         return min(dev->rdev.lldi.max_ordird_qp, c4iw_max_read_depth);
 360 }
 361
 362 struct c4iw_pd {
 363         struct ib_pd ibpd;
 364         u32 pdid;
 365         struct c4iw_dev *rhp;
 366 };
 367
 368 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
 369 {
 370         return container_of(ibpd, struct c4iw_pd, ibpd);
 371 }
 372
 373 struct tpt_attributes {
 374         u64 len;
 375         u64 va_fbo;
 376         enum fw_ri_mem_perms perms;
 377         u32 stag;
 378         u32 pdid;
 379         u32 qpid;
 380         u32 pbl_addr;
 381         u32 pbl_size;
 382         u32 state:1;
 383         u32 type:2;
 384         u32 rsvd:1;
 385         u32 remote_invaliate_disable:1;
 386         u32 zbva:1;
 387         u32 mw_bind_enable:1;
 388         u32 page_size:5;
 389 };
 390
 391 struct c4iw_mr {
 392         struct ib_mr ibmr;
 393         struct ib_umem *umem;
 394         struct c4iw_dev *rhp;
 395         struct sk_buff *dereg_skb;
 396         u64 kva;
 397         struct tpt_attributes attr;
 398         u64 *mpl;
 399         dma_addr_t mpl_addr;
 400         u32 max_mpl_len;
 401         u32 mpl_len;
 402 };
 403
 404 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
 405 {
 406         return container_of(ibmr, struct c4iw_mr, ibmr);
 407 }
 408
 409 struct c4iw_mw {
 410         struct ib_mw ibmw;
 411         struct c4iw_dev *rhp;
 412         struct sk_buff *dereg_skb;
 413         u64 kva;
 414         struct tpt_attributes attr;
 415 };
 416
 417 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
 418 {
 419         return container_of(ibmw, struct c4iw_mw, ibmw);
 420 }
 421
 422 struct c4iw_cq {
 423         struct ib_cq ibcq;
 424         struct c4iw_dev *rhp;
 425         struct sk_buff *destroy_skb;
 426         struct t4_cq cq;
 427         spinlock_t lock;
 428         spinlock_t comp_handler_lock;
 429         atomic_t refcnt;
 430         wait_queue_head_t wait;
 431 };
 432
 433 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
 434 {
 435         return container_of(ibcq, struct c4iw_cq, ibcq);
 436 }
 437
 438 struct c4iw_mpa_attributes {
 439         u8 initiator;
 440         u8 recv_marker_enabled;
 441         u8 xmit_marker_enabled;
 442         u8 crc_enabled;
 443         u8 enhanced_rdma_conn;
 444         u8 version;
 445         u8 p2p_type;
 446 };
 447
 448 struct c4iw_qp_attributes {
 449         u32 scq;
 450         u32 rcq;
 451         u32 sq_num_entries;
 452         u32 rq_num_entries;
 453         u32 sq_max_sges;
 454         u32 sq_max_sges_rdma_write;
 455         u32 rq_max_sges;
 456         u32 state;
 457         u8 enable_rdma_read;
 458         u8 enable_rdma_write;
 459         u8 enable_bind;
 460         u8 enable_mmid0_fastreg;
 461         u32 max_ord;
 462         u32 max_ird;
 463         u32 pd;
 464         u32 next_state;
 465         char terminate_buffer[52];
 466         u32 terminate_msg_len;
 467         u8 is_terminate_local;
 468         struct c4iw_mpa_attributes mpa_attr;
 469         struct c4iw_ep *llp_stream_handle;
 470         u8 layer_etype;
 471         u8 ecode;
 472         u16 sq_db_inc;
 473         u16 rq_db_inc;
 474         u8 send_term;
 475 };
 476
 477 struct c4iw_qp {
 478         struct ib_qp ibqp;
 479         struct list_head db_fc_entry;
 480         struct c4iw_dev *rhp;
 481         struct c4iw_ep *ep;
 482         struct c4iw_qp_attributes attr;
 483         struct t4_wq wq;
 484         spinlock_t lock;
 485         struct mutex mutex;
 486         struct kref kref;
 487         wait_queue_head_t wait;
 488         struct timer_list timer;
 489         int sq_sig_all;
 490         struct completion rq_drained;
 491         struct completion sq_drained;
 492         struct work_struct free_work;
 493         struct c4iw_ucontext *ucontext;
 494 };
 495
 496 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
 497 {
 498         return container_of(ibqp, struct c4iw_qp, ibqp);
 499 }
 500
 501 struct c4iw_ucontext {
 502         struct ib_ucontext ibucontext;
 503         struct c4iw_dev_ucontext uctx;
 504         u32 key;
 505         spinlock_t mmap_lock;
 506         struct list_head mmaps;
 507         struct kref kref;
 508 };
 509
 510 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
 511 {
 512         return container_of(c, struct c4iw_ucontext, ibucontext);
 513 }
 514
 515 void _c4iw_free_ucontext(struct kref *kref);
 516
 517 static inline void c4iw_put_ucontext(struct c4iw_ucontext *ucontext)
 518 {
 519         kref_put(&ucontext->kref, _c4iw_free_ucontext);
 520 }
 521
 522 static inline void c4iw_get_ucontext(struct c4iw_ucontext *ucontext)
 523 {
 524         kref_get(&ucontext->kref);
 525 }
 526
 527 struct c4iw_mm_entry {
 528         struct list_head entry;
 529         u64 addr;
 530         u32 key;
 531         unsigned len;
 532 };
 533
 534 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
 535                                                 u32 key, unsigned len)
 536 {
 537         struct list_head *pos, *nxt;
 538         struct c4iw_mm_entry *mm;
 539
 540         spin_lock(&ucontext->mmap_lock);
 541         list_for_each_safe(pos, nxt, &ucontext->mmaps) {
 542
 543                 mm = list_entry(pos, struct c4iw_mm_entry, entry);
 544                 if (mm->key == key && mm->len == len) {
 545                         list_del_init(&mm->entry);
 546                         spin_unlock(&ucontext->mmap_lock);
 547                         PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
 548                              key, (unsigned long long) mm->addr, mm->len);
 549                         return mm;
 550                 }
 551         }
 552         spin_unlock(&ucontext->mmap_lock);
 553         return NULL;
 554 }
 555
 556 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
 557                                struct c4iw_mm_entry *mm)
 558 {
 559         spin_lock(&ucontext->mmap_lock);
 560         PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
 561              mm->key, (unsigned long long) mm->addr, mm->len);
 562         list_add_tail(&mm->entry, &ucontext->mmaps);
 563         spin_unlock(&ucontext->mmap_lock);
 564 }
 565
 566 enum c4iw_qp_attr_mask {
 567         C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
 568         C4IW_QP_ATTR_SQ_DB = 1<<1,
 569         C4IW_QP_ATTR_RQ_DB = 1<<2,
 570         C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
 571         C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
 572         C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
 573         C4IW_QP_ATTR_MAX_ORD = 1 << 11,
 574         C4IW_QP_ATTR_MAX_IRD = 1 << 12,
 575         C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
 576         C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
 577         C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
 578         C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
 579         C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
 580                                      C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
 581                                      C4IW_QP_ATTR_MAX_ORD |
 582                                      C4IW_QP_ATTR_MAX_IRD |
 583                                      C4IW_QP_ATTR_LLP_STREAM_HANDLE |
 584                                      C4IW_QP_ATTR_STREAM_MSG_BUFFER |
 585                                      C4IW_QP_ATTR_MPA_ATTR |
 586                                      C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
 587 };
 588
 589 int c4iw_modify_qp(struct c4iw_dev *rhp,
 590                                 struct c4iw_qp *qhp,
 591                                 enum c4iw_qp_attr_mask mask,
 592                                 struct c4iw_qp_attributes *attrs,
 593                                 int internal);
 594
 595 enum c4iw_qp_state {
 596         C4IW_QP_STATE_IDLE,
 597         C4IW_QP_STATE_RTS,
 598         C4IW_QP_STATE_ERROR,
 599         C4IW_QP_STATE_TERMINATE,
 600         C4IW_QP_STATE_CLOSING,
 601         C4IW_QP_STATE_TOT
 602 };
 603
 604 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
 605 {
 606         switch (ib_state) {
 607         case IB_QPS_RESET:
 608         case IB_QPS_INIT:
 609                 return C4IW_QP_STATE_IDLE;
 610         case IB_QPS_RTS:
 611                 return C4IW_QP_STATE_RTS;
 612         case IB_QPS_SQD:
 613                 return C4IW_QP_STATE_CLOSING;
 614         case IB_QPS_SQE:
 615                 return C4IW_QP_STATE_TERMINATE;
 616         case IB_QPS_ERR:
 617                 return C4IW_QP_STATE_ERROR;
 618         default:
 619                 return -1;
 620         }
 621 }
 622
 623 static inline int to_ib_qp_state(int c4iw_qp_state)
 624 {
 625         switch (c4iw_qp_state) {
 626         case C4IW_QP_STATE_IDLE:
 627                 return IB_QPS_INIT;
 628         case C4IW_QP_STATE_RTS:
 629                 return IB_QPS_RTS;
 630         case C4IW_QP_STATE_CLOSING:
 631                 return IB_QPS_SQD;
 632         case C4IW_QP_STATE_TERMINATE:
 633                 return IB_QPS_SQE;
 634         case C4IW_QP_STATE_ERROR:
 635                 return IB_QPS_ERR;
 636         }
 637         return IB_QPS_ERR;
 638 }
 639
 640 static inline u32 c4iw_ib_to_tpt_access(int a)
 641 {
 642         return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
 643                (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
 644                (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
 645                FW_RI_MEM_ACCESS_LOCAL_READ;
 646 }
 647
 648 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
 649 {
 650         return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
 651                (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
 652 }
 653
 654 enum c4iw_mmid_state {
 655         C4IW_STAG_STATE_VALID,
 656         C4IW_STAG_STATE_INVALID
 657 };
 658
 659 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
 660
 661 #define MPA_KEY_REQ "MPA ID Req Frame"
 662 #define MPA_KEY_REP "MPA ID Rep Frame"
 663
 664 #define MPA_MAX_PRIVATE_DATA    256
 665 #define MPA_ENHANCED_RDMA_CONN  0x10
 666 #define MPA_REJECT              0x20
 667 #define MPA_CRC                 0x40
 668 #define MPA_MARKERS             0x80
 669 #define MPA_FLAGS_MASK          0xE0
 670
 671 #define MPA_V2_PEER2PEER_MODEL          0x8000
 672 #define MPA_V2_ZERO_LEN_FPDU_RTR        0x4000
 673 #define MPA_V2_RDMA_WRITE_RTR           0x8000
 674 #define MPA_V2_RDMA_READ_RTR            0x4000
 675 #define MPA_V2_IRD_ORD_MASK             0x3FFF
 676
 677 #define c4iw_put_ep(ep) { \
 678         PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__,  \
 679              ep, atomic_read(&((ep)->kref.refcount))); \
 680         WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
 681         kref_put(&((ep)->kref), _c4iw_free_ep); \
 682 }
 683
 684 #define c4iw_get_ep(ep) { \
 685         PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
 686              ep, atomic_read(&((ep)->kref.refcount))); \
 687         kref_get(&((ep)->kref));  \
 688 }
 689 void _c4iw_free_ep(struct kref *kref);
 690
 691 struct mpa_message {
 692         u8 key[16];
 693         u8 flags;
 694         u8 revision;
 695         __be16 private_data_size;
 696         u8 private_data[0];
 697 };
 698
 699 struct mpa_v2_conn_params {
 700         __be16 ird;
 701         __be16 ord;
 702 };
 703
 704 struct terminate_message {
 705         u8 layer_etype;
 706         u8 ecode;
 707         __be16 hdrct_rsvd;
 708         u8 len_hdrs[0];
 709 };
 710
 711 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
 712
 713 enum c4iw_layers_types {
 714         LAYER_RDMAP             = 0x00,
 715         LAYER_DDP               = 0x10,
 716         LAYER_MPA               = 0x20,
 717         RDMAP_LOCAL_CATA        = 0x00,
 718         RDMAP_REMOTE_PROT       = 0x01,
 719         RDMAP_REMOTE_OP         = 0x02,
 720         DDP_LOCAL_CATA          = 0x00,
 721         DDP_TAGGED_ERR          = 0x01,
 722         DDP_UNTAGGED_ERR        = 0x02,
 723         DDP_LLP                 = 0x03
 724 };
 725
 726 enum c4iw_rdma_ecodes {
 727         RDMAP_INV_STAG          = 0x00,
 728         RDMAP_BASE_BOUNDS       = 0x01,
 729         RDMAP_ACC_VIOL          = 0x02,
 730         RDMAP_STAG_NOT_ASSOC    = 0x03,
 731         RDMAP_TO_WRAP           = 0x04,
 732         RDMAP_INV_VERS          = 0x05,
 733         RDMAP_INV_OPCODE        = 0x06,
 734         RDMAP_STREAM_CATA       = 0x07,
 735         RDMAP_GLOBAL_CATA       = 0x08,
 736         RDMAP_CANT_INV_STAG     = 0x09,
 737         RDMAP_UNSPECIFIED       = 0xff
 738 };
 739
 740 enum c4iw_ddp_ecodes {
 741         DDPT_INV_STAG           = 0x00,
 742         DDPT_BASE_BOUNDS        = 0x01,
 743         DDPT_STAG_NOT_ASSOC     = 0x02,
 744         DDPT_TO_WRAP            = 0x03,
 745         DDPT_INV_VERS           = 0x04,
 746         DDPU_INV_QN             = 0x01,
 747         DDPU_INV_MSN_NOBUF      = 0x02,
 748         DDPU_INV_MSN_RANGE      = 0x03,
 749         DDPU_INV_MO             = 0x04,
 750         DDPU_MSG_TOOBIG         = 0x05,
 751         DDPU_INV_VERS           = 0x06
 752 };
 753
 754 enum c4iw_mpa_ecodes {
 755         MPA_CRC_ERR             = 0x02,
 756         MPA_MARKER_ERR          = 0x03,
 757         MPA_LOCAL_CATA          = 0x05,
 758         MPA_INSUFF_IRD          = 0x06,
 759         MPA_NOMATCH_RTR         = 0x07,
 760 };
 761
 762 enum c4iw_ep_state {
 763         IDLE = 0,
 764         LISTEN,
 765         CONNECTING,
 766         MPA_REQ_WAIT,
 767         MPA_REQ_SENT,
 768         MPA_REQ_RCVD,
 769         MPA_REP_SENT,
 770         FPDU_MODE,
 771         ABORTING,
 772         CLOSING,
 773         MORIBUND,
 774         DEAD,
 775 };
 776
 777 enum c4iw_ep_flags {
 778         PEER_ABORT_IN_PROGRESS  = 0,
 779         ABORT_REQ_IN_PROGRESS   = 1,
 780         RELEASE_RESOURCES       = 2,
 781         CLOSE_SENT              = 3,
 782         TIMEOUT                 = 4,
 783         QP_REFERENCED           = 5,
 784         STOP_MPA_TIMER          = 7,
 785 };
 786
 787 enum c4iw_ep_history {
 788         ACT_OPEN_REQ            = 0,
 789         ACT_OFLD_CONN           = 1,
 790         ACT_OPEN_RPL            = 2,
 791         ACT_ESTAB               = 3,
 792         PASS_ACCEPT_REQ         = 4,
 793         PASS_ESTAB              = 5,
 794         ABORT_UPCALL            = 6,
 795         ESTAB_UPCALL            = 7,
 796         CLOSE_UPCALL            = 8,
 797         ULP_ACCEPT              = 9,
 798         ULP_REJECT              = 10,
 799         TIMEDOUT                = 11,
 800         PEER_ABORT              = 12,
 801         PEER_CLOSE              = 13,
 802         CONNREQ_UPCALL          = 14,
 803         ABORT_CONN              = 15,
 804         DISCONN_UPCALL          = 16,
 805         EP_DISC_CLOSE           = 17,
 806         EP_DISC_ABORT           = 18,
 807         CONN_RPL_UPCALL         = 19,
 808         ACT_RETRY_NOMEM         = 20,
 809         ACT_RETRY_INUSE         = 21,
 810         CLOSE_CON_RPL           = 22,
 811         EP_DISC_FAIL            = 24,
 812         QP_REFED                = 25,
 813         QP_DEREFED              = 26,
 814         CM_ID_REFED             = 27,
 815         CM_ID_DEREFED           = 28,
 816 };
 817
 818 enum conn_pre_alloc_buffers {
 819         CN_ABORT_REQ_BUF,
 820         CN_ABORT_RPL_BUF,
 821         CN_CLOSE_CON_REQ_BUF,
 822         CN_DESTROY_BUF,
 823         CN_FLOWC_BUF,
 824         CN_MAX_CON_BUF
 825 };
 826
 827 #define FLOWC_LEN 80
 828 union cpl_wr_size {
 829         struct cpl_abort_req abrt_req;
 830         struct cpl_abort_rpl abrt_rpl;
 831         struct fw_ri_wr ri_req;
 832         struct cpl_close_con_req close_req;
 833         char flowc_buf[FLOWC_LEN];
 834 };
 835
 836 struct c4iw_ep_common {
 837         struct iw_cm_id *cm_id;
 838         struct c4iw_qp *qp;
 839         struct c4iw_dev *dev;
 840         struct sk_buff_head ep_skb_list;
 841         enum c4iw_ep_state state;
 842         struct kref kref;
 843         struct mutex mutex;
 844         struct sockaddr_storage local_addr;
 845         struct sockaddr_storage remote_addr;
 846         struct c4iw_wr_wait wr_wait;
 847         unsigned long flags;
 848         unsigned long history;
 849 };
 850
 851 struct c4iw_listen_ep {
 852         struct c4iw_ep_common com;
 853         unsigned int stid;
 854         int backlog;
 855 };
 856
 857 struct c4iw_ep_stats {
 858         unsigned connect_neg_adv;
 859         unsigned abort_neg_adv;
 860 };
 861
 862 struct c4iw_ep {
 863         struct c4iw_ep_common com;
 864         struct c4iw_ep *parent_ep;
 865         struct timer_list timer;
 866         struct list_head entry;
 867         unsigned int atid;
 868         u32 hwtid;
 869         u32 snd_seq;
 870         u32 rcv_seq;
 871         struct l2t_entry *l2t;
 872         struct dst_entry *dst;
 873         struct sk_buff *mpa_skb;
 874         struct c4iw_mpa_attributes mpa_attr;
 875         u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
 876         unsigned int mpa_pkt_len;
 877         u32 ird;
 878         u32 ord;
 879         u32 smac_idx;
 880         u32 tx_chan;
 881         u32 mtu;
 882         u16 mss;
 883         u16 emss;
 884         u16 plen;
 885         u16 rss_qid;
 886         u16 txq_idx;
 887         u16 ctrlq_idx;
 888         u8 tos;
 889         u8 retry_with_mpa_v1;
 890         u8 tried_with_mpa_v1;
 891         unsigned int retry_count;
 892         int snd_win;
 893         int rcv_win;
 894         struct c4iw_ep_stats stats;
 895 };
 896
 897 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
 898 {
 899         return cm_id->provider_data;
 900 }
 901
 902 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
 903 {
 904         return cm_id->provider_data;
 905 }
 906
 907 static inline int ocqp_supported(const struct cxgb4_lld_info *infop)
 908 {
 909 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
 910         return infop->vr->ocq.size > 0;
 911 #else
 912         return 0;
 913 #endif
 914 }
 915
 916 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
 917 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
 918 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
 919                         u32 reserved, u32 flags);
 920 void c4iw_id_table_free(struct c4iw_id_table *alloc);
 921
 922 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
 923
 924 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
 925                      struct l2t_entry *l2t);
 926 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
 927                    struct c4iw_dev_ucontext *uctx);
 928 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
 929 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
 930 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
 931 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
 932 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
 933 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
 934 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
 935 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
 936 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
 937 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
 938 void c4iw_destroy_resource(struct c4iw_resource *rscp);
 939 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
 940 int c4iw_register_device(struct c4iw_dev *dev);
 941 void c4iw_unregister_device(struct c4iw_dev *dev);
 942 int __init c4iw_cm_init(void);
 943 void c4iw_cm_term(void);
 944 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
 945                                struct c4iw_dev_ucontext *uctx);
 946 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
 947                             struct c4iw_dev_ucontext *uctx);
 948 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 949 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 950                       struct ib_send_wr **bad_wr);
 951 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 952                       struct ib_recv_wr **bad_wr);
 953 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
 954 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
 955 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
 956 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
 957 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
 958 void c4iw_qp_add_ref(struct ib_qp *qp);
 959 void c4iw_qp_rem_ref(struct ib_qp *qp);
 960 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
 961                             enum ib_mr_type mr_type,
 962                             u32 max_num_sg);
 963 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
 964                    unsigned int *sg_offset);
 965 int c4iw_dealloc_mw(struct ib_mw *mw);
 966 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
 967                             struct ib_udata *udata);
 968 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
 969                                            u64 length, u64 virt, int acc,
 970                                            struct ib_udata *udata);
 971 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
 972 int c4iw_dereg_mr(struct ib_mr *ib_mr);
 973 int c4iw_destroy_cq(struct ib_cq *ib_cq);
 974 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
 975                              const struct ib_cq_init_attr *attr,
 976                              struct ib_ucontext *ib_context,
 977                              struct ib_udata *udata);
 978 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
 979 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 980 int c4iw_destroy_qp(struct ib_qp *ib_qp);
 981 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
 982                              struct ib_qp_init_attr *attrs,
 983                              struct ib_udata *udata);
 984 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 985                                  int attr_mask, struct ib_udata *udata);
 986 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 987                      int attr_mask, struct ib_qp_init_attr *init_attr);
 988 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
 989 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
 990 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
 991 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
 992 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
 993 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
 994 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
 995 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
 996 void c4iw_flush_hw_cq(struct c4iw_cq *chp);
 997 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
 998 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
 999 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
1000 int c4iw_flush_sq(struct c4iw_qp *qhp);
1001 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
1002 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
1003 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
1004 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1005 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
1006                 struct c4iw_dev_ucontext *uctx);
1007 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1008 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
1009                 struct c4iw_dev_ucontext *uctx);
1010 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
1011
1012 extern struct cxgb4_client t4c_client;
1013 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
1014 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
1015                               enum cxgb4_bar2_qtype qtype,
1016                               unsigned int *pbar2_qid, u64 *pbar2_pa);
1017 extern void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe);
1018 extern int c4iw_wr_log;
1019 extern int db_fc_threshold;
1020 extern int db_coalescing_threshold;
1021 extern int use_dsgl;
1022 void c4iw_drain_rq(struct ib_qp *qp);
1023 void c4iw_drain_sq(struct ib_qp *qp);
1024 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey);
1025
1026 #endif