arch/arc/boot/dts/axc003.dtsi

   1 /*
   2  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Device tree for AXC003 CPU card: HS38x UP configuration
  11  */
  12
  13 / {
  14         compatible = "snps,arc";
  15         clock-frequency = <90000000>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpu_card {
  20                 compatible = "simple-bus";
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23
  24                 ranges = <0x00000000 0xf0000000 0x10000000>;
  25
  26                 cpu_intc: archs-intc@cpu {
  27                         compatible = "snps,archs-intc";
  28                         interrupt-controller;
  29                         #interrupt-cells = <1>;
  30                 };
  31
  32                 /*
  33                  * this GPIO block ORs all interrupts on CPU card (creg,..)
  34                  * to uplink only 1 IRQ to ARC core intc
  35                  */
  36                 dw-apb-gpio@0x2000 {
  37                         compatible = "snps,dw-apb-gpio";
  38                         reg = < 0x2000 0x80 >;
  39                         #address-cells = <1>;
  40                         #size-cells = <0>;
  41
  42                         ictl_intc: gpio-controller@0 {
  43                                 compatible = "snps,dw-apb-gpio-port";
  44                                 gpio-controller;
  45                                 #gpio-cells = <2>;
  46                                 snps,nr-gpios = <30>;
  47                                 reg = <0>;
  48                                 interrupt-controller;
  49                                 #interrupt-cells = <2>;
  50                                 interrupt-parent = <&cpu_intc>;
  51                                 interrupts = <25>;
  52                         };
  53                 };
  54
  55                 debug_uart: dw-apb-uart@0x5000 {
  56                         compatible = "snps,dw-apb-uart";
  57                         reg = <0x5000 0x100>;
  58                         clock-frequency = <33333000>;
  59                         interrupt-parent = <&ictl_intc>;
  60                         interrupts = <2 4>;
  61                         baud = <115200>;
  62                         reg-shift = <2>;
  63                         reg-io-width = <4>;
  64                 };
  65
  66                 arcpct0: pct {
  67                         compatible = "snps,archs-pct";
  68                         #interrupt-cells = <1>;
  69                         interrupt-parent = <&cpu_intc>;
  70                         interrupts = <20>;
  71                 };
  72         };
  73
  74         /*
  75          * The DW APB ICTL intc on MB is connected to CPU intc via a
  76          * DT "invisible" DW APB GPIO block, configured to simply pass thru
  77          * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
  78          *
  79          * So here we mimic a direct connection betwen them, ignoring the
  80          * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
  81          * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
  82          *
  83          * This intc actually resides on MB, but we move it here to
  84          * avoid duplicating the MB dtsi file given that IRQ from
  85          * this intc to cpu intc are different for axs101 and axs103
  86          */
  87         mb_intc: dw-apb-ictl@0xe0012000 {
  88                 #interrupt-cells = <1>;
  89                 compatible = "snps,dw-apb-ictl";
  90                 reg = < 0xe0012000 0x200 >;
  91                 interrupt-controller;
  92                 interrupt-parent = <&cpu_intc>;
  93                 interrupts = < 24 >;
  94         };
  95
  96         memory {
  97                 #address-cells = <1>;
  98                 #size-cells = <1>;
  99                 ranges = <0x00000000 0x80000000 0x40000000>;
 100                 device_type = "memory";
 101                 reg = <0x80000000 0x20000000>;  /* 512MiB */
 102         };
 103 };