| blob | 688dc7b0d95121a95285a998b6f019a4b8f30cf5 |
1 config ARM
2 bool
3 default y
4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
18 select EDAC_SUPPORT
19 select EDAC_ATOMIC_SCRUB
20 select GENERIC_ALLOCATOR
21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
23 select GENERIC_IDLE_POLL_SETUP
24 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW
26 select GENERIC_IRQ_SHOW_LEVEL
27 select GENERIC_PCI_IOMAP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select GENERIC_STRNCPY_FROM_USER
31 select GENERIC_STRNLEN_USER
32 select HANDLE_DOMAIN_IRQ
33 select HARDIRQS_SW_RESEND
34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
38 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
39 select HAVE_ARCH_TRACEHOOK
40 select HAVE_BPF_JIT
41 select HAVE_CC_STACKPROTECTOR
42 select HAVE_CONTEXT_TRACKING
43 select HAVE_C_RECORDMCOUNT
44 select HAVE_DEBUG_KMEMLEAK
45 select HAVE_DMA_API_DEBUG
46 select HAVE_DMA_ATTRS
47 select HAVE_DMA_CONTIGUOUS if MMU
48 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
49 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
50 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
51 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
52 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
53 select HAVE_GENERIC_DMA_COHERENT
54 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
55 select HAVE_IDE if PCI || ISA || PCMCIA
56 select HAVE_IRQ_TIME_ACCOUNTING
57 select HAVE_KERNEL_GZIP
58 select HAVE_KERNEL_LZ4
59 select HAVE_KERNEL_LZMA
60 select HAVE_KERNEL_LZO
61 select HAVE_KERNEL_XZ
62 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
63 select HAVE_KRETPROBES if (HAVE_KPROBES)
64 select HAVE_MEMBLOCK
65 select HAVE_MOD_ARCH_SPECIFIC
66 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
67 select HAVE_OPTPROBES if !THUMB2_KERNEL
68 select HAVE_PERF_EVENTS
69 select HAVE_PERF_REGS
70 select HAVE_PERF_USER_STACK_DUMP
71 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
72 select HAVE_REGS_AND_STACK_ACCESS_API
73 select HAVE_SYSCALL_TRACEPOINTS
74 select HAVE_UID16
75 select HAVE_VIRT_CPU_ACCOUNTING_GEN
76 select IRQ_FORCED_THREADING
77 select MODULES_USE_ELF_REL
78 select NO_BOOTMEM
79 select OF_EARLY_FLATTREE if OF
80 select OF_RESERVED_MEM if OF
81 select OLD_SIGACTION
82 select OLD_SIGSUSPEND3
83 select PERF_USE_VMALLOC
84 select RTC_LIB
85 select SYS_SUPPORTS_APM_EMULATION
86 # Above selects are sorted alphabetically; please add new ones
87 # according to that. Thanks.
88 help
89 The ARM series is a line of low-power-consumption RISC chip designs
90 licensed by ARM Ltd and targeted at embedded applications and
91 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
92 manufactured, but legacy ARM-based PC hardware remains popular in
93 Europe. There is an ARM Linux project with a web page at
94 <http://www.arm.linux.org.uk/>.
96 config ARM_HAS_SG_CHAIN
97 select ARCH_HAS_SG_CHAIN
98 bool
100 config NEED_SG_DMA_LENGTH
101 bool
103 config ARM_DMA_USE_IOMMU
104 bool
105 select ARM_HAS_SG_CHAIN
106 select NEED_SG_DMA_LENGTH
108 if ARM_DMA_USE_IOMMU
110 config ARM_DMA_IOMMU_ALIGNMENT
111 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
112 range 4 9
113 default 8
114 help
115 DMA mapping framework by default aligns all buffers to the smallest
116 PAGE_SIZE order which is greater than or equal to the requested buffer
117 size. This works well for buffers up to a few hundreds kilobytes, but
118 for larger buffers it just a waste of address space. Drivers which has
119 relatively small addressing window (like 64Mib) might run out of
120 virtual space with just a few allocations.
122 With this parameter you can specify the maximum PAGE_SIZE order for
123 DMA IOMMU buffers. Larger buffers will be aligned only to this
124 specified order. The order is expressed as a power of two multiplied
125 by the PAGE_SIZE.
127 endif
129 config MIGHT_HAVE_PCI
130 bool
132 config SYS_SUPPORTS_APM_EMULATION
133 bool
135 config HAVE_TCM
136 bool
137 select GENERIC_ALLOCATOR
139 config HAVE_PROC_CPU
140 bool
142 config NO_IOPORT_MAP
143 bool
145 config EISA
146 bool
147 ---help---
148 The Extended Industry Standard Architecture (EISA) bus was
149 developed as an open alternative to the IBM MicroChannel bus.
151 The EISA bus provided some of the features of the IBM MicroChannel
152 bus while maintaining backward compatibility with cards made for
153 the older ISA bus. The EISA bus saw limited use between 1988 and
154 1995 when it was made obsolete by the PCI bus.
156 Say Y here if you are building a kernel for an EISA-based machine.
158 Otherwise, say N.
160 config SBUS
161 bool
163 config STACKTRACE_SUPPORT
164 bool
165 default y
167 config HAVE_LATENCYTOP_SUPPORT
168 bool
169 depends on !SMP
170 default y
172 config LOCKDEP_SUPPORT
173 bool
174 default y
176 config TRACE_IRQFLAGS_SUPPORT
177 bool
178 default !CPU_V7M
180 config RWSEM_XCHGADD_ALGORITHM
181 bool
182 default y
184 config ARCH_HAS_ILOG2_U32
185 bool
187 config ARCH_HAS_ILOG2_U64
188 bool
190 config ARCH_HAS_BANDGAP
191 bool
193 config FIX_EARLYCON_MEM
194 def_bool y if MMU
196 config GENERIC_HWEIGHT
197 bool
198 default y
200 config GENERIC_CALIBRATE_DELAY
201 bool
202 default y
204 config ARCH_MAY_HAVE_PC_FDC
205 bool
207 config ZONE_DMA
208 bool
210 config NEED_DMA_MAP_STATE
211 def_bool y
213 config ARCH_SUPPORTS_UPROBES
214 def_bool y
216 config ARCH_HAS_DMA_SET_COHERENT_MASK
217 bool
219 config GENERIC_ISA_DMA
220 bool
222 config FIQ
223 bool
225 config NEED_RET_TO_USER
226 bool
228 config ARCH_MTD_XIP
229 bool
231 config VECTORS_BASE
232 hex
233 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
234 default DRAM_BASE if REMAP_VECTORS_TO_RAM
235 default 0x00000000
236 help
237 The base address of exception vectors. This must be two pages
238 in size.
240 config ARM_PATCH_PHYS_VIRT
241 bool "Patch physical to virtual translations at runtime" if EMBEDDED
242 default y
243 depends on !XIP_KERNEL && MMU
244 depends on !ARCH_REALVIEW || !SPARSEMEM
245 help
246 Patch phys-to-virt and virt-to-phys translation functions at
247 boot and module load time according to the position of the
248 kernel in system memory.
250 This can only be used with non-XIP MMU kernels where the base
251 of physical memory is at a 16MB boundary.
253 Only disable this option if you know that you do not require
254 this feature (eg, building a kernel for a single machine) and
255 you need to shrink the kernel to the minimal size.
257 config NEED_MACH_IO_H
258 bool
259 help
260 Select this when mach/io.h is required to provide special
261 definitions for this platform. The need for mach/io.h should
262 be avoided when possible.
264 config NEED_MACH_MEMORY_H
265 bool
266 help
267 Select this when mach/memory.h is required to provide special
268 definitions for this platform. The need for mach/memory.h should
269 be avoided when possible.
271 config PHYS_OFFSET
272 hex "Physical address of main memory" if MMU
273 depends on !ARM_PATCH_PHYS_VIRT
274 default DRAM_BASE if !MMU
275 default 0x00000000 if ARCH_EBSA110 || \
276 ARCH_FOOTBRIDGE || \
277 ARCH_INTEGRATOR || \
278 ARCH_IOP13XX || \
279 ARCH_KS8695 || \
280 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
281 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
282 default 0x20000000 if ARCH_S5PV210
283 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
284 default 0xc0000000 if ARCH_SA1100
285 help
286 Please provide the physical address corresponding to the
287 location of main memory in your system.
289 config GENERIC_BUG
290 def_bool y
291 depends on BUG
293 config PGTABLE_LEVELS
294 int
295 default 3 if ARM_LPAE
296 default 2
298 source "init/Kconfig"
300 source "kernel/Kconfig.freezer"
302 menu "System Type"
304 config MMU
305 bool "MMU-based Paged Memory Management Support"
306 default y
307 help
308 Select if you want MMU-based virtualised addressing space
309 support by paged memory management. If unsure, say 'Y'.
311 #
312 # The "ARM system type" choice list is ordered alphabetically by option
313 # text. Please add new entries in the option alphabetic order.
314 #
315 choice
316 prompt "ARM system type"
317 default ARCH_VERSATILE if !MMU
318 default ARCH_MULTIPLATFORM if MMU
320 config ARCH_MULTIPLATFORM
321 bool "Allow multiple platforms to be selected"
322 depends on MMU
323 select ARCH_WANT_OPTIONAL_GPIOLIB
324 select ARM_HAS_SG_CHAIN
325 select ARM_PATCH_PHYS_VIRT
326 select AUTO_ZRELADDR
327 select CLKSRC_OF
328 select COMMON_CLK
329 select GENERIC_CLOCKEVENTS
330 select MIGHT_HAVE_PCI
331 select MULTI_IRQ_HANDLER
332 select SPARSE_IRQ
333 select USE_OF
335 config ARM_SINGLE_ARMV7M
336 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
337 depends on !MMU
338 select ARCH_WANT_OPTIONAL_GPIOLIB
339 select ARM_NVIC
340 select AUTO_ZRELADDR
341 select CLKSRC_OF
342 select COMMON_CLK
343 select CPU_V7M
344 select GENERIC_CLOCKEVENTS
345 select NO_IOPORT_MAP
346 select SPARSE_IRQ
347 select USE_OF
349 config ARCH_REALVIEW
350 bool "ARM Ltd. RealView family"
351 select ARCH_WANT_OPTIONAL_GPIOLIB
352 select ARM_AMBA
353 select ARM_TIMER_SP804
354 select COMMON_CLK
355 select COMMON_CLK_VERSATILE
356 select GENERIC_CLOCKEVENTS
357 select GPIO_PL061 if GPIOLIB
358 select ICST
359 select NEED_MACH_MEMORY_H
360 select PLAT_VERSATILE
361 select PLAT_VERSATILE_SCHED_CLOCK
362 help
363 This enables support for ARM Ltd RealView boards.
365 config ARCH_VERSATILE
366 bool "ARM Ltd. Versatile family"
367 select ARCH_WANT_OPTIONAL_GPIOLIB
368 select ARM_AMBA
369 select ARM_TIMER_SP804
370 select ARM_VIC
371 select CLKDEV_LOOKUP
372 select GENERIC_CLOCKEVENTS
373 select HAVE_MACH_CLKDEV
374 select ICST
375 select PLAT_VERSATILE
376 select PLAT_VERSATILE_CLOCK
377 select PLAT_VERSATILE_SCHED_CLOCK
378 select VERSATILE_FPGA_IRQ
379 help
380 This enables support for ARM Ltd Versatile board.
382 config ARCH_CLPS711X
383 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
384 select ARCH_REQUIRE_GPIOLIB
385 select AUTO_ZRELADDR
386 select CLKSRC_MMIO
387 select COMMON_CLK
388 select CPU_ARM720T
389 select GENERIC_CLOCKEVENTS
390 select MFD_SYSCON
391 select SOC_BUS
392 help
393 Support for Cirrus Logic 711x/721x/731x based boards.
395 config ARCH_GEMINI
396 bool "Cortina Systems Gemini"
397 select ARCH_REQUIRE_GPIOLIB
398 select CLKSRC_MMIO
399 select CPU_FA526
400 select GENERIC_CLOCKEVENTS
401 help
402 Support for the Cortina Systems Gemini family SoCs
404 config ARCH_EBSA110
405 bool "EBSA-110"
406 select ARCH_USES_GETTIMEOFFSET
407 select CPU_SA110
408 select ISA
409 select NEED_MACH_IO_H
410 select NEED_MACH_MEMORY_H
411 select NO_IOPORT_MAP
412 help
413 This is an evaluation board for the StrongARM processor available
414 from Digital. It has limited hardware on-board, including an
415 Ethernet interface, two PCMCIA sockets, two serial ports and a
416 parallel port.
418 config ARCH_EP93XX
419 bool "EP93xx-based"
420 select ARCH_HAS_HOLES_MEMORYMODEL
421 select ARCH_REQUIRE_GPIOLIB
422 select ARM_AMBA
423 select ARM_PATCH_PHYS_VIRT
424 select ARM_VIC
425 select AUTO_ZRELADDR
426 select CLKDEV_LOOKUP
427 select CLKSRC_MMIO
428 select CPU_ARM920T
429 select GENERIC_CLOCKEVENTS
430 help
431 This enables support for the Cirrus EP93xx series of CPUs.
433 config ARCH_FOOTBRIDGE
434 bool "FootBridge"
435 select CPU_SA110
436 select FOOTBRIDGE
437 select GENERIC_CLOCKEVENTS
438 select HAVE_IDE
439 select NEED_MACH_IO_H if !MMU
440 select NEED_MACH_MEMORY_H
441 help
442 Support for systems based on the DC21285 companion chip
443 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
445 config ARCH_NETX
446 bool "Hilscher NetX based"
447 select ARM_VIC
448 select CLKSRC_MMIO
449 select CPU_ARM926T
450 select GENERIC_CLOCKEVENTS
451 help
452 This enables support for systems based on the Hilscher NetX Soc
454 config ARCH_IOP13XX
455 bool "IOP13xx-based"
456 depends on MMU
457 select CPU_XSC3
458 select NEED_MACH_MEMORY_H
459 select NEED_RET_TO_USER
460 select PCI
461 select PLAT_IOP
462 select VMSPLIT_1G
463 select SPARSE_IRQ
464 help
465 Support for Intel's IOP13XX (XScale) family of processors.
467 config ARCH_IOP32X
468 bool "IOP32x-based"
469 depends on MMU
470 select ARCH_REQUIRE_GPIOLIB
471 select CPU_XSCALE
472 select GPIO_IOP
473 select NEED_RET_TO_USER
474 select PCI
475 select PLAT_IOP
476 help
477 Support for Intel's 80219 and IOP32X (XScale) family of
478 processors.
480 config ARCH_IOP33X
481 bool "IOP33x-based"
482 depends on MMU
483 select ARCH_REQUIRE_GPIOLIB
484 select CPU_XSCALE
485 select GPIO_IOP
486 select NEED_RET_TO_USER
487 select PCI
488 select PLAT_IOP
489 help
490 Support for Intel's IOP33X (XScale) family of processors.
492 config ARCH_IXP4XX
493 bool "IXP4xx-based"
494 depends on MMU
495 select ARCH_HAS_DMA_SET_COHERENT_MASK
496 select ARCH_REQUIRE_GPIOLIB
497 select ARCH_SUPPORTS_BIG_ENDIAN
498 select CLKSRC_MMIO
499 select CPU_XSCALE
500 select DMABOUNCE if PCI
501 select GENERIC_CLOCKEVENTS
502 select MIGHT_HAVE_PCI
503 select NEED_MACH_IO_H
504 select USB_EHCI_BIG_ENDIAN_DESC
505 select USB_EHCI_BIG_ENDIAN_MMIO
506 help
507 Support for Intel's IXP4XX (XScale) family of processors.
509 config ARCH_DOVE
510 bool "Marvell Dove"
511 select ARCH_REQUIRE_GPIOLIB
512 select CPU_PJ4
513 select GENERIC_CLOCKEVENTS
514 select MIGHT_HAVE_PCI
515 select MVEBU_MBUS
516 select PINCTRL
517 select PINCTRL_DOVE
518 select PLAT_ORION_LEGACY
519 help
520 Support for the Marvell Dove SoC 88AP510
522 config ARCH_MV78XX0
523 bool "Marvell MV78xx0"
524 select ARCH_REQUIRE_GPIOLIB
525 select CPU_FEROCEON
526 select GENERIC_CLOCKEVENTS
527 select MVEBU_MBUS
528 select PCI
529 select PLAT_ORION_LEGACY
530 help
531 Support for the following Marvell MV78xx0 series SoCs:
532 MV781x0, MV782x0.
534 config ARCH_ORION5X
535 bool "Marvell Orion"
536 depends on MMU
537 select ARCH_REQUIRE_GPIOLIB
538 select CPU_FEROCEON
539 select GENERIC_CLOCKEVENTS
540 select MVEBU_MBUS
541 select PCI
542 select PLAT_ORION_LEGACY
543 select MULTI_IRQ_HANDLER
544 help
545 Support for the following Marvell Orion 5x series SoCs:
546 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
547 Orion-2 (5281), Orion-1-90 (6183).
549 config ARCH_MMP
550 bool "Marvell PXA168/910/MMP2"
551 depends on MMU
552 select ARCH_REQUIRE_GPIOLIB
553 select CLKDEV_LOOKUP
554 select GENERIC_ALLOCATOR
555 select GENERIC_CLOCKEVENTS
556 select GPIO_PXA
557 select IRQ_DOMAIN
558 select MULTI_IRQ_HANDLER
559 select PINCTRL
560 select PLAT_PXA
561 select SPARSE_IRQ
562 help
563 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
565 config ARCH_KS8695
566 bool "Micrel/Kendin KS8695"
567 select ARCH_REQUIRE_GPIOLIB
568 select CLKSRC_MMIO
569 select CPU_ARM922T
570 select GENERIC_CLOCKEVENTS
571 select NEED_MACH_MEMORY_H
572 help
573 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
574 System-on-Chip devices.
576 config ARCH_W90X900
577 bool "Nuvoton W90X900 CPU"
578 select ARCH_REQUIRE_GPIOLIB
579 select CLKDEV_LOOKUP
580 select CLKSRC_MMIO
581 select CPU_ARM926T
582 select GENERIC_CLOCKEVENTS
583 help
584 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
585 At present, the w90x900 has been renamed nuc900, regarding
586 the ARM series product line, you can login the following
587 link address to know more.
589 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
590 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
592 config ARCH_LPC32XX
593 bool "NXP LPC32XX"
594 select ARCH_REQUIRE_GPIOLIB
595 select ARM_AMBA
596 select CLKDEV_LOOKUP
597 select CLKSRC_MMIO
598 select CPU_ARM926T
599 select GENERIC_CLOCKEVENTS
600 select HAVE_IDE
601 select USE_OF
602 help
603 Support for the NXP LPC32XX family of processors
605 config ARCH_PXA
606 bool "PXA2xx/PXA3xx-based"
607 depends on MMU
608 select ARCH_MTD_XIP
609 select ARCH_REQUIRE_GPIOLIB
610 select ARM_CPU_SUSPEND if PM
611 select AUTO_ZRELADDR
612 select COMMON_CLK
613 select CLKDEV_LOOKUP
614 select CLKSRC_PXA
615 select CLKSRC_MMIO
616 select CLKSRC_OF
617 select GENERIC_CLOCKEVENTS
618 select GPIO_PXA
619 select HAVE_IDE
620 select IRQ_DOMAIN
621 select MULTI_IRQ_HANDLER
622 select PLAT_PXA
623 select SPARSE_IRQ
624 help
625 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
627 config ARCH_RPC
628 bool "RiscPC"
629 depends on MMU
630 select ARCH_ACORN
631 select ARCH_MAY_HAVE_PC_FDC
632 select ARCH_SPARSEMEM_ENABLE
633 select ARCH_USES_GETTIMEOFFSET
634 select CPU_SA110
635 select FIQ
636 select HAVE_IDE
637 select HAVE_PATA_PLATFORM
638 select ISA_DMA_API
639 select NEED_MACH_IO_H
640 select NEED_MACH_MEMORY_H
641 select NO_IOPORT_MAP
642 select VIRT_TO_BUS
643 help
644 On the Acorn Risc-PC, Linux can support the internal IDE disk and
645 CD-ROM interface, serial and parallel port, and the floppy drive.
647 config ARCH_SA1100
648 bool "SA1100-based"
649 select ARCH_MTD_XIP
650 select ARCH_REQUIRE_GPIOLIB
651 select ARCH_SPARSEMEM_ENABLE
652 select CLKDEV_LOOKUP
653 select CLKSRC_MMIO
654 select CLKSRC_PXA
655 select CLKSRC_OF if OF
656 select CPU_FREQ
657 select CPU_SA1100
658 select GENERIC_CLOCKEVENTS
659 select HAVE_IDE
660 select IRQ_DOMAIN
661 select ISA
662 select MULTI_IRQ_HANDLER
663 select NEED_MACH_MEMORY_H
664 select SPARSE_IRQ
665 help
666 Support for StrongARM 11x0 based boards.
668 config ARCH_S3C24XX
669 bool "Samsung S3C24XX SoCs"
670 select ARCH_REQUIRE_GPIOLIB
671 select ATAGS
672 select CLKDEV_LOOKUP
673 select CLKSRC_SAMSUNG_PWM
674 select GENERIC_CLOCKEVENTS
675 select GPIO_SAMSUNG
676 select HAVE_S3C2410_I2C if I2C
677 select HAVE_S3C2410_WATCHDOG if WATCHDOG
678 select HAVE_S3C_RTC if RTC_CLASS
679 select MULTI_IRQ_HANDLER
680 select NEED_MACH_IO_H
681 select SAMSUNG_ATAGS
682 help
683 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
684 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
685 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
686 Samsung SMDK2410 development board (and derivatives).
688 config ARCH_S3C64XX
689 bool "Samsung S3C64XX"
690 select ARCH_REQUIRE_GPIOLIB
691 select ARM_AMBA
692 select ARM_VIC
693 select ATAGS
694 select CLKDEV_LOOKUP
695 select CLKSRC_SAMSUNG_PWM
696 select COMMON_CLK_SAMSUNG
697 select CPU_V6K
698 select GENERIC_CLOCKEVENTS
699 select GPIO_SAMSUNG
700 select HAVE_S3C2410_I2C if I2C
701 select HAVE_S3C2410_WATCHDOG if WATCHDOG
702 select HAVE_TCM
703 select NO_IOPORT_MAP
704 select PLAT_SAMSUNG
705 select PM_GENERIC_DOMAINS if PM
706 select S3C_DEV_NAND
707 select S3C_GPIO_TRACK
708 select SAMSUNG_ATAGS
709 select SAMSUNG_WAKEMASK
710 select SAMSUNG_WDT_RESET
711 help
712 Samsung S3C64XX series based systems
714 config ARCH_DAVINCI
715 bool "TI DaVinci"
716 select ARCH_HAS_HOLES_MEMORYMODEL
717 select ARCH_REQUIRE_GPIOLIB
718 select CLKDEV_LOOKUP
719 select GENERIC_ALLOCATOR
720 select GENERIC_CLOCKEVENTS
721 select GENERIC_IRQ_CHIP
722 select HAVE_IDE
723 select USE_OF
724 select ZONE_DMA
725 help
726 Support for TI's DaVinci platform.
728 config ARCH_OMAP1
729 bool "TI OMAP1"
730 depends on MMU
731 select ARCH_HAS_HOLES_MEMORYMODEL
732 select ARCH_OMAP
733 select ARCH_REQUIRE_GPIOLIB
734 select CLKDEV_LOOKUP
735 select CLKSRC_MMIO
736 select GENERIC_CLOCKEVENTS
737 select GENERIC_IRQ_CHIP
738 select HAVE_IDE
739 select IRQ_DOMAIN
740 select MULTI_IRQ_HANDLER
741 select NEED_MACH_IO_H if PCCARD
742 select NEED_MACH_MEMORY_H
743 select SPARSE_IRQ
744 help
745 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
747 endchoice
749 menu "Multiple platform selection"
750 depends on ARCH_MULTIPLATFORM
752 comment "CPU Core family selection"
754 config ARCH_MULTI_V4
755 bool "ARMv4 based platforms (FA526)"
756 depends on !ARCH_MULTI_V6_V7
757 select ARCH_MULTI_V4_V5
758 select CPU_FA526
760 config ARCH_MULTI_V4T
761 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
762 depends on !ARCH_MULTI_V6_V7
763 select ARCH_MULTI_V4_V5
764 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
765 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
766 CPU_ARM925T || CPU_ARM940T)
768 config ARCH_MULTI_V5
769 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
770 depends on !ARCH_MULTI_V6_V7
771 select ARCH_MULTI_V4_V5
772 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
773 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
774 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
776 config ARCH_MULTI_V4_V5
777 bool
779 config ARCH_MULTI_V6
780 bool "ARMv6 based platforms (ARM11)"
781 select ARCH_MULTI_V6_V7
782 select CPU_V6K
784 config ARCH_MULTI_V7
785 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
786 default y
787 select ARCH_MULTI_V6_V7
788 select CPU_V7
789 select HAVE_SMP
791 config ARCH_MULTI_V6_V7
792 bool
793 select MIGHT_HAVE_CACHE_L2X0
795 config ARCH_MULTI_CPU_AUTO
796 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
797 select ARCH_MULTI_V5
799 endmenu
801 config ARCH_VIRT
802 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
803 select ARM_AMBA
804 select ARM_GIC
805 select ARM_GIC_V3
806 select ARM_PSCI
807 select HAVE_ARM_ARCH_TIMER
809 #
810 # This is sorted alphabetically by mach-* pathname. However, plat-*
811 # Kconfigs may be included either alphabetically (according to the
812 # plat- suffix) or along side the corresponding mach-* source.
813 #
814 source "arch/arm/mach-mvebu/Kconfig"
816 source "arch/arm/mach-alpine/Kconfig"
818 source "arch/arm/mach-asm9260/Kconfig"
820 source "arch/arm/mach-at91/Kconfig"
822 source "arch/arm/mach-axxia/Kconfig"
824 source "arch/arm/mach-bcm/Kconfig"
826 source "arch/arm/mach-berlin/Kconfig"
828 source "arch/arm/mach-clps711x/Kconfig"
830 source "arch/arm/mach-cns3xxx/Kconfig"
832 source "arch/arm/mach-davinci/Kconfig"
834 source "arch/arm/mach-digicolor/Kconfig"
836 source "arch/arm/mach-dove/Kconfig"
838 source "arch/arm/mach-ep93xx/Kconfig"
840 source "arch/arm/mach-footbridge/Kconfig"
842 source "arch/arm/mach-gemini/Kconfig"
844 source "arch/arm/mach-highbank/Kconfig"
846 source "arch/arm/mach-hisi/Kconfig"
848 source "arch/arm/mach-integrator/Kconfig"
850 source "arch/arm/mach-iop32x/Kconfig"
852 source "arch/arm/mach-iop33x/Kconfig"
854 source "arch/arm/mach-iop13xx/Kconfig"
856 source "arch/arm/mach-ixp4xx/Kconfig"
858 source "arch/arm/mach-keystone/Kconfig"
860 source "arch/arm/mach-ks8695/Kconfig"
862 source "arch/arm/mach-meson/Kconfig"
864 source "arch/arm/mach-moxart/Kconfig"
866 source "arch/arm/mach-mv78xx0/Kconfig"
868 source "arch/arm/mach-imx/Kconfig"
870 source "arch/arm/mach-mediatek/Kconfig"
872 source "arch/arm/mach-mxs/Kconfig"
874 source "arch/arm/mach-netx/Kconfig"
876 source "arch/arm/mach-nomadik/Kconfig"
878 source "arch/arm/mach-nspire/Kconfig"
880 source "arch/arm/plat-omap/Kconfig"
882 source "arch/arm/mach-omap1/Kconfig"
884 source "arch/arm/mach-omap2/Kconfig"
886 source "arch/arm/mach-orion5x/Kconfig"
888 source "arch/arm/mach-picoxcell/Kconfig"
890 source "arch/arm/mach-pxa/Kconfig"
891 source "arch/arm/plat-pxa/Kconfig"
893 source "arch/arm/mach-mmp/Kconfig"
895 source "arch/arm/mach-qcom/Kconfig"
897 source "arch/arm/mach-realview/Kconfig"
899 source "arch/arm/mach-rockchip/Kconfig"
901 source "arch/arm/mach-sa1100/Kconfig"
903 source "arch/arm/mach-socfpga/Kconfig"
905 source "arch/arm/mach-spear/Kconfig"
907 source "arch/arm/mach-sti/Kconfig"
909 source "arch/arm/mach-s3c24xx/Kconfig"
911 source "arch/arm/mach-s3c64xx/Kconfig"
913 source "arch/arm/mach-s5pv210/Kconfig"
915 source "arch/arm/mach-exynos/Kconfig"
916 source "arch/arm/plat-samsung/Kconfig"
918 source "arch/arm/mach-shmobile/Kconfig"
920 source "arch/arm/mach-sunxi/Kconfig"
922 source "arch/arm/mach-prima2/Kconfig"
924 source "arch/arm/mach-tegra/Kconfig"
926 source "arch/arm/mach-u300/Kconfig"
928 source "arch/arm/mach-uniphier/Kconfig"
930 source "arch/arm/mach-ux500/Kconfig"
932 source "arch/arm/mach-versatile/Kconfig"
934 source "arch/arm/mach-vexpress/Kconfig"
935 source "arch/arm/plat-versatile/Kconfig"
937 source "arch/arm/mach-vt8500/Kconfig"
939 source "arch/arm/mach-w90x900/Kconfig"
941 source "arch/arm/mach-zx/Kconfig"
943 source "arch/arm/mach-zynq/Kconfig"
945 # ARMv7-M architecture
946 config ARCH_EFM32
947 bool "Energy Micro efm32"
948 depends on ARM_SINGLE_ARMV7M
949 select ARCH_REQUIRE_GPIOLIB
950 help
951 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
952 processors.
954 config ARCH_LPC18XX
955 bool "NXP LPC18xx/LPC43xx"
956 depends on ARM_SINGLE_ARMV7M
957 select ARCH_HAS_RESET_CONTROLLER
958 select ARM_AMBA
959 select CLKSRC_LPC32XX
960 select PINCTRL
961 help
962 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
963 high performance microcontrollers.
965 config ARCH_STM32
966 bool "STMicrolectronics STM32"
967 depends on ARM_SINGLE_ARMV7M
968 select ARCH_HAS_RESET_CONTROLLER
969 select ARMV7M_SYSTICK
970 select CLKSRC_STM32
971 select RESET_CONTROLLER
972 help
973 Support for STMicroelectronics STM32 processors.
975 # Definitions to make life easier
976 config ARCH_ACORN
977 bool
979 config PLAT_IOP
980 bool
981 select GENERIC_CLOCKEVENTS
983 config PLAT_ORION
984 bool
985 select CLKSRC_MMIO
986 select COMMON_CLK
987 select GENERIC_IRQ_CHIP
988 select IRQ_DOMAIN
990 config PLAT_ORION_LEGACY
991 bool
992 select PLAT_ORION
994 config PLAT_PXA
995 bool
997 config PLAT_VERSATILE
998 bool
1000 source "arch/arm/firmware/Kconfig"
1002 source arch/arm/mm/Kconfig
1004 config IWMMXT
1005 bool "Enable iWMMXt support"
1006 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1007 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1008 help
1009 Enable support for iWMMXt context switching at run time if
1010 running on a CPU that supports it.
1012 config MULTI_IRQ_HANDLER
1013 bool
1014 help
1015 Allow each machine to specify it's own IRQ handler at run time.
1017 if !MMU
1018 source "arch/arm/Kconfig-nommu"
1019 endif
1021 config PJ4B_ERRATA_4742
1022 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1023 depends on CPU_PJ4B && MACH_ARMADA_370
1024 default y
1025 help
1026 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1027 Event (WFE) IDLE states, a specific timing sensitivity exists between
1028 the retiring WFI/WFE instructions and the newly issued subsequent
1029 instructions. This sensitivity can result in a CPU hang scenario.
1030 Workaround:
1031 The software must insert either a Data Synchronization Barrier (DSB)
1032 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1033 instruction
1035 config ARM_ERRATA_326103
1036 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1037 depends on CPU_V6
1038 help
1039 Executing a SWP instruction to read-only memory does not set bit 11
1040 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1041 treat the access as a read, preventing a COW from occurring and
1042 causing the faulting task to livelock.
1044 config ARM_ERRATA_411920
1045 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1046 depends on CPU_V6 || CPU_V6K
1047 help
1048 Invalidation of the Instruction Cache operation can
1049 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1050 It does not affect the MPCore. This option enables the ARM Ltd.
1051 recommended workaround.
1053 config ARM_ERRATA_430973
1054 bool "ARM errata: Stale prediction on replaced interworking branch"
1055 depends on CPU_V7
1056 help
1057 This option enables the workaround for the 430973 Cortex-A8
1058 r1p* erratum. If a code sequence containing an ARM/Thumb
1059 interworking branch is replaced with another code sequence at the
1060 same virtual address, whether due to self-modifying code or virtual
1061 to physical address re-mapping, Cortex-A8 does not recover from the
1062 stale interworking branch prediction. This results in Cortex-A8
1063 executing the new code sequence in the incorrect ARM or Thumb state.
1064 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1065 and also flushes the branch target cache at every context switch.
1066 Note that setting specific bits in the ACTLR register may not be
1067 available in non-secure mode.
1069 config ARM_ERRATA_458693
1070 bool "ARM errata: Processor deadlock when a false hazard is created"
1071 depends on CPU_V7
1072 depends on !ARCH_MULTIPLATFORM
1073 help
1074 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1075 erratum. For very specific sequences of memory operations, it is
1076 possible for a hazard condition intended for a cache line to instead
1077 be incorrectly associated with a different cache line. This false
1078 hazard might then cause a processor deadlock. The workaround enables
1079 the L1 caching of the NEON accesses and disables the PLD instruction
1080 in the ACTLR register. Note that setting specific bits in the ACTLR
1081 register may not be available in non-secure mode.
1083 config ARM_ERRATA_460075
1084 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1085 depends on CPU_V7
1086 depends on !ARCH_MULTIPLATFORM
1087 help
1088 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1089 erratum. Any asynchronous access to the L2 cache may encounter a
1090 situation in which recent store transactions to the L2 cache are lost
1091 and overwritten with stale memory contents from external memory. The
1092 workaround disables the write-allocate mode for the L2 cache via the
1093 ACTLR register. Note that setting specific bits in the ACTLR register
1094 may not be available in non-secure mode.
1096 config ARM_ERRATA_742230
1097 bool "ARM errata: DMB operation may be faulty"
1098 depends on CPU_V7 && SMP
1099 depends on !ARCH_MULTIPLATFORM
1100 help
1101 This option enables the workaround for the 742230 Cortex-A9
1102 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1103 between two write operations may not ensure the correct visibility
1104 ordering of the two writes. This workaround sets a specific bit in
1105 the diagnostic register of the Cortex-A9 which causes the DMB
1106 instruction to behave as a DSB, ensuring the correct behaviour of
1107 the two writes.
1109 config ARM_ERRATA_742231
1110 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1111 depends on CPU_V7 && SMP
1112 depends on !ARCH_MULTIPLATFORM
1113 help
1114 This option enables the workaround for the 742231 Cortex-A9
1115 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1116 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1117 accessing some data located in the same cache line, may get corrupted
1118 data due to bad handling of the address hazard when the line gets
1119 replaced from one of the CPUs at the same time as another CPU is
1120 accessing it. This workaround sets specific bits in the diagnostic
1121 register of the Cortex-A9 which reduces the linefill issuing
1122 capabilities of the processor.
1124 config ARM_ERRATA_643719
1125 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1126 depends on CPU_V7 && SMP
1127 default y
1128 help
1129 This option enables the workaround for the 643719 Cortex-A9 (prior to
1130 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1131 register returns zero when it should return one. The workaround
1132 corrects this value, ensuring cache maintenance operations which use
1133 it behave as intended and avoiding data corruption.
1135 config ARM_ERRATA_720789
1136 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1137 depends on CPU_V7
1138 help
1139 This option enables the workaround for the 720789 Cortex-A9 (prior to
1140 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1141 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1142 As a consequence of this erratum, some TLB entries which should be
1143 invalidated are not, resulting in an incoherency in the system page
1144 tables. The workaround changes the TLB flushing routines to invalidate
1145 entries regardless of the ASID.
1147 config ARM_ERRATA_743622
1148 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1149 depends on CPU_V7
1150 depends on !ARCH_MULTIPLATFORM
1151 help
1152 This option enables the workaround for the 743622 Cortex-A9
1153 (r2p*) erratum. Under very rare conditions, a faulty
1154 optimisation in the Cortex-A9 Store Buffer may lead to data
1155 corruption. This workaround sets a specific bit in the diagnostic
1156 register of the Cortex-A9 which disables the Store Buffer
1157 optimisation, preventing the defect from occurring. This has no
1158 visible impact on the overall performance or power consumption of the
1159 processor.
1161 config ARM_ERRATA_751472
1162 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1163 depends on CPU_V7
1164 depends on !ARCH_MULTIPLATFORM
1165 help
1166 This option enables the workaround for the 751472 Cortex-A9 (prior
1167 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1168 completion of a following broadcasted operation if the second
1169 operation is received by a CPU before the ICIALLUIS has completed,
1170 potentially leading to corrupted entries in the cache or TLB.
1172 config ARM_ERRATA_754322
1173 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1174 depends on CPU_V7
1175 help
1176 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1177 r3p*) erratum. A speculative memory access may cause a page table walk
1178 which starts prior to an ASID switch but completes afterwards. This
1179 can populate the micro-TLB with a stale entry which may be hit with
1180 the new ASID. This workaround places two dsb instructions in the mm
1181 switching code so that no page table walks can cross the ASID switch.
1183 config ARM_ERRATA_754327
1184 bool "ARM errata: no automatic Store Buffer drain"
1185 depends on CPU_V7 && SMP
1186 help
1187 This option enables the workaround for the 754327 Cortex-A9 (prior to
1188 r2p0) erratum. The Store Buffer does not have any automatic draining
1189 mechanism and therefore a livelock may occur if an external agent
1190 continuously polls a memory location waiting to observe an update.
1191 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1192 written polling loops from denying visibility of updates to memory.
1194 config ARM_ERRATA_364296
1195 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1196 depends on CPU_V6
1197 help
1198 This options enables the workaround for the 364296 ARM1136
1199 r0p2 erratum (possible cache data corruption with
1200 hit-under-miss enabled). It sets the undocumented bit 31 in
1201 the auxiliary control register and the FI bit in the control
1202 register, thus disabling hit-under-miss without putting the
1203 processor into full low interrupt latency mode. ARM11MPCore
1204 is not affected.
1206 config ARM_ERRATA_764369
1207 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1208 depends on CPU_V7 && SMP
1209 help
1210 This option enables the workaround for erratum 764369
1211 affecting Cortex-A9 MPCore with two or more processors (all
1212 current revisions). Under certain timing circumstances, a data
1213 cache line maintenance operation by MVA targeting an Inner
1214 Shareable memory region may fail to proceed up to either the
1215 Point of Coherency or to the Point of Unification of the
1216 system. This workaround adds a DSB instruction before the
1217 relevant cache maintenance functions and sets a specific bit
1218 in the diagnostic control register of the SCU.
1220 config ARM_ERRATA_775420
1221 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1222 depends on CPU_V7
1223 help
1224 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1225 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1226 operation aborts with MMU exception, it might cause the processor
1227 to deadlock. This workaround puts DSB before executing ISB if
1228 an abort may occur on cache maintenance.
1230 config ARM_ERRATA_798181
1231 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1232 depends on CPU_V7 && SMP
1233 help
1234 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1235 adequately shooting down all use of the old entries. This
1236 option enables the Linux kernel workaround for this erratum
1237 which sends an IPI to the CPUs that are running the same ASID
1238 as the one being invalidated.
1240 config ARM_ERRATA_773022
1241 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1242 depends on CPU_V7
1243 help
1244 This option enables the workaround for the 773022 Cortex-A15
1245 (up to r0p4) erratum. In certain rare sequences of code, the
1246 loop buffer may deliver incorrect instructions. This
1247 workaround disables the loop buffer to avoid the erratum.
1249 endmenu
1251 source "arch/arm/common/Kconfig"
1253 menu "Bus support"
1255 config ISA
1256 bool
1257 help
1258 Find out whether you have ISA slots on your motherboard. ISA is the
1259 name of a bus system, i.e. the way the CPU talks to the other stuff
1260 inside your box. Other bus systems are PCI, EISA, MicroChannel
1261 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1262 newer boards don't support it. If you have ISA, say Y, otherwise N.
1264 # Select ISA DMA controller support
1265 config ISA_DMA
1266 bool
1267 select ISA_DMA_API
1269 # Select ISA DMA interface
1270 config ISA_DMA_API
1271 bool
1273 config PCI
1274 bool "PCI support" if MIGHT_HAVE_PCI
1275 help
1276 Find out whether you have a PCI motherboard. PCI is the name of a
1277 bus system, i.e. the way the CPU talks to the other stuff inside
1278 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1279 VESA. If you have PCI, say Y, otherwise N.
1281 config PCI_DOMAINS
1282 bool
1283 depends on PCI
1285 config PCI_DOMAINS_GENERIC
1286 def_bool PCI_DOMAINS
1288 config PCI_NANOENGINE
1289 bool "BSE nanoEngine PCI support"
1290 depends on SA1100_NANOENGINE
1291 help
1292 Enable PCI on the BSE nanoEngine board.
1294 config PCI_SYSCALL
1295 def_bool PCI
1297 config PCI_HOST_ITE8152
1298 bool
1299 depends on PCI && MACH_ARMCORE
1300 default y
1301 select DMABOUNCE
1303 source "drivers/pci/Kconfig"
1304 source "drivers/pci/pcie/Kconfig"
1306 source "drivers/pcmcia/Kconfig"
1308 endmenu
1310 menu "Kernel Features"
1312 config HAVE_SMP
1313 bool
1314 help
1315 This option should be selected by machines which have an SMP-
1316 capable CPU.
1318 The only effect of this option is to make the SMP-related
1319 options available to the user for configuration.
1321 config SMP
1322 bool "Symmetric Multi-Processing"
1323 depends on CPU_V6K || CPU_V7
1324 depends on GENERIC_CLOCKEVENTS
1325 depends on HAVE_SMP
1326 depends on MMU || ARM_MPU
1327 select IRQ_WORK
1328 help
1329 This enables support for systems with more than one CPU. If you have
1330 a system with only one CPU, say N. If you have a system with more
1331 than one CPU, say Y.
1333 If you say N here, the kernel will run on uni- and multiprocessor
1334 machines, but will use only one CPU of a multiprocessor machine. If
1335 you say Y here, the kernel will run on many, but not all,
1336 uniprocessor machines. On a uniprocessor machine, the kernel
1337 will run faster if you say N here.
1339 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1340 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1341 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1343 If you don't know what to do here, say N.
1345 config SMP_ON_UP
1346 bool "Allow booting SMP kernel on uniprocessor systems"
1347 depends on SMP && !XIP_KERNEL && MMU
1348 default y
1349 help
1350 SMP kernels contain instructions which fail on non-SMP processors.
1351 Enabling this option allows the kernel to modify itself to make
1352 these instructions safe. Disabling it allows about 1K of space
1353 savings.
1355 If you don't know what to do here, say Y.
1357 config ARM_CPU_TOPOLOGY
1358 bool "Support cpu topology definition"
1359 depends on SMP && CPU_V7
1360 default y
1361 help
1362 Support ARM cpu topology definition. The MPIDR register defines
1363 affinity between processors which is then used to describe the cpu
1364 topology of an ARM System.
1366 config SCHED_MC
1367 bool "Multi-core scheduler support"
1368 depends on ARM_CPU_TOPOLOGY
1369 help
1370 Multi-core scheduler support improves the CPU scheduler's decision
1371 making when dealing with multi-core CPU chips at a cost of slightly
1372 increased overhead in some places. If unsure say N here.
1374 config SCHED_SMT
1375 bool "SMT scheduler support"
1376 depends on ARM_CPU_TOPOLOGY
1377 help
1378 Improves the CPU scheduler's decision making when dealing with
1379 MultiThreading at a cost of slightly increased overhead in some
1380 places. If unsure say N here.
1382 config HAVE_ARM_SCU
1383 bool
1384 help
1385 This option enables support for the ARM system coherency unit
1387 config HAVE_ARM_ARCH_TIMER
1388 bool "Architected timer support"
1389 depends on CPU_V7
1390 select ARM_ARCH_TIMER
1391 select GENERIC_CLOCKEVENTS
1392 help
1393 This option enables support for the ARM architected timer
1395 config HAVE_ARM_TWD
1396 bool
1397 select CLKSRC_OF if OF
1398 help
1399 This options enables support for the ARM timer and watchdog unit
1401 config MCPM
1402 bool "Multi-Cluster Power Management"
1403 depends on CPU_V7 && SMP
1404 help
1405 This option provides the common power management infrastructure
1406 for (multi-)cluster based systems, such as big.LITTLE based
1407 systems.
1409 config MCPM_QUAD_CLUSTER
1410 bool
1411 depends on MCPM
1412 help
1413 To avoid wasting resources unnecessarily, MCPM only supports up
1414 to 2 clusters by default.
1415 Platforms with 3 or 4 clusters that use MCPM must select this
1416 option to allow the additional clusters to be managed.
1418 config BIG_LITTLE
1419 bool "big.LITTLE support (Experimental)"
1420 depends on CPU_V7 && SMP
1421 select MCPM
1422 help
1423 This option enables support selections for the big.LITTLE
1424 system architecture.
1426 config BL_SWITCHER
1427 bool "big.LITTLE switcher support"
1428 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1429 select ARM_CPU_SUSPEND
1430 select CPU_PM
1431 help
1432 The big.LITTLE "switcher" provides the core functionality to
1433 transparently handle transition between a cluster of A15's
1434 and a cluster of A7's in a big.LITTLE system.
1436 config BL_SWITCHER_DUMMY_IF
1437 tristate "Simple big.LITTLE switcher user interface"
1438 depends on BL_SWITCHER && DEBUG_KERNEL
1439 help
1440 This is a simple and dummy char dev interface to control
1441 the big.LITTLE switcher core code. It is meant for
1442 debugging purposes only.
1444 choice
1445 prompt "Memory split"
1446 depends on MMU
1447 default VMSPLIT_3G
1448 help
1449 Select the desired split between kernel and user memory.
1451 If you are not absolutely sure what you are doing, leave this
1452 option alone!
1454 config VMSPLIT_3G
1455 bool "3G/1G user/kernel split"
1456 config VMSPLIT_3G_OPT
1457 bool "3G/1G user/kernel split (for full 1G low memory)"
1458 config VMSPLIT_2G
1459 bool "2G/2G user/kernel split"
1460 config VMSPLIT_1G
1461 bool "1G/3G user/kernel split"
1462 endchoice
1464 config PAGE_OFFSET
1465 hex
1466 default PHYS_OFFSET if !MMU
1467 default 0x40000000 if VMSPLIT_1G
1468 default 0x80000000 if VMSPLIT_2G
1469 default 0xB0000000 if VMSPLIT_3G_OPT
1470 default 0xC0000000
1472 config NR_CPUS
1473 int "Maximum number of CPUs (2-32)"
1474 range 2 32
1475 depends on SMP
1476 default "4"
1478 config HOTPLUG_CPU
1479 bool "Support for hot-pluggable CPUs"
1480 depends on SMP
1481 help
1482 Say Y here to experiment with turning CPUs off and on. CPUs
1483 can be controlled through /sys/devices/system/cpu.
1485 config ARM_PSCI
1486 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1487 depends on CPU_V7
1488 select ARM_PSCI_FW
1489 help
1490 Say Y here if you want Linux to communicate with system firmware
1491 implementing the PSCI specification for CPU-centric power
1492 management operations described in ARM document number ARM DEN
1493 0022A ("Power State Coordination Interface System Software on
1494 ARM processors").
1496 # The GPIO number here must be sorted by descending number. In case of
1497 # a multiplatform kernel, we just want the highest value required by the
1498 # selected platforms.
1499 config ARCH_NR_GPIO
1500 int
1501 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1502 ARCH_ZYNQ
1503 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1504 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1505 default 416 if ARCH_SUNXI
1506 default 392 if ARCH_U8500
1507 default 352 if ARCH_VT8500
1508 default 288 if ARCH_ROCKCHIP
1509 default 264 if MACH_H4700
1510 default 0
1511 help
1512 Maximum number of GPIOs in the system.
1514 If unsure, leave the default value.
1516 source kernel/Kconfig.preempt
1518 config HZ_FIXED
1519 int
1520 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1521 ARCH_S5PV210 || ARCH_EXYNOS4
1522 default 128 if SOC_AT91RM9200
1523 default 0
1525 choice
1526 depends on HZ_FIXED = 0
1527 prompt "Timer frequency"
1529 config HZ_100
1530 bool "100 Hz"
1532 config HZ_200
1533 bool "200 Hz"
1535 config HZ_250
1536 bool "250 Hz"
1538 config HZ_300
1539 bool "300 Hz"
1541 config HZ_500
1542 bool "500 Hz"
1544 config HZ_1000
1545 bool "1000 Hz"
1547 endchoice
1549 config HZ
1550 int
1551 default HZ_FIXED if HZ_FIXED != 0
1552 default 100 if HZ_100
1553 default 200 if HZ_200
1554 default 250 if HZ_250
1555 default 300 if HZ_300
1556 default 500 if HZ_500
1557 default 1000
1559 config SCHED_HRTICK
1560 def_bool HIGH_RES_TIMERS
1562 config THUMB2_KERNEL
1563 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1564 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1565 default y if CPU_THUMBONLY
1566 select AEABI
1567 select ARM_ASM_UNIFIED
1568 select ARM_UNWIND
1569 help
1570 By enabling this option, the kernel will be compiled in
1571 Thumb-2 mode. A compiler/assembler that understand the unified
1572 ARM-Thumb syntax is needed.
1574 If unsure, say N.
1576 config THUMB2_AVOID_R_ARM_THM_JUMP11
1577 bool "Work around buggy Thumb-2 short branch relocations in gas"
1578 depends on THUMB2_KERNEL && MODULES
1579 default y
1580 help
1581 Various binutils versions can resolve Thumb-2 branches to
1582 locally-defined, preemptible global symbols as short-range "b.n"
1583 branch instructions.
1585 This is a problem, because there's no guarantee the final
1586 destination of the symbol, or any candidate locations for a
1587 trampoline, are within range of the branch. For this reason, the
1588 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1589 relocation in modules at all, and it makes little sense to add
1590 support.
1592 The symptom is that the kernel fails with an "unsupported
1593 relocation" error when loading some modules.
1595 Until fixed tools are available, passing
1596 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1597 code which hits this problem, at the cost of a bit of extra runtime
1598 stack usage in some cases.
1600 The problem is described in more detail at:
1601 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1603 Only Thumb-2 kernels are affected.
1605 Unless you are sure your tools don't have this problem, say Y.
1607 config ARM_ASM_UNIFIED
1608 bool
1610 config AEABI
1611 bool "Use the ARM EABI to compile the kernel"
1612 help
1613 This option allows for the kernel to be compiled using the latest
1614 ARM ABI (aka EABI). This is only useful if you are using a user
1615 space environment that is also compiled with EABI.
1617 Since there are major incompatibilities between the legacy ABI and
1618 EABI, especially with regard to structure member alignment, this
1619 option also changes the kernel syscall calling convention to
1620 disambiguate both ABIs and allow for backward compatibility support
1621 (selected with CONFIG_OABI_COMPAT).
1623 To use this you need GCC version 4.0.0 or later.
1625 config OABI_COMPAT
1626 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1627 depends on AEABI && !THUMB2_KERNEL
1628 help
1629 This option preserves the old syscall interface along with the
1630 new (ARM EABI) one. It also provides a compatibility layer to
1631 intercept syscalls that have structure arguments which layout
1632 in memory differs between the legacy ABI and the new ARM EABI
1633 (only for non "thumb" binaries). This option adds a tiny
1634 overhead to all syscalls and produces a slightly larger kernel.
1636 The seccomp filter system will not be available when this is
1637 selected, since there is no way yet to sensibly distinguish
1638 between calling conventions during filtering.
1640 If you know you'll be using only pure EABI user space then you
1641 can say N here. If this option is not selected and you attempt
1642 to execute a legacy ABI binary then the result will be
1643 UNPREDICTABLE (in fact it can be predicted that it won't work
1644 at all). If in doubt say N.
1646 config ARCH_HAS_HOLES_MEMORYMODEL
1647 bool
1649 config ARCH_SPARSEMEM_ENABLE
1650 bool
1652 config ARCH_SPARSEMEM_DEFAULT
1653 def_bool ARCH_SPARSEMEM_ENABLE
1655 config ARCH_SELECT_MEMORY_MODEL
1656 def_bool ARCH_SPARSEMEM_ENABLE
1658 config HAVE_ARCH_PFN_VALID
1659 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1661 config HAVE_GENERIC_RCU_GUP
1662 def_bool y
1663 depends on ARM_LPAE
1665 config HIGHMEM
1666 bool "High Memory Support"
1667 depends on MMU
1668 help
1669 The address space of ARM processors is only 4 Gigabytes large
1670 and it has to accommodate user address space, kernel address
1671 space as well as some memory mapped IO. That means that, if you
1672 have a large amount of physical memory and/or IO, not all of the
1673 memory can be "permanently mapped" by the kernel. The physical
1674 memory that is not permanently mapped is called "high memory".
1676 Depending on the selected kernel/user memory split, minimum
1677 vmalloc space and actual amount of RAM, you may not need this
1678 option which should result in a slightly faster kernel.
1680 If unsure, say n.
1682 config HIGHPTE
1683 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1684 depends on HIGHMEM
1685 default y
1686 help
1687 The VM uses one page of physical memory for each page table.
1688 For systems with a lot of processes, this can use a lot of
1689 precious low memory, eventually leading to low memory being
1690 consumed by page tables. Setting this option will allow
1691 user-space 2nd level page tables to reside in high memory.
1693 config CPU_SW_DOMAIN_PAN
1694 bool "Enable use of CPU domains to implement privileged no-access"
1695 depends on MMU && !ARM_LPAE
1696 default y
1697 help
1698 Increase kernel security by ensuring that normal kernel accesses
1699 are unable to access userspace addresses. This can help prevent
1700 use-after-free bugs becoming an exploitable privilege escalation
1701 by ensuring that magic values (such as LIST_POISON) will always
1702 fault when dereferenced.
1704 CPUs with low-vector mappings use a best-efforts implementation.
1705 Their lower 1MB needs to remain accessible for the vectors, but
1706 the remainder of userspace will become appropriately inaccessible.
1708 config HW_PERF_EVENTS
1709 def_bool y
1710 depends on ARM_PMU
1712 config SYS_SUPPORTS_HUGETLBFS
1713 def_bool y
1714 depends on ARM_LPAE
1716 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1717 def_bool y
1718 depends on ARM_LPAE
1720 config ARCH_WANT_GENERAL_HUGETLB
1721 def_bool y
1723 config ARM_MODULE_PLTS
1724 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1725 depends on MODULES
1726 help
1727 Allocate PLTs when loading modules so that jumps and calls whose
1728 targets are too far away for their relative offsets to be encoded
1729 in the instructions themselves can be bounced via veneers in the
1730 module's PLT. This allows modules to be allocated in the generic
1731 vmalloc area after the dedicated module memory area has been
1732 exhausted. The modules will use slightly more memory, but after
1733 rounding up to page size, the actual memory footprint is usually
1734 the same.
1736 Say y if you are getting out of memory errors while loading modules
1738 source "mm/Kconfig"
1740 config FORCE_MAX_ZONEORDER
1741 int "Maximum zone order"
1742 default "12" if SOC_AM33XX
1743 default "9" if SA1111 || ARCH_EFM32
1744 default "11"
1745 help
1746 The kernel memory allocator divides physically contiguous memory
1747 blocks into "zones", where each zone is a power of two number of
1748 pages. This option selects the largest power of two that the kernel
1749 keeps in the memory allocator. If you need to allocate very large
1750 blocks of physically contiguous memory, then you may need to
1751 increase this value.
1753 This config option is actually maximum order plus one. For example,
1754 a value of 11 means that the largest free memory block is 2^10 pages.
1756 config ALIGNMENT_TRAP
1757 bool
1758 depends on CPU_CP15_MMU
1759 default y if !ARCH_EBSA110
1760 select HAVE_PROC_CPU if PROC_FS
1761 help
1762 ARM processors cannot fetch/store information which is not
1763 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1764 address divisible by 4. On 32-bit ARM processors, these non-aligned
1765 fetch/store instructions will be emulated in software if you say
1766 here, which has a severe performance impact. This is necessary for
1767 correct operation of some network protocols. With an IP-only
1768 configuration it is safe to say N, otherwise say Y.
1770 config UACCESS_WITH_MEMCPY
1771 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1772 depends on MMU
1773 default y if CPU_FEROCEON
1774 help
1775 Implement faster copy_to_user and clear_user methods for CPU
1776 cores where a 8-word STM instruction give significantly higher
1777 memory write throughput than a sequence of individual 32bit stores.
1779 A possible side effect is a slight increase in scheduling latency
1780 between threads sharing the same address space if they invoke
1781 such copy operations with large buffers.
1783 However, if the CPU data cache is using a write-allocate mode,
1784 this option is unlikely to provide any performance gain.
1786 config SECCOMP
1787 bool
1788 prompt "Enable seccomp to safely compute untrusted bytecode"
1789 ---help---
1790 This kernel feature is useful for number crunching applications
1791 that may need to compute untrusted bytecode during their
1792 execution. By using pipes or other transports made available to
1793 the process as file descriptors supporting the read/write
1794 syscalls, it's possible to isolate those applications in
1795 their own address space using seccomp. Once seccomp is
1796 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1797 and the task is only allowed to execute a few safe syscalls
1798 defined by each seccomp mode.
1800 config SWIOTLB
1801 def_bool y
1803 config IOMMU_HELPER
1804 def_bool SWIOTLB
1806 config XEN_DOM0
1807 def_bool y
1808 depends on XEN
1810 config XEN
1811 bool "Xen guest support on ARM"
1812 depends on ARM && AEABI && OF
1813 depends on CPU_V7 && !CPU_V6
1814 depends on !GENERIC_ATOMIC64
1815 depends on MMU
1816 select ARCH_DMA_ADDR_T_64BIT
1817 select ARM_PSCI
1818 select SWIOTLB_XEN
1819 help
1820 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1822 endmenu
1824 menu "Boot options"
1826 config USE_OF
1827 bool "Flattened Device Tree support"
1828 select IRQ_DOMAIN
1829 select OF
1830 help
1831 Include support for flattened device tree machine descriptions.
1833 config ATAGS
1834 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1835 default y
1836 help
1837 This is the traditional way of passing data to the kernel at boot
1838 time. If you are solely relying on the flattened device tree (or
1839 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1840 to remove ATAGS support from your kernel binary. If unsure,
1841 leave this to y.
1843 config DEPRECATED_PARAM_STRUCT
1844 bool "Provide old way to pass kernel parameters"
1845 depends on ATAGS
1846 help
1847 This was deprecated in 2001 and announced to live on for 5 years.
1848 Some old boot loaders still use this way.
1850 # Compressed boot loader in ROM. Yes, we really want to ask about
1851 # TEXT and BSS so we preserve their values in the config files.
1852 config ZBOOT_ROM_TEXT
1853 hex "Compressed ROM boot loader base address"
1854 default "0"
1855 help
1856 The physical address at which the ROM-able zImage is to be
1857 placed in the target. Platforms which normally make use of
1858 ROM-able zImage formats normally set this to a suitable
1859 value in their defconfig file.
1861 If ZBOOT_ROM is not enabled, this has no effect.
1863 config ZBOOT_ROM_BSS
1864 hex "Compressed ROM boot loader BSS address"
1865 default "0"
1866 help
1867 The base address of an area of read/write memory in the target
1868 for the ROM-able zImage which must be available while the
1869 decompressor is running. It must be large enough to hold the
1870 entire decompressed kernel plus an additional 128 KiB.
1871 Platforms which normally make use of ROM-able zImage formats
1872 normally set this to a suitable value in their defconfig file.
1874 If ZBOOT_ROM is not enabled, this has no effect.
1876 config ZBOOT_ROM
1877 bool "Compressed boot loader in ROM/flash"
1878 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1879 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1880 help
1881 Say Y here if you intend to execute your compressed kernel image
1882 (zImage) directly from ROM or flash. If unsure, say N.
1884 config ARM_APPENDED_DTB
1885 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1886 depends on OF
1887 help
1888 With this option, the boot code will look for a device tree binary
1889 (DTB) appended to zImage
1890 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1892 This is meant as a backward compatibility convenience for those
1893 systems with a bootloader that can't be upgraded to accommodate
1894 the documented boot protocol using a device tree.
1896 Beware that there is very little in terms of protection against
1897 this option being confused by leftover garbage in memory that might
1898 look like a DTB header after a reboot if no actual DTB is appended
1899 to zImage. Do not leave this option active in a production kernel
1900 if you don't intend to always append a DTB. Proper passing of the
1901 location into r2 of a bootloader provided DTB is always preferable
1902 to this option.
1904 config ARM_ATAG_DTB_COMPAT
1905 bool "Supplement the appended DTB with traditional ATAG information"
1906 depends on ARM_APPENDED_DTB
1907 help
1908 Some old bootloaders can't be updated to a DTB capable one, yet
1909 they provide ATAGs with memory configuration, the ramdisk address,
1910 the kernel cmdline string, etc. Such information is dynamically
1911 provided by the bootloader and can't always be stored in a static
1912 DTB. To allow a device tree enabled kernel to be used with such
1913 bootloaders, this option allows zImage to extract the information
1914 from the ATAG list and store it at run time into the appended DTB.
1916 choice
1917 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1918 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1920 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1921 bool "Use bootloader kernel arguments if available"
1922 help
1923 Uses the command-line options passed by the boot loader instead of
1924 the device tree bootargs property. If the boot loader doesn't provide
1925 any, the device tree bootargs property will be used.
1927 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1928 bool "Extend with bootloader kernel arguments"
1929 help
1930 The command-line arguments provided by the boot loader will be
1931 appended to the the device tree bootargs property.
1933 endchoice
1935 config CMDLINE
1936 string "Default kernel command string"
1937 default ""
1938 help
1939 On some architectures (EBSA110 and CATS), there is currently no way
1940 for the boot loader to pass arguments to the kernel. For these
1941 architectures, you should supply some command-line options at build
1942 time by entering them here. As a minimum, you should specify the
1943 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1945 choice
1946 prompt "Kernel command line type" if CMDLINE != ""
1947 default CMDLINE_FROM_BOOTLOADER
1948 depends on ATAGS
1950 config CMDLINE_FROM_BOOTLOADER
1951 bool "Use bootloader kernel arguments if available"
1952 help
1953 Uses the command-line options passed by the boot loader. If
1954 the boot loader doesn't provide any, the default kernel command
1955 string provided in CMDLINE will be used.
1957 config CMDLINE_EXTEND
1958 bool "Extend bootloader kernel arguments"
1959 help
1960 The command-line arguments provided by the boot loader will be
1961 appended to the default kernel command string.
1963 config CMDLINE_FORCE
1964 bool "Always use the default kernel command string"
1965 help
1966 Always use the default kernel command string, even if the boot
1967 loader passes other arguments to the kernel.
1968 This is useful if you cannot or don't want to change the
1969 command-line options your boot loader passes to the kernel.
1970 endchoice
1972 config XIP_KERNEL
1973 bool "Kernel Execute-In-Place from ROM"
1974 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1975 help
1976 Execute-In-Place allows the kernel to run from non-volatile storage
1977 directly addressable by the CPU, such as NOR flash. This saves RAM
1978 space since the text section of the kernel is not loaded from flash
1979 to RAM. Read-write sections, such as the data section and stack,
1980 are still copied to RAM. The XIP kernel is not compressed since
1981 it has to run directly from flash, so it will take more space to
1982 store it. The flash address used to link the kernel object files,
1983 and for storing it, is configuration dependent. Therefore, if you
1984 say Y here, you must know the proper physical address where to
1985 store the kernel image depending on your own flash memory usage.
1987 Also note that the make target becomes "make xipImage" rather than
1988 "make zImage" or "make Image". The final kernel binary to put in
1989 ROM memory will be arch/arm/boot/xipImage.
1991 If unsure, say N.
1993 config XIP_PHYS_ADDR
1994 hex "XIP Kernel Physical Location"
1995 depends on XIP_KERNEL
1996 default "0x00080000"
1997 help
1998 This is the physical address in your flash memory the kernel will
1999 be linked for and stored to. This address is dependent on your
2000 own flash usage.
2002 config KEXEC
2003 bool "Kexec system call (EXPERIMENTAL)"
2004 depends on (!SMP || PM_SLEEP_SMP)
2005 depends on !CPU_V7M
2006 select KEXEC_CORE
2007 help
2008 kexec is a system call that implements the ability to shutdown your
2009 current kernel, and to start another kernel. It is like a reboot
2010 but it is independent of the system firmware. And like a reboot
2011 you can start any kernel with it, not just Linux.
2013 It is an ongoing process to be certain the hardware in a machine
2014 is properly shutdown, so do not be surprised if this code does not
2015 initially work for you.
2017 config ATAGS_PROC
2018 bool "Export atags in procfs"
2019 depends on ATAGS && KEXEC
2020 default y
2021 help
2022 Should the atags used to boot the kernel be exported in an "atags"
2023 file in procfs. Useful with kexec.
2025 config CRASH_DUMP
2026 bool "Build kdump crash kernel (EXPERIMENTAL)"
2027 help
2028 Generate crash dump after being started by kexec. This should
2029 be normally only set in special crash dump kernels which are
2030 loaded in the main kernel with kexec-tools into a specially
2031 reserved region and then later executed after a crash by
2032 kdump/kexec. The crash dump kernel must be compiled to a
2033 memory address not used by the main kernel
2035 For more details see Documentation/kdump/kdump.txt
2037 config AUTO_ZRELADDR
2038 bool "Auto calculation of the decompressed kernel image address"
2039 help
2040 ZRELADDR is the physical address where the decompressed kernel
2041 image will be placed. If AUTO_ZRELADDR is selected, the address
2042 will be determined at run-time by masking the current IP with
2043 0xf8000000. This assumes the zImage being placed in the first 128MB
2044 from start of memory.
2046 endmenu
2048 menu "CPU Power Management"
2050 source "drivers/cpufreq/Kconfig"
2052 source "drivers/cpuidle/Kconfig"
2054 endmenu
2056 menu "Floating point emulation"
2058 comment "At least one emulation must be selected"
2060 config FPE_NWFPE
2061 bool "NWFPE math emulation"
2062 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2063 ---help---
2064 Say Y to include the NWFPE floating point emulator in the kernel.
2065 This is necessary to run most binaries. Linux does not currently
2066 support floating point hardware so you need to say Y here even if
2067 your machine has an FPA or floating point co-processor podule.
2069 You may say N here if you are going to load the Acorn FPEmulator
2070 early in the bootup.
2072 config FPE_NWFPE_XP
2073 bool "Support extended precision"
2074 depends on FPE_NWFPE
2075 help
2076 Say Y to include 80-bit support in the kernel floating-point
2077 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2078 Note that gcc does not generate 80-bit operations by default,
2079 so in most cases this option only enlarges the size of the
2080 floating point emulator without any good reason.
2082 You almost surely want to say N here.
2084 config FPE_FASTFPE
2085 bool "FastFPE math emulation (EXPERIMENTAL)"
2086 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2087 ---help---
2088 Say Y here to include the FAST floating point emulator in the kernel.
2089 This is an experimental much faster emulator which now also has full
2090 precision for the mantissa. It does not support any exceptions.
2091 It is very simple, and approximately 3-6 times faster than NWFPE.
2093 It should be sufficient for most programs. It may be not suitable
2094 for scientific calculations, but you have to check this for yourself.
2095 If you do not feel you need a faster FP emulation you should better
2096 choose NWFPE.
2098 config VFP
2099 bool "VFP-format floating point maths"
2100 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2101 help
2102 Say Y to include VFP support code in the kernel. This is needed
2103 if your hardware includes a VFP unit.
2105 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2106 release notes and additional status information.
2108 Say N if your target does not have VFP hardware.
2110 config VFPv3
2111 bool
2112 depends on VFP
2113 default y if CPU_V7
2115 config NEON
2116 bool "Advanced SIMD (NEON) Extension support"
2117 depends on VFPv3 && CPU_V7
2118 help
2119 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2120 Extension.
2122 config KERNEL_MODE_NEON
2123 bool "Support for NEON in kernel mode"
2124 depends on NEON && AEABI
2125 help
2126 Say Y to include support for NEON in kernel mode.
2128 endmenu
2130 menu "Userspace binary formats"
2132 source "fs/Kconfig.binfmt"
2134 endmenu
2136 menu "Power management options"
2138 source "kernel/power/Kconfig"
2140 config ARCH_SUSPEND_POSSIBLE
2141 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2142 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2143 def_bool y
2145 config ARM_CPU_SUSPEND
2146 def_bool PM_SLEEP
2148 config ARCH_HIBERNATION_POSSIBLE
2149 bool
2150 depends on MMU
2151 default y if ARCH_SUSPEND_POSSIBLE
2153 endmenu
2155 source "net/Kconfig"
2157 source "drivers/Kconfig"
2159 source "drivers/firmware/Kconfig"
2161 source "fs/Kconfig"
2163 source "arch/arm/Kconfig.debug"
2165 source "security/Kconfig"
2167 source "crypto/Kconfig"
2168 if CRYPTO
2169 source "arch/arm/crypto/Kconfig"
2170 endif
2172 source "lib/Kconfig"
2174 source "arch/arm/kvm/Kconfig"