| blob | d8ba99f1d87ba396b4e320ec52e63f903461d6bf |
1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "skeleton.dtsi"
12 #include "imx6sl-pinfunc.h"
13 #include <dt-bindings/clock/imx6sl-clock.h>
15 / {
16 aliases {
17 ethernet0 = &fec;
18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
22 gpio4 = &gpio5;
23 serial0 = &uart1;
24 serial1 = &uart2;
25 serial2 = &uart3;
26 serial3 = &uart4;
27 serial4 = &uart5;
28 spi0 = &ecspi1;
29 spi1 = &ecspi2;
30 spi2 = &ecspi3;
31 spi3 = &ecspi4;
32 usbphy0 = &usbphy1;
33 usbphy1 = &usbphy2;
34 };
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
40 cpu@0 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 reg = <0x0>;
44 next-level-cache = <&L2>;
45 operating-points = <
46 /* kHz uV */
47 996000 1275000
48 792000 1175000
49 396000 975000
50 >;
51 fsl,soc-operating-points = <
52 /* ARM kHz SOC-PU uV */
53 996000 1225000
54 792000 1175000
55 396000 1175000
56 >;
57 clock-latency = <61036>; /* two CLK32 periods */
58 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
59 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
60 <&clks IMX6SL_CLK_PLL1_SYS>;
61 clock-names = "arm", "pll2_pfd2_396m", "step",
62 "pll1_sw", "pll1_sys";
63 arm-supply = <®_arm>;
64 pu-supply = <®_pu>;
65 soc-supply = <®_soc>;
66 };
67 };
69 intc: interrupt-controller@00a01000 {
70 compatible = "arm,cortex-a9-gic";
71 #interrupt-cells = <3>;
72 interrupt-controller;
73 reg = <0x00a01000 0x1000>,
74 <0x00a00100 0x100>;
75 interrupt-parent = <&intc>;
76 };
78 clocks {
79 #address-cells = <1>;
80 #size-cells = <0>;
82 ckil {
83 compatible = "fixed-clock";
84 #clock-cells = <0>;
85 clock-frequency = <32768>;
86 };
88 osc {
89 compatible = "fixed-clock";
90 #clock-cells = <0>;
91 clock-frequency = <24000000>;
92 };
93 };
95 soc {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 compatible = "simple-bus";
99 interrupt-parent = <&gpc>;
100 ranges;
102 ocram: sram@00900000 {
103 compatible = "mmio-sram";
104 reg = <0x00900000 0x20000>;
105 clocks = <&clks IMX6SL_CLK_OCRAM>;
106 };
108 L2: l2-cache@00a02000 {
109 compatible = "arm,pl310-cache";
110 reg = <0x00a02000 0x1000>;
111 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
112 cache-unified;
113 cache-level = <2>;
114 arm,tag-latency = <4 2 3>;
115 arm,data-latency = <4 2 3>;
116 };
118 pmu {
119 compatible = "arm,cortex-a9-pmu";
120 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
121 };
123 aips1: aips-bus@02000000 {
124 compatible = "fsl,aips-bus", "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 reg = <0x02000000 0x100000>;
128 ranges;
130 spba: spba-bus@02000000 {
131 compatible = "fsl,spba-bus", "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 reg = <0x02000000 0x40000>;
135 ranges;
137 spdif: spdif@02004000 {
138 compatible = "fsl,imx6sl-spdif",
139 "fsl,imx35-spdif";
140 reg = <0x02004000 0x4000>;
141 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
142 dmas = <&sdma 14 18 0>,
143 <&sdma 15 18 0>;
144 dma-names = "rx", "tx";
145 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
146 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
147 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
148 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
149 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
150 clock-names = "core", "rxtx0",
151 "rxtx1", "rxtx2",
152 "rxtx3", "rxtx4",
153 "rxtx5", "rxtx6",
154 "rxtx7", "dma";
155 status = "disabled";
156 };
158 ecspi1: ecspi@02008000 {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
162 reg = <0x02008000 0x4000>;
163 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&clks IMX6SL_CLK_ECSPI1>,
165 <&clks IMX6SL_CLK_ECSPI1>;
166 clock-names = "ipg", "per";
167 status = "disabled";
168 };
170 ecspi2: ecspi@0200c000 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
174 reg = <0x0200c000 0x4000>;
175 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clks IMX6SL_CLK_ECSPI2>,
177 <&clks IMX6SL_CLK_ECSPI2>;
178 clock-names = "ipg", "per";
179 status = "disabled";
180 };
182 ecspi3: ecspi@02010000 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
186 reg = <0x02010000 0x4000>;
187 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&clks IMX6SL_CLK_ECSPI3>,
189 <&clks IMX6SL_CLK_ECSPI3>;
190 clock-names = "ipg", "per";
191 status = "disabled";
192 };
194 ecspi4: ecspi@02014000 {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
198 reg = <0x02014000 0x4000>;
199 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&clks IMX6SL_CLK_ECSPI4>,
201 <&clks IMX6SL_CLK_ECSPI4>;
202 clock-names = "ipg", "per";
203 status = "disabled";
204 };
206 uart5: serial@02018000 {
207 compatible = "fsl,imx6sl-uart",
208 "fsl,imx6q-uart", "fsl,imx21-uart";
209 reg = <0x02018000 0x4000>;
210 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&clks IMX6SL_CLK_UART>,
212 <&clks IMX6SL_CLK_UART_SERIAL>;
213 clock-names = "ipg", "per";
214 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
215 dma-names = "rx", "tx";
216 status = "disabled";
217 };
219 uart1: serial@02020000 {
220 compatible = "fsl,imx6sl-uart",
221 "fsl,imx6q-uart", "fsl,imx21-uart";
222 reg = <0x02020000 0x4000>;
223 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&clks IMX6SL_CLK_UART>,
225 <&clks IMX6SL_CLK_UART_SERIAL>;
226 clock-names = "ipg", "per";
227 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
228 dma-names = "rx", "tx";
229 status = "disabled";
230 };
232 uart2: serial@02024000 {
233 compatible = "fsl,imx6sl-uart",
234 "fsl,imx6q-uart", "fsl,imx21-uart";
235 reg = <0x02024000 0x4000>;
236 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&clks IMX6SL_CLK_UART>,
238 <&clks IMX6SL_CLK_UART_SERIAL>;
239 clock-names = "ipg", "per";
240 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
241 dma-names = "rx", "tx";
242 status = "disabled";
243 };
245 ssi1: ssi@02028000 {
246 #sound-dai-cells = <0>;
247 compatible = "fsl,imx6sl-ssi",
248 "fsl,imx51-ssi";
249 reg = <0x02028000 0x4000>;
250 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
252 <&clks IMX6SL_CLK_SSI1>;
253 clock-names = "ipg", "baud";
254 dmas = <&sdma 37 1 0>,
255 <&sdma 38 1 0>;
256 dma-names = "rx", "tx";
257 fsl,fifo-depth = <15>;
258 status = "disabled";
259 };
261 ssi2: ssi@0202c000 {
262 #sound-dai-cells = <0>;
263 compatible = "fsl,imx6sl-ssi",
264 "fsl,imx51-ssi";
265 reg = <0x0202c000 0x4000>;
266 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
268 <&clks IMX6SL_CLK_SSI2>;
269 clock-names = "ipg", "baud";
270 dmas = <&sdma 41 1 0>,
271 <&sdma 42 1 0>;
272 dma-names = "rx", "tx";
273 fsl,fifo-depth = <15>;
274 status = "disabled";
275 };
277 ssi3: ssi@02030000 {
278 #sound-dai-cells = <0>;
279 compatible = "fsl,imx6sl-ssi",
280 "fsl,imx51-ssi";
281 reg = <0x02030000 0x4000>;
282 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
284 <&clks IMX6SL_CLK_SSI3>;
285 clock-names = "ipg", "baud";
286 dmas = <&sdma 45 1 0>,
287 <&sdma 46 1 0>;
288 dma-names = "rx", "tx";
289 fsl,fifo-depth = <15>;
290 status = "disabled";
291 };
293 uart3: serial@02034000 {
294 compatible = "fsl,imx6sl-uart",
295 "fsl,imx6q-uart", "fsl,imx21-uart";
296 reg = <0x02034000 0x4000>;
297 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&clks IMX6SL_CLK_UART>,
299 <&clks IMX6SL_CLK_UART_SERIAL>;
300 clock-names = "ipg", "per";
301 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
302 dma-names = "rx", "tx";
303 status = "disabled";
304 };
306 uart4: serial@02038000 {
307 compatible = "fsl,imx6sl-uart",
308 "fsl,imx6q-uart", "fsl,imx21-uart";
309 reg = <0x02038000 0x4000>;
310 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clks IMX6SL_CLK_UART>,
312 <&clks IMX6SL_CLK_UART_SERIAL>;
313 clock-names = "ipg", "per";
314 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
315 dma-names = "rx", "tx";
316 status = "disabled";
317 };
318 };
320 pwm1: pwm@02080000 {
321 #pwm-cells = <2>;
322 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
323 reg = <0x02080000 0x4000>;
324 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&clks IMX6SL_CLK_PWM1>,
326 <&clks IMX6SL_CLK_PWM1>;
327 clock-names = "ipg", "per";
328 };
330 pwm2: pwm@02084000 {
331 #pwm-cells = <2>;
332 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
333 reg = <0x02084000 0x4000>;
334 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&clks IMX6SL_CLK_PWM2>,
336 <&clks IMX6SL_CLK_PWM2>;
337 clock-names = "ipg", "per";
338 };
340 pwm3: pwm@02088000 {
341 #pwm-cells = <2>;
342 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
343 reg = <0x02088000 0x4000>;
344 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&clks IMX6SL_CLK_PWM3>,
346 <&clks IMX6SL_CLK_PWM3>;
347 clock-names = "ipg", "per";
348 };
350 pwm4: pwm@0208c000 {
351 #pwm-cells = <2>;
352 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
353 reg = <0x0208c000 0x4000>;
354 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&clks IMX6SL_CLK_PWM4>,
356 <&clks IMX6SL_CLK_PWM4>;
357 clock-names = "ipg", "per";
358 };
360 gpt: gpt@02098000 {
361 compatible = "fsl,imx6sl-gpt";
362 reg = <0x02098000 0x4000>;
363 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clks IMX6SL_CLK_GPT>,
365 <&clks IMX6SL_CLK_GPT_SERIAL>;
366 clock-names = "ipg", "per";
367 };
369 gpio1: gpio@0209c000 {
370 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
371 reg = <0x0209c000 0x4000>;
372 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
373 <0 67 IRQ_TYPE_LEVEL_HIGH>;
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
378 };
380 gpio2: gpio@020a0000 {
381 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
382 reg = <0x020a0000 0x4000>;
383 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
384 <0 69 IRQ_TYPE_LEVEL_HIGH>;
385 gpio-controller;
386 #gpio-cells = <2>;
387 interrupt-controller;
388 #interrupt-cells = <2>;
389 };
391 gpio3: gpio@020a4000 {
392 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
393 reg = <0x020a4000 0x4000>;
394 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
395 <0 71 IRQ_TYPE_LEVEL_HIGH>;
396 gpio-controller;
397 #gpio-cells = <2>;
398 interrupt-controller;
399 #interrupt-cells = <2>;
400 };
402 gpio4: gpio@020a8000 {
403 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
404 reg = <0x020a8000 0x4000>;
405 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
406 <0 73 IRQ_TYPE_LEVEL_HIGH>;
407 gpio-controller;
408 #gpio-cells = <2>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
411 };
413 gpio5: gpio@020ac000 {
414 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
415 reg = <0x020ac000 0x4000>;
416 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
417 <0 75 IRQ_TYPE_LEVEL_HIGH>;
418 gpio-controller;
419 #gpio-cells = <2>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
422 };
424 kpp: kpp@020b8000 {
425 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
426 reg = <0x020b8000 0x4000>;
427 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&clks IMX6SL_CLK_DUMMY>;
429 status = "disabled";
430 };
432 wdog1: wdog@020bc000 {
433 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
434 reg = <0x020bc000 0x4000>;
435 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&clks IMX6SL_CLK_DUMMY>;
437 };
439 wdog2: wdog@020c0000 {
440 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
441 reg = <0x020c0000 0x4000>;
442 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clks IMX6SL_CLK_DUMMY>;
444 status = "disabled";
445 };
447 clks: ccm@020c4000 {
448 compatible = "fsl,imx6sl-ccm";
449 reg = <0x020c4000 0x4000>;
450 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
451 <0 88 IRQ_TYPE_LEVEL_HIGH>;
452 #clock-cells = <1>;
453 };
455 anatop: anatop@020c8000 {
456 compatible = "fsl,imx6sl-anatop",
457 "fsl,imx6q-anatop",
458 "syscon", "simple-bus";
459 reg = <0x020c8000 0x1000>;
460 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
461 <0 54 IRQ_TYPE_LEVEL_HIGH>,
462 <0 127 IRQ_TYPE_LEVEL_HIGH>;
464 regulator-1p1@110 {
465 compatible = "fsl,anatop-regulator";
466 regulator-name = "vdd1p1";
467 regulator-min-microvolt = <800000>;
468 regulator-max-microvolt = <1375000>;
469 regulator-always-on;
470 anatop-reg-offset = <0x110>;
471 anatop-vol-bit-shift = <8>;
472 anatop-vol-bit-width = <5>;
473 anatop-min-bit-val = <4>;
474 anatop-min-voltage = <800000>;
475 anatop-max-voltage = <1375000>;
476 };
478 regulator-3p0@120 {
479 compatible = "fsl,anatop-regulator";
480 regulator-name = "vdd3p0";
481 regulator-min-microvolt = <2800000>;
482 regulator-max-microvolt = <3150000>;
483 regulator-always-on;
484 anatop-reg-offset = <0x120>;
485 anatop-vol-bit-shift = <8>;
486 anatop-vol-bit-width = <5>;
487 anatop-min-bit-val = <0>;
488 anatop-min-voltage = <2625000>;
489 anatop-max-voltage = <3400000>;
490 };
492 regulator-2p5@130 {
493 compatible = "fsl,anatop-regulator";
494 regulator-name = "vdd2p5";
495 regulator-min-microvolt = <2100000>;
496 regulator-max-microvolt = <2850000>;
497 regulator-always-on;
498 anatop-reg-offset = <0x130>;
499 anatop-vol-bit-shift = <8>;
500 anatop-vol-bit-width = <5>;
501 anatop-min-bit-val = <0>;
502 anatop-min-voltage = <2100000>;
503 anatop-max-voltage = <2850000>;
504 };
506 reg_arm: regulator-vddcore@140 {
507 compatible = "fsl,anatop-regulator";
508 regulator-name = "vddarm";
509 regulator-min-microvolt = <725000>;
510 regulator-max-microvolt = <1450000>;
511 regulator-always-on;
512 anatop-reg-offset = <0x140>;
513 anatop-vol-bit-shift = <0>;
514 anatop-vol-bit-width = <5>;
515 anatop-delay-reg-offset = <0x170>;
516 anatop-delay-bit-shift = <24>;
517 anatop-delay-bit-width = <2>;
518 anatop-min-bit-val = <1>;
519 anatop-min-voltage = <725000>;
520 anatop-max-voltage = <1450000>;
521 };
523 reg_pu: regulator-vddpu@140 {
524 compatible = "fsl,anatop-regulator";
525 regulator-name = "vddpu";
526 regulator-min-microvolt = <725000>;
527 regulator-max-microvolt = <1450000>;
528 regulator-always-on;
529 anatop-reg-offset = <0x140>;
530 anatop-vol-bit-shift = <9>;
531 anatop-vol-bit-width = <5>;
532 anatop-delay-reg-offset = <0x170>;
533 anatop-delay-bit-shift = <26>;
534 anatop-delay-bit-width = <2>;
535 anatop-min-bit-val = <1>;
536 anatop-min-voltage = <725000>;
537 anatop-max-voltage = <1450000>;
538 };
540 reg_soc: regulator-vddsoc@140 {
541 compatible = "fsl,anatop-regulator";
542 regulator-name = "vddsoc";
543 regulator-min-microvolt = <725000>;
544 regulator-max-microvolt = <1450000>;
545 regulator-always-on;
546 anatop-reg-offset = <0x140>;
547 anatop-vol-bit-shift = <18>;
548 anatop-vol-bit-width = <5>;
549 anatop-delay-reg-offset = <0x170>;
550 anatop-delay-bit-shift = <28>;
551 anatop-delay-bit-width = <2>;
552 anatop-min-bit-val = <1>;
553 anatop-min-voltage = <725000>;
554 anatop-max-voltage = <1450000>;
555 };
556 };
558 tempmon: tempmon {
559 compatible = "fsl,imx6q-tempmon";
560 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
561 fsl,tempmon = <&anatop>;
562 fsl,tempmon-data = <&ocotp>;
563 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
564 };
566 usbphy1: usbphy@020c9000 {
567 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
568 reg = <0x020c9000 0x1000>;
569 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&clks IMX6SL_CLK_USBPHY1>;
571 fsl,anatop = <&anatop>;
572 };
574 usbphy2: usbphy@020ca000 {
575 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
576 reg = <0x020ca000 0x1000>;
577 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&clks IMX6SL_CLK_USBPHY2>;
579 fsl,anatop = <&anatop>;
580 };
582 snvs: snvs@020cc000 {
583 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
584 reg = <0x020cc000 0x4000>;
586 snvs_rtc: snvs-rtc-lp {
587 compatible = "fsl,sec-v4.0-mon-rtc-lp";
588 regmap = <&snvs>;
589 offset = <0x34>;
590 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
591 <0 20 IRQ_TYPE_LEVEL_HIGH>;
592 };
594 snvs_poweroff: snvs-poweroff {
595 compatible = "syscon-poweroff";
596 regmap = <&snvs>;
597 offset = <0x38>;
598 mask = <0x60>;
599 status = "disabled";
600 };
601 };
603 epit1: epit@020d0000 {
604 reg = <0x020d0000 0x4000>;
605 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
606 };
608 epit2: epit@020d4000 {
609 reg = <0x020d4000 0x4000>;
610 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
611 };
613 src: src@020d8000 {
614 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
615 reg = <0x020d8000 0x4000>;
616 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
617 <0 96 IRQ_TYPE_LEVEL_HIGH>;
618 #reset-cells = <1>;
619 };
621 gpc: gpc@020dc000 {
622 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
623 reg = <0x020dc000 0x4000>;
624 interrupt-controller;
625 #interrupt-cells = <3>;
626 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
627 interrupt-parent = <&intc>;
628 pu-supply = <®_pu>;
629 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
630 <&clks IMX6SL_CLK_GPU2D_PODF>;
631 #power-domain-cells = <1>;
632 };
634 gpr: iomuxc-gpr@020e0000 {
635 compatible = "fsl,imx6sl-iomuxc-gpr",
636 "fsl,imx6q-iomuxc-gpr", "syscon";
637 reg = <0x020e0000 0x38>;
638 };
640 iomuxc: iomuxc@020e0000 {
641 compatible = "fsl,imx6sl-iomuxc";
642 reg = <0x020e0000 0x4000>;
643 };
645 csi: csi@020e4000 {
646 reg = <0x020e4000 0x4000>;
647 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
648 };
650 spdc: spdc@020e8000 {
651 reg = <0x020e8000 0x4000>;
652 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
653 };
655 sdma: sdma@020ec000 {
656 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
657 reg = <0x020ec000 0x4000>;
658 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&clks IMX6SL_CLK_SDMA>,
660 <&clks IMX6SL_CLK_SDMA>;
661 clock-names = "ipg", "ahb";
662 #dma-cells = <3>;
663 /* imx6sl reuses imx6q sdma firmware */
664 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
665 };
667 pxp: pxp@020f0000 {
668 reg = <0x020f0000 0x4000>;
669 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
670 };
672 epdc: epdc@020f4000 {
673 reg = <0x020f4000 0x4000>;
674 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
675 };
677 lcdif: lcdif@020f8000 {
678 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
679 reg = <0x020f8000 0x4000>;
680 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
682 <&clks IMX6SL_CLK_LCDIF_AXI>,
683 <&clks IMX6SL_CLK_DUMMY>;
684 clock-names = "pix", "axi", "disp_axi";
685 status = "disabled";
686 };
688 dcp: dcp@020fc000 {
689 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
690 reg = <0x020fc000 0x4000>;
691 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
692 <0 100 IRQ_TYPE_LEVEL_HIGH>,
693 <0 101 IRQ_TYPE_LEVEL_HIGH>;
694 };
695 };
697 aips2: aips-bus@02100000 {
698 compatible = "fsl,aips-bus", "simple-bus";
699 #address-cells = <1>;
700 #size-cells = <1>;
701 reg = <0x02100000 0x100000>;
702 ranges;
704 usbotg1: usb@02184000 {
705 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
706 reg = <0x02184000 0x200>;
707 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&clks IMX6SL_CLK_USBOH3>;
709 fsl,usbphy = <&usbphy1>;
710 fsl,usbmisc = <&usbmisc 0>;
711 status = "disabled";
712 };
714 usbotg2: usb@02184200 {
715 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
716 reg = <0x02184200 0x200>;
717 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&clks IMX6SL_CLK_USBOH3>;
719 fsl,usbphy = <&usbphy2>;
720 fsl,usbmisc = <&usbmisc 1>;
721 status = "disabled";
722 };
724 usbh: usb@02184400 {
725 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
726 reg = <0x02184400 0x200>;
727 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&clks IMX6SL_CLK_USBOH3>;
729 fsl,usbmisc = <&usbmisc 2>;
730 dr_mode = "host";
731 status = "disabled";
732 };
734 usbmisc: usbmisc@02184800 {
735 #index-cells = <1>;
736 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
737 reg = <0x02184800 0x200>;
738 clocks = <&clks IMX6SL_CLK_USBOH3>;
739 };
741 fec: ethernet@02188000 {
742 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
743 reg = <0x02188000 0x4000>;
744 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&clks IMX6SL_CLK_ENET>,
746 <&clks IMX6SL_CLK_ENET_REF>;
747 clock-names = "ipg", "ahb";
748 status = "disabled";
749 };
751 usdhc1: usdhc@02190000 {
752 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
753 reg = <0x02190000 0x4000>;
754 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&clks IMX6SL_CLK_USDHC1>,
756 <&clks IMX6SL_CLK_USDHC1>,
757 <&clks IMX6SL_CLK_USDHC1>;
758 clock-names = "ipg", "ahb", "per";
759 bus-width = <4>;
760 status = "disabled";
761 };
763 usdhc2: usdhc@02194000 {
764 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
765 reg = <0x02194000 0x4000>;
766 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&clks IMX6SL_CLK_USDHC2>,
768 <&clks IMX6SL_CLK_USDHC2>,
769 <&clks IMX6SL_CLK_USDHC2>;
770 clock-names = "ipg", "ahb", "per";
771 bus-width = <4>;
772 status = "disabled";
773 };
775 usdhc3: usdhc@02198000 {
776 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
777 reg = <0x02198000 0x4000>;
778 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&clks IMX6SL_CLK_USDHC3>,
780 <&clks IMX6SL_CLK_USDHC3>,
781 <&clks IMX6SL_CLK_USDHC3>;
782 clock-names = "ipg", "ahb", "per";
783 bus-width = <4>;
784 status = "disabled";
785 };
787 usdhc4: usdhc@0219c000 {
788 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
789 reg = <0x0219c000 0x4000>;
790 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&clks IMX6SL_CLK_USDHC4>,
792 <&clks IMX6SL_CLK_USDHC4>,
793 <&clks IMX6SL_CLK_USDHC4>;
794 clock-names = "ipg", "ahb", "per";
795 bus-width = <4>;
796 status = "disabled";
797 };
799 i2c1: i2c@021a0000 {
800 #address-cells = <1>;
801 #size-cells = <0>;
802 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
803 reg = <0x021a0000 0x4000>;
804 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&clks IMX6SL_CLK_I2C1>;
806 status = "disabled";
807 };
809 i2c2: i2c@021a4000 {
810 #address-cells = <1>;
811 #size-cells = <0>;
812 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
813 reg = <0x021a4000 0x4000>;
814 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&clks IMX6SL_CLK_I2C2>;
816 status = "disabled";
817 };
819 i2c3: i2c@021a8000 {
820 #address-cells = <1>;
821 #size-cells = <0>;
822 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
823 reg = <0x021a8000 0x4000>;
824 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&clks IMX6SL_CLK_I2C3>;
826 status = "disabled";
827 };
829 mmdc: mmdc@021b0000 {
830 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
831 reg = <0x021b0000 0x4000>;
832 };
834 rngb: rngb@021b4000 {
835 reg = <0x021b4000 0x4000>;
836 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
837 };
839 weim: weim@021b8000 {
840 reg = <0x021b8000 0x4000>;
841 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
842 };
844 ocotp: ocotp@021bc000 {
845 compatible = "fsl,imx6sl-ocotp", "syscon";
846 reg = <0x021bc000 0x4000>;
847 };
849 audmux: audmux@021d8000 {
850 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
851 reg = <0x021d8000 0x4000>;
852 status = "disabled";
853 };
854 };
855 };
856 };