2 * Hitex LPC4350 Evaluation Board
4 * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com>
6 * This code is released using a dual license strategy: BSD/GPL
7 * You can choose the licence that better fits your requirements.
9 * Released under the terms of 3-clause BSD License
10 * Released under the terms of GNU General Public License Version 2.0
15 #include "lpc18xx.dtsi"
16 #include "lpc4350.dtsi"
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
22 model = "Hitex LPC4350 Evaluation Board";
23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
37 device_type = "memory";
38 reg = <0x28000000 0x800000>; /* 8 MB */
42 compatible = "gpio-keys-polled";
45 poll-interval = <100>;
50 linux,code = <KEY_RIGHT>;
51 gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>;
56 linux,code = <KEY_UP>;
57 gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>;
63 linux,code = <KEY_ENTER>;
64 gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>;
69 linux,code = <KEY_LEFT>;
70 gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>;
75 linux,code = <KEY_DOWN>;
76 gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>;
81 linux,code = <KEY_F1>;
82 gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>;
87 linux,code = <KEY_F2>;
88 gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>;
93 linux,code = <KEY_F3>;
94 gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>;
99 compatible = "gpio-leds";
103 gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>;
104 linux,default-trigger = "heartbeat";
109 gpios = <&pca_gpio 1 GPIO_ACTIVE_LOW>;
114 gpios = <&pca_gpio 2 GPIO_ACTIVE_LOW>;
119 gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>;
127 pins = "p2_9", "p2_10", "p2_11", "p2_12",
128 "p2_13", "p1_0", "p1_1", "p1_2",
129 "p2_8", "p2_7", "p2_6", "p2_2",
130 "p2_1", "p2_0", "p6_8", "p6_7",
131 "pd_16", "pd_15", "pe_0", "pe_1",
132 "pe_2", "pe_3", "pe_4", "pa_4";
137 input-schmitt-disable;
141 pins = "p1_7", "p1_8", "p1_9", "p1_10",
142 "p1_11", "p1_12", "p1_13", "p1_14",
143 "p5_4", "p5_5", "p5_6", "p5_7",
144 "p5_0", "p5_1", "p5_2", "p5_3";
149 input-schmitt-disable;
153 pins = "p1_6", "p1_3";
158 input-schmitt-disable;
162 pins = "p1_4", "p6_6", "pd_13", "pd_10";
167 input-schmitt-disable;
171 pins = "p1_5", "pd_12";
176 input-schmitt-disable;
179 emc_sdram_dqm0_3_cfg {
180 pins = "p6_12", "p6_10", "pd_0", "pe_13";
185 input-schmitt-disable;
188 emc_sdram_ras_cas_cfg {
189 pins = "p6_5", "p6_4";
194 input-schmitt-disable;
197 emc_sdram_dycs0_cfg {
203 input-schmitt-disable;
212 input-schmitt-disable;
215 emc_sdram_clock_cfg {
216 pins = "clk0", "clk1", "clk2", "clk3";
221 input-schmitt-disable;
225 enet_mii_pins: enet-mii-pins {
226 enet_mii_rxd0_3_cfg {
227 pins = "p1_15", "p0_0", "p9_3", "p9_2";
233 enet_mii_txd0_3_cfg {
234 pins = "p1_18", "p1_20", "p9_4", "p9_5";
239 enet_mii_crs_col_cfg {
240 pins = "p9_0", "p9_6";
246 enet_mii_rx_clk_dv_er_cfg {
247 pins = "pc_0", "p1_16", "p9_1";
253 enet_mii_tx_clk_en_cfg {
254 pins = "p1_19", "p0_1";
274 i2c0_pins: i2c0-pins {
276 pins = "i2c0_scl", "i2c0_sda";
282 spifi_pins: spifi-pins {
289 input-schmitt-disable;
292 spifi_mosi_miso_sio2_3_cfg {
293 pins = "p3_7", "p3_6", "p3_5", "p3_4";
298 input-schmitt-disable;
307 input-schmitt-disable;
311 uart0_pins: uart0-pins {
315 input-schmitt-disable;
330 pinctrl-names = "default";
331 pinctrl-0 = <&emc_pins>;
334 #address-cells = <2>;
339 mpmc,memory-width = <16>;
341 mpmc,write-enable-delay = <0>;
342 mpmc,output-enable-delay = <0>;
343 mpmc,read-access-delay = <70>;
344 mpmc,page-mode-read-delay = <70>;
347 compatible = "sst,sst39vf320", "cfi-flash";
348 reg = <0 0 0x400000>;
350 #address-cells = <1>;
354 label = "bootloader";
355 reg = <0x000000 0x040000>; /* 256 KiB */
360 reg = <0x040000 0x2C0000>; /* 2.75 MiB */
365 reg = <0x300000 0x100000>; /* 1 MiB */
371 #address-cells = <2>;
376 mpmc,memory-width = <16>;
378 mpmc,write-enable-delay = <0>;
379 mpmc,output-enable-delay = <30>;
380 mpmc,read-access-delay = <90>;
381 mpmc,page-mode-read-delay = <55>;
382 mpmc,write-access-delay = <55>;
383 mpmc,turn-round-delay = <55>;
386 compatible = "mmio-sram";
387 reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */
393 clock-frequency = <25000000>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&i2c0_pins>;
400 clock-frequency = <400000>;
402 /* NXP SE97BTP with temperature sensor + eeprom */
404 compatible = "nxp,jc42";
409 compatible = "nxp,24c02";
414 compatible = "nxp,pca9673";
424 pinctrl-names = "default";
425 pinctrl-0 = <&enet_mii_pins>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&spifi_pins>;
434 compatible = "jedec,spi-nor";
435 spi-rx-bus-width = <4>;
436 #address-cells = <1>;
440 label = "bootloader";
441 reg = <0x000000 0x040000>; /* 256 KiB */
446 reg = <0x040000 0x2c0000>; /* 2.75 MiB */
451 reg = <0x300000 0x500000>; /* 5 MiB */
458 pinctrl-names = "default";
459 pinctrl-0 = <&uart0_pins>;