arch/arm/boot/dts/versatile-ab.dts

   1 /dts-v1/;
   2 /include/ "skeleton.dtsi"
   3
   4 / {
   5         model = "ARM Versatile AB";
   6         compatible = "arm,versatile-ab";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&vic>;
  10
  11         aliases {
  12                 serial0 = &uart0;
  13                 serial1 = &uart1;
  14                 serial2 = &uart2;
  15                 i2c0 = &i2c0;
  16         };
  17
  18         chosen {
  19                 stdout-path = &uart0;
  20         };
  21
  22         memory {
  23                 reg = <0x0 0x08000000>;
  24         };
  25
  26         xtal24mhz: xtal24mhz@24M {
  27                 #clock-cells = <0>;
  28                 compatible = "fixed-clock";
  29                 clock-frequency = <24000000>;
  30         };
  31
  32         core-module@10000000 {
  33                 compatible = "arm,core-module-versatile", "syscon";
  34                 reg = <0x10000000 0x200>;
  35
  36                 /* OSC1 on AB, OSC4 on PB */
  37                 osc1: cm_aux_osc@24M {
  38                         #clock-cells = <0>;
  39                         compatible = "arm,versatile-cm-auxosc";
  40                         clocks = <&xtal24mhz>;
  41                 };
  42
  43                 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
  44                 timclk: timclk@1M {
  45                         #clock-cells = <0>;
  46                         compatible = "fixed-factor-clock";
  47                         clock-div = <24>;
  48                         clock-mult = <1>;
  49                         clocks = <&xtal24mhz>;
  50                 };
  51
  52                 pclk: pclk@24M {
  53                         #clock-cells = <0>;
  54                         compatible = "fixed-factor-clock";
  55                         clock-div = <1>;
  56                         clock-mult = <1>;
  57                         clocks = <&xtal24mhz>;
  58                 };
  59         };
  60
  61         flash@34000000 {
  62                 compatible = "arm,versatile-flash";
  63                 reg = <0x34000000 0x4000000>;
  64                 bank-width = <4>;
  65         };
  66
  67         i2c0: i2c@10002000 {
  68                 #address-cells = <1>;
  69                 #size-cells = <0>;
  70                 compatible = "arm,versatile-i2c";
  71                 reg = <0x10002000 0x1000>;
  72
  73                 rtc@68 {
  74                         compatible = "dallas,ds1338";
  75                         reg = <0x68>;
  76                 };
  77         };
  78
  79         net@10010000 {
  80                 compatible = "smsc,lan91c111";
  81                 reg = <0x10010000 0x10000>;
  82                 interrupts = <25>;
  83         };
  84
  85         lcd@10008000 {
  86                 compatible = "arm,versatile-lcd";
  87                 reg = <0x10008000 0x1000>;
  88         };
  89
  90         amba {
  91                 compatible = "arm,amba-bus";
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges;
  95
  96                 vic: intc@10140000 {
  97                         compatible = "arm,versatile-vic";
  98                         interrupt-controller;
  99                         #interrupt-cells = <1>;
 100                         reg = <0x10140000 0x1000>;
 101                         clear-mask = <0xffffffff>;
 102                         valid-mask = <0xffffffff>;
 103                 };
 104
 105                 sic: intc@10003000 {
 106                         compatible = "arm,versatile-sic";
 107                         interrupt-controller;
 108                         #interrupt-cells = <1>;
 109                         reg = <0x10003000 0x1000>;
 110                         interrupt-parent = <&vic>;
 111                         interrupts = <31>; /* Cascaded to vic */
 112                         clear-mask = <0xffffffff>;
 113                         /*
 114                          * Valid interrupt lines mask according to
 115                          * table 4-36 page 4-50 of ARM DUI 0225D
 116                          */
 117                         valid-mask = <0x0760031b>;
 118                 };
 119
 120                 dma@10130000 {
 121                         compatible = "arm,pl081", "arm,primecell";
 122                         reg = <0x10130000 0x1000>;
 123                         interrupts = <17>;
 124                         clocks = <&pclk>;
 125                         clock-names = "apb_pclk";
 126                 };
 127
 128                 uart0: uart@101f1000 {
 129                         compatible = "arm,pl011", "arm,primecell";
 130                         reg = <0x101f1000 0x1000>;
 131                         interrupts = <12>;
 132                         clocks = <&xtal24mhz>, <&pclk>;
 133                         clock-names = "uartclk", "apb_pclk";
 134                 };
 135
 136                 uart1: uart@101f2000 {
 137                         compatible = "arm,pl011", "arm,primecell";
 138                         reg = <0x101f2000 0x1000>;
 139                         interrupts = <13>;
 140                         clocks = <&xtal24mhz>, <&pclk>;
 141                         clock-names = "uartclk", "apb_pclk";
 142                 };
 143
 144                 uart2: uart@101f3000 {
 145                         compatible = "arm,pl011", "arm,primecell";
 146                         reg = <0x101f3000 0x1000>;
 147                         interrupts = <14>;
 148                         clocks = <&xtal24mhz>, <&pclk>;
 149                         clock-names = "uartclk", "apb_pclk";
 150                 };
 151
 152                 smc@10100000 {
 153                         compatible = "arm,primecell";
 154                         reg = <0x10100000 0x1000>;
 155                         clocks = <&pclk>;
 156                         clock-names = "apb_pclk";
 157                 };
 158
 159                 mpmc@10110000 {
 160                         compatible = "arm,primecell";
 161                         reg = <0x10110000 0x1000>;
 162                         clocks = <&pclk>;
 163                         clock-names = "apb_pclk";
 164                 };
 165
 166                 display@10120000 {
 167                         compatible = "arm,pl110", "arm,primecell";
 168                         reg = <0x10120000 0x1000>;
 169                         interrupts = <16>;
 170                         clocks = <&osc1>, <&pclk>;
 171                         clock-names = "clcd", "apb_pclk";
 172                 };
 173
 174                 sctl@101e0000 {
 175                         compatible = "arm,primecell";
 176                         reg = <0x101e0000 0x1000>;
 177                         clocks = <&pclk>;
 178                         clock-names = "apb_pclk";
 179                 };
 180
 181                 watchdog@101e1000 {
 182                         compatible = "arm,primecell";
 183                         reg = <0x101e1000 0x1000>;
 184                         interrupts = <0>;
 185                         clocks = <&pclk>;
 186                         clock-names = "apb_pclk";
 187                 };
 188
 189                 timer@101e2000 {
 190                         compatible = "arm,sp804", "arm,primecell";
 191                         reg = <0x101e2000 0x1000>;
 192                         interrupts = <4>;
 193                         clocks = <&timclk>, <&timclk>, <&pclk>;
 194                         clock-names = "timer0", "timer1", "apb_pclk";
 195                 };
 196
 197                 timer@101e3000 {
 198                         compatible = "arm,sp804", "arm,primecell";
 199                         reg = <0x101e3000 0x1000>;
 200                         interrupts = <5>;
 201                         clocks = <&timclk>, <&timclk>, <&pclk>;
 202                         clock-names = "timer0", "timer1", "apb_pclk";
 203                 };
 204
 205                 gpio0: gpio@101e4000 {
 206                         compatible = "arm,pl061", "arm,primecell";
 207                         reg = <0x101e4000 0x1000>;
 208                         gpio-controller;
 209                         interrupts = <6>;
 210                         #gpio-cells = <2>;
 211                         interrupt-controller;
 212                         #interrupt-cells = <2>;
 213                         clocks = <&pclk>;
 214                         clock-names = "apb_pclk";
 215                 };
 216
 217                 gpio1: gpio@101e5000 {
 218                         compatible = "arm,pl061", "arm,primecell";
 219                         reg = <0x101e5000 0x1000>;
 220                         interrupts = <7>;
 221                         gpio-controller;
 222                         #gpio-cells = <2>;
 223                         interrupt-controller;
 224                         #interrupt-cells = <2>;
 225                         clocks = <&pclk>;
 226                         clock-names = "apb_pclk";
 227                 };
 228
 229                 rtc@101e8000 {
 230                         compatible = "arm,pl030", "arm,primecell";
 231                         reg = <0x101e8000 0x1000>;
 232                         interrupts = <10>;
 233                         clocks = <&pclk>;
 234                         clock-names = "apb_pclk";
 235                 };
 236
 237                 sci@101f0000 {
 238                         compatible = "arm,primecell";
 239                         reg = <0x101f0000 0x1000>;
 240                         interrupts = <15>;
 241                         clocks = <&pclk>;
 242                         clock-names = "apb_pclk";
 243                 };
 244
 245                 ssp@101f4000 {
 246                         compatible = "arm,pl022", "arm,primecell";
 247                         reg = <0x101f4000 0x1000>;
 248                         interrupts = <11>;
 249                         clocks = <&xtal24mhz>, <&pclk>;
 250                         clock-names = "SSPCLK", "apb_pclk";
 251                 };
 252
 253                 fpga {
 254                         compatible = "arm,versatile-fpga", "simple-bus";
 255                         #address-cells = <1>;
 256                         #size-cells = <1>;
 257                         ranges = <0 0x10000000 0x10000>;
 258
 259                         sysreg@0 {
 260                                 compatible = "arm,versatile-sysreg", "syscon";
 261                                 reg = <0x00000 0x1000>;
 262                         };
 263
 264                         aaci@4000 {
 265                                 compatible = "arm,primecell";
 266                                 reg = <0x4000 0x1000>;
 267                                 interrupts = <24>;
 268                                 clocks = <&pclk>;
 269                                 clock-names = "apb_pclk";
 270                         };
 271                         mmc@5000 {
 272                                 compatible = "arm,pl180", "arm,primecell";
 273                                 reg = <0x5000 0x1000>;
 274                                 interrupts-extended = <&vic 22 &sic 1>;
 275                                 clocks = <&xtal24mhz>, <&pclk>;
 276                                 clock-names = "mclk", "apb_pclk";
 277                         };
 278                         kmi@6000 {
 279                                 compatible = "arm,pl050", "arm,primecell";
 280                                 reg = <0x6000 0x1000>;
 281                                 interrupt-parent = <&sic>;
 282                                 interrupts = <3>;
 283                                 clocks = <&xtal24mhz>, <&pclk>;
 284                                 clock-names = "KMIREFCLK", "apb_pclk";
 285                         };
 286                         kmi@7000 {
 287                                 compatible = "arm,pl050", "arm,primecell";
 288                                 reg = <0x7000 0x1000>;
 289                                 interrupt-parent = <&sic>;
 290                                 interrupts = <4>;
 291                                 clocks = <&xtal24mhz>, <&pclk>;
 292                                 clock-names = "KMIREFCLK", "apb_pclk";
 293                         };
 294                 };
 295         };
 296 };