| blob | 1a5220e05109022dda87912a0145666176f670e0 |
1 /*
2 * Copyright (C) 2011 - 2014 Xilinx
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13 /include/ "skeleton.dtsi"
15 / {
16 compatible = "xlnx,zynq-7000";
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cpu@0 {
23 compatible = "arm,cortex-a9";
24 device_type = "cpu";
25 reg = <0>;
26 clocks = <&clkc 3>;
27 clock-latency = <1000>;
28 cpu0-supply = <®ulator_vccpint>;
29 operating-points = <
30 /* kHz uV */
31 666667 1000000
32 333334 1000000
33 >;
34 };
36 cpu@1 {
37 compatible = "arm,cortex-a9";
38 device_type = "cpu";
39 reg = <1>;
40 clocks = <&clkc 3>;
41 };
42 };
44 pmu {
45 compatible = "arm,cortex-a9-pmu";
46 interrupts = <0 5 4>, <0 6 4>;
47 interrupt-parent = <&intc>;
48 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
49 };
51 regulator_vccpint: fixedregulator@0 {
52 compatible = "regulator-fixed";
53 regulator-name = "VCCPINT";
54 regulator-min-microvolt = <1000000>;
55 regulator-max-microvolt = <1000000>;
56 regulator-boot-on;
57 regulator-always-on;
58 };
60 amba: amba {
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
64 interrupt-parent = <&intc>;
65 ranges;
67 adc: adc@f8007100 {
68 compatible = "xlnx,zynq-xadc-1.00.a";
69 reg = <0xf8007100 0x20>;
70 interrupts = <0 7 4>;
71 interrupt-parent = <&intc>;
72 clocks = <&clkc 12>;
73 };
75 can0: can@e0008000 {
76 compatible = "xlnx,zynq-can-1.0";
77 status = "disabled";
78 clocks = <&clkc 19>, <&clkc 36>;
79 clock-names = "can_clk", "pclk";
80 reg = <0xe0008000 0x1000>;
81 interrupts = <0 28 4>;
82 interrupt-parent = <&intc>;
83 tx-fifo-depth = <0x40>;
84 rx-fifo-depth = <0x40>;
85 };
87 can1: can@e0009000 {
88 compatible = "xlnx,zynq-can-1.0";
89 status = "disabled";
90 clocks = <&clkc 20>, <&clkc 37>;
91 clock-names = "can_clk", "pclk";
92 reg = <0xe0009000 0x1000>;
93 interrupts = <0 51 4>;
94 interrupt-parent = <&intc>;
95 tx-fifo-depth = <0x40>;
96 rx-fifo-depth = <0x40>;
97 };
99 gpio0: gpio@e000a000 {
100 compatible = "xlnx,zynq-gpio-1.0";
101 #gpio-cells = <2>;
102 clocks = <&clkc 42>;
103 gpio-controller;
104 interrupt-parent = <&intc>;
105 interrupts = <0 20 4>;
106 reg = <0xe000a000 0x1000>;
107 };
109 i2c0: i2c@e0004000 {
110 compatible = "cdns,i2c-r1p10";
111 status = "disabled";
112 clocks = <&clkc 38>;
113 interrupt-parent = <&intc>;
114 interrupts = <0 25 4>;
115 reg = <0xe0004000 0x1000>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 };
120 i2c1: i2c@e0005000 {
121 compatible = "cdns,i2c-r1p10";
122 status = "disabled";
123 clocks = <&clkc 39>;
124 interrupt-parent = <&intc>;
125 interrupts = <0 48 4>;
126 reg = <0xe0005000 0x1000>;
127 #address-cells = <1>;
128 #size-cells = <0>;
129 };
131 intc: interrupt-controller@f8f01000 {
132 compatible = "arm,cortex-a9-gic";
133 #interrupt-cells = <3>;
134 interrupt-controller;
135 reg = <0xF8F01000 0x1000>,
136 <0xF8F00100 0x100>;
137 };
139 L2: cache-controller@f8f02000 {
140 compatible = "arm,pl310-cache";
141 reg = <0xF8F02000 0x1000>;
142 interrupts = <0 2 4>;
143 arm,data-latency = <3 2 2>;
144 arm,tag-latency = <2 2 2>;
145 cache-unified;
146 cache-level = <2>;
147 };
149 mc: memory-controller@f8006000 {
150 compatible = "xlnx,zynq-ddrc-a05";
151 reg = <0xf8006000 0x1000>;
152 };
154 uart0: serial@e0000000 {
155 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
156 status = "disabled";
157 clocks = <&clkc 23>, <&clkc 40>;
158 clock-names = "uart_clk", "pclk";
159 reg = <0xE0000000 0x1000>;
160 interrupts = <0 27 4>;
161 };
163 uart1: serial@e0001000 {
164 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
165 status = "disabled";
166 clocks = <&clkc 24>, <&clkc 41>;
167 clock-names = "uart_clk", "pclk";
168 reg = <0xE0001000 0x1000>;
169 interrupts = <0 50 4>;
170 };
172 spi0: spi@e0006000 {
173 compatible = "xlnx,zynq-spi-r1p6";
174 reg = <0xe0006000 0x1000>;
175 status = "disabled";
176 interrupt-parent = <&intc>;
177 interrupts = <0 26 4>;
178 clocks = <&clkc 25>, <&clkc 34>;
179 clock-names = "ref_clk", "pclk";
180 #address-cells = <1>;
181 #size-cells = <0>;
182 };
184 spi1: spi@e0007000 {
185 compatible = "xlnx,zynq-spi-r1p6";
186 reg = <0xe0007000 0x1000>;
187 status = "disabled";
188 interrupt-parent = <&intc>;
189 interrupts = <0 49 4>;
190 clocks = <&clkc 26>, <&clkc 35>;
191 clock-names = "ref_clk", "pclk";
192 #address-cells = <1>;
193 #size-cells = <0>;
194 };
196 gem0: ethernet@e000b000 {
197 compatible = "cdns,zynq-gem", "cdns,gem";
198 reg = <0xe000b000 0x1000>;
199 status = "disabled";
200 interrupts = <0 22 4>;
201 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
202 clock-names = "pclk", "hclk", "tx_clk";
203 #address-cells = <1>;
204 #size-cells = <0>;
205 };
207 gem1: ethernet@e000c000 {
208 compatible = "cdns,zynq-gem", "cdns,gem";
209 reg = <0xe000c000 0x1000>;
210 status = "disabled";
211 interrupts = <0 45 4>;
212 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
213 clock-names = "pclk", "hclk", "tx_clk";
214 #address-cells = <1>;
215 #size-cells = <0>;
216 };
218 sdhci0: sdhci@e0100000 {
219 compatible = "arasan,sdhci-8.9a";
220 status = "disabled";
221 clock-names = "clk_xin", "clk_ahb";
222 clocks = <&clkc 21>, <&clkc 32>;
223 interrupt-parent = <&intc>;
224 interrupts = <0 24 4>;
225 reg = <0xe0100000 0x1000>;
226 };
228 sdhci1: sdhci@e0101000 {
229 compatible = "arasan,sdhci-8.9a";
230 status = "disabled";
231 clock-names = "clk_xin", "clk_ahb";
232 clocks = <&clkc 22>, <&clkc 33>;
233 interrupt-parent = <&intc>;
234 interrupts = <0 47 4>;
235 reg = <0xe0101000 0x1000>;
236 };
238 slcr: slcr@f8000000 {
239 #address-cells = <1>;
240 #size-cells = <1>;
241 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
242 reg = <0xF8000000 0x1000>;
243 ranges;
244 clkc: clkc@100 {
245 #clock-cells = <1>;
246 compatible = "xlnx,ps7-clkc";
247 fclk-enable = <0>;
248 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
249 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
250 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
251 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
252 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
253 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
254 "gem1_aper", "sdio0_aper", "sdio1_aper",
255 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
256 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
257 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
258 "dbg_trc", "dbg_apb";
259 reg = <0x100 0x100>;
260 };
262 rstc: rstc@200 {
263 compatible = "xlnx,zynq-reset";
264 reg = <0x200 0x48>;
265 #reset-cells = <1>;
266 syscon = <&slcr>;
267 };
269 pinctrl0: pinctrl@700 {
270 compatible = "xlnx,pinctrl-zynq";
271 reg = <0x700 0x200>;
272 syscon = <&slcr>;
273 };
274 };
276 dmac_s: dmac@f8003000 {
277 compatible = "arm,pl330", "arm,primecell";
278 reg = <0xf8003000 0x1000>;
279 interrupt-parent = <&intc>;
280 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
281 "dma4", "dma5", "dma6", "dma7";
282 interrupts = <0 13 4>,
283 <0 14 4>, <0 15 4>,
284 <0 16 4>, <0 17 4>,
285 <0 40 4>, <0 41 4>,
286 <0 42 4>, <0 43 4>;
287 #dma-cells = <1>;
288 #dma-channels = <8>;
289 #dma-requests = <4>;
290 clocks = <&clkc 27>;
291 clock-names = "apb_pclk";
292 };
294 devcfg: devcfg@f8007000 {
295 compatible = "xlnx,zynq-devcfg-1.0";
296 reg = <0xf8007000 0x100>;
297 interrupt-parent = <&intc>;
298 interrupts = <0 8 4>;
299 clocks = <&clkc 12>;
300 clock-names = "ref_clk";
301 syscon = <&slcr>;
302 };
304 global_timer: timer@f8f00200 {
305 compatible = "arm,cortex-a9-global-timer";
306 reg = <0xf8f00200 0x20>;
307 interrupts = <1 11 0x301>;
308 interrupt-parent = <&intc>;
309 clocks = <&clkc 4>;
310 };
312 ttc0: timer@f8001000 {
313 interrupt-parent = <&intc>;
314 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
315 compatible = "cdns,ttc";
316 clocks = <&clkc 6>;
317 reg = <0xF8001000 0x1000>;
318 };
320 ttc1: timer@f8002000 {
321 interrupt-parent = <&intc>;
322 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
323 compatible = "cdns,ttc";
324 clocks = <&clkc 6>;
325 reg = <0xF8002000 0x1000>;
326 };
328 scutimer: timer@f8f00600 {
329 interrupt-parent = <&intc>;
330 interrupts = <1 13 0x301>;
331 compatible = "arm,cortex-a9-twd-timer";
332 reg = <0xf8f00600 0x20>;
333 clocks = <&clkc 4>;
334 };
336 usb0: usb@e0002000 {
337 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
338 status = "disabled";
339 clocks = <&clkc 28>;
340 interrupt-parent = <&intc>;
341 interrupts = <0 21 4>;
342 reg = <0xe0002000 0x1000>;
343 phy_type = "ulpi";
344 };
346 usb1: usb@e0003000 {
347 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
348 status = "disabled";
349 clocks = <&clkc 29>;
350 interrupt-parent = <&intc>;
351 interrupts = <0 44 4>;
352 reg = <0xe0003000 0x1000>;
353 phy_type = "ulpi";
354 };
356 watchdog0: watchdog@f8005000 {
357 clocks = <&clkc 45>;
358 compatible = "cdns,wdt-r1p2";
359 interrupt-parent = <&intc>;
360 interrupts = <0 9 1>;
361 reg = <0xf8005000 0x1000>;
362 timeout-sec = <10>;
363 };
364 };
365 };