arch/arm64/include/asm/arch_gicv3.h

   1 /*
   2  * arch/arm64/include/asm/arch_gicv3.h
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #ifndef __ASM_ARCH_GICV3_H
  19 #define __ASM_ARCH_GICV3_H
  20
  21 #include <asm/sysreg.h>
  22
  23 #define ICC_EOIR1_EL1                   sys_reg(3, 0, 12, 12, 1)
  24 #define ICC_DIR_EL1                     sys_reg(3, 0, 12, 11, 1)
  25 #define ICC_IAR1_EL1                    sys_reg(3, 0, 12, 12, 0)
  26 #define ICC_SGI1R_EL1                   sys_reg(3, 0, 12, 11, 5)
  27 #define ICC_PMR_EL1                     sys_reg(3, 0, 4, 6, 0)
  28 #define ICC_CTLR_EL1                    sys_reg(3, 0, 12, 12, 4)
  29 #define ICC_SRE_EL1                     sys_reg(3, 0, 12, 12, 5)
  30 #define ICC_GRPEN1_EL1                  sys_reg(3, 0, 12, 12, 7)
  31
  32 #define ICC_SRE_EL2                     sys_reg(3, 4, 12, 9, 5)
  33
  34 /*
  35  * System register definitions
  36  */
  37 #define ICH_VSEIR_EL2                   sys_reg(3, 4, 12, 9, 4)
  38 #define ICH_HCR_EL2                     sys_reg(3, 4, 12, 11, 0)
  39 #define ICH_VTR_EL2                     sys_reg(3, 4, 12, 11, 1)
  40 #define ICH_MISR_EL2                    sys_reg(3, 4, 12, 11, 2)
  41 #define ICH_EISR_EL2                    sys_reg(3, 4, 12, 11, 3)
  42 #define ICH_ELSR_EL2                    sys_reg(3, 4, 12, 11, 5)
  43 #define ICH_VMCR_EL2                    sys_reg(3, 4, 12, 11, 7)
  44
  45 #define __LR0_EL2(x)                    sys_reg(3, 4, 12, 12, x)
  46 #define __LR8_EL2(x)                    sys_reg(3, 4, 12, 13, x)
  47
  48 #define ICH_LR0_EL2                     __LR0_EL2(0)
  49 #define ICH_LR1_EL2                     __LR0_EL2(1)
  50 #define ICH_LR2_EL2                     __LR0_EL2(2)
  51 #define ICH_LR3_EL2                     __LR0_EL2(3)
  52 #define ICH_LR4_EL2                     __LR0_EL2(4)
  53 #define ICH_LR5_EL2                     __LR0_EL2(5)
  54 #define ICH_LR6_EL2                     __LR0_EL2(6)
  55 #define ICH_LR7_EL2                     __LR0_EL2(7)
  56 #define ICH_LR8_EL2                     __LR8_EL2(0)
  57 #define ICH_LR9_EL2                     __LR8_EL2(1)
  58 #define ICH_LR10_EL2                    __LR8_EL2(2)
  59 #define ICH_LR11_EL2                    __LR8_EL2(3)
  60 #define ICH_LR12_EL2                    __LR8_EL2(4)
  61 #define ICH_LR13_EL2                    __LR8_EL2(5)
  62 #define ICH_LR14_EL2                    __LR8_EL2(6)
  63 #define ICH_LR15_EL2                    __LR8_EL2(7)
  64
  65 #define __AP0Rx_EL2(x)                  sys_reg(3, 4, 12, 8, x)
  66 #define ICH_AP0R0_EL2                   __AP0Rx_EL2(0)
  67 #define ICH_AP0R1_EL2                   __AP0Rx_EL2(1)
  68 #define ICH_AP0R2_EL2                   __AP0Rx_EL2(2)
  69 #define ICH_AP0R3_EL2                   __AP0Rx_EL2(3)
  70
  71 #define __AP1Rx_EL2(x)                  sys_reg(3, 4, 12, 9, x)
  72 #define ICH_AP1R0_EL2                   __AP1Rx_EL2(0)
  73 #define ICH_AP1R1_EL2                   __AP1Rx_EL2(1)
  74 #define ICH_AP1R2_EL2                   __AP1Rx_EL2(2)
  75 #define ICH_AP1R3_EL2                   __AP1Rx_EL2(3)
  76
  77 #ifndef __ASSEMBLY__
  78
  79 #include <linux/stringify.h>
  80 #include <asm/barrier.h>
  81
  82 /*
  83  * Low-level accessors
  84  *
  85  * These system registers are 32 bits, but we make sure that the compiler
  86  * sets the GP register's most significant bits to 0 with an explicit cast.
  87  */
  88
  89 static inline void gic_write_eoir(u32 irq)
  90 {
  91         asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" ((u64)irq));
  92         isb();
  93 }
  94
  95 static inline void gic_write_dir(u32 irq)
  96 {
  97         asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" ((u64)irq));
  98         isb();
  99 }
 100
 101 static inline u64 gic_read_iar_common(void)
 102 {
 103         u64 irqstat;
 104
 105         asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
 106         return irqstat;
 107 }
 108
 109 /*
 110  * Cavium ThunderX erratum 23154
 111  *
 112  * The gicv3 of ThunderX requires a modified version for reading the
 113  * IAR status to ensure data synchronization (access to icc_iar1_el1
 114  * is not sync'ed before and after).
 115  */
 116 static inline u64 gic_read_iar_cavium_thunderx(void)
 117 {
 118         u64 irqstat;
 119
 120         asm volatile(
 121                 "nop;nop;nop;nop\n\t"
 122                 "nop;nop;nop;nop\n\t"
 123                 "mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t"
 124                 "nop;nop;nop;nop"
 125                 : "=r" (irqstat));
 126         mb();
 127
 128         return irqstat;
 129 }
 130
 131 static inline void gic_write_pmr(u32 val)
 132 {
 133         asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val));
 134 }
 135
 136 static inline void gic_write_ctlr(u32 val)
 137 {
 138         asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" ((u64)val));
 139         isb();
 140 }
 141
 142 static inline void gic_write_grpen1(u32 val)
 143 {
 144         asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" ((u64)val));
 145         isb();
 146 }
 147
 148 static inline void gic_write_sgi1r(u64 val)
 149 {
 150         asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
 151 }
 152
 153 static inline u32 gic_read_sre(void)
 154 {
 155         u64 val;
 156
 157         asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
 158         return val;
 159 }
 160
 161 static inline void gic_write_sre(u32 val)
 162 {
 163         asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" ((u64)val));
 164         isb();
 165 }
 166
 167 #define gic_read_typer(c)               readq_relaxed(c)
 168 #define gic_write_irouter(v, c)         writeq_relaxed(v, c)
 169
 170 #endif /* __ASSEMBLY__ */
 171 #endif /* __ASM_ARCH_GICV3_H */